[NFC][LLVM][AArch64] Cleanup pass initialization for AArch64 (#134315)
- Remove calls to pass initialization from pass constructors. - https://github.com/llvm/llvm-project/issues/111767
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@ -81,9 +81,7 @@ class AArch64A53Fix835769 : public MachineFunctionPass {
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public:
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static char ID;
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explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {
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initializeAArch64A53Fix835769Pass(*PassRegistry::getPassRegistry());
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}
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explicit AArch64A53Fix835769() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &F) override;
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@ -112,9 +112,7 @@ class AArch64A57FPLoadBalancing : public MachineFunctionPass {
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public:
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static char ID;
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explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {
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initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry());
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}
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explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &F) override;
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@ -82,9 +82,7 @@ private:
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public:
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static char ID; // Pass identification, replacement for typeid.
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explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {
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initializeAArch64AdvSIMDScalarPass(*PassRegistry::getPassRegistry());
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}
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explicit AArch64AdvSIMDScalar() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &F) override;
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@ -63,9 +63,7 @@ struct ThunkArgInfo {
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class AArch64Arm64ECCallLowering : public ModulePass {
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public:
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static char ID;
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AArch64Arm64ECCallLowering() : ModulePass(ID) {
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initializeAArch64Arm64ECCallLoweringPass(*PassRegistry::getPassRegistry());
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}
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AArch64Arm64ECCallLowering() : ModulePass(ID) {}
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Function *buildExitThunk(FunctionType *FnTy, AttributeList Attrs);
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Function *buildEntryThunk(Function *F);
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@ -47,9 +47,7 @@ class AArch64CompressJumpTables : public MachineFunctionPass {
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public:
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static char ID;
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AArch64CompressJumpTables() : MachineFunctionPass(ID) {
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initializeAArch64CompressJumpTablesPass(*PassRegistry::getPassRegistry());
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}
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AArch64CompressJumpTables() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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@ -52,9 +52,7 @@ class AArch64CondBrTuning : public MachineFunctionPass {
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public:
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static char ID;
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AArch64CondBrTuning() : MachineFunctionPass(ID) {
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initializeAArch64CondBrTuningPass(*PassRegistry::getPassRegistry());
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}
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AArch64CondBrTuning() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return AARCH64_CONDBR_TUNING_NAME; }
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@ -103,9 +103,7 @@ public:
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static char ID;
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AArch64ConditionOptimizer() : MachineFunctionPass(ID) {
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initializeAArch64ConditionOptimizerPass(*PassRegistry::getPassRegistry());
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}
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AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
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@ -771,9 +771,7 @@ class AArch64ConditionalCompares : public MachineFunctionPass {
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public:
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static char ID;
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AArch64ConditionalCompares() : MachineFunctionPass(ID) {
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initializeAArch64ConditionalComparesPass(*PassRegistry::getPassRegistry());
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}
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AArch64ConditionalCompares() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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@ -40,10 +40,7 @@ private:
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void processMachineBasicBlock(MachineBasicBlock &MBB);
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public:
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static char ID; // Pass identification, replacement for typeid.
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AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
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initializeAArch64DeadRegisterDefinitionsPass(
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*PassRegistry::getPassRegistry());
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}
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AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &F) override;
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@ -50,9 +50,7 @@ public:
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static char ID;
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AArch64ExpandPseudo() : MachineFunctionPass(ID) {
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initializeAArch64ExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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AArch64ExpandPseudo() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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@ -124,9 +124,7 @@ using LdStPairFlags = struct LdStPairFlags {
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struct AArch64LoadStoreOpt : public MachineFunctionPass {
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static char ID;
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AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
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initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
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}
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AArch64LoadStoreOpt() : MachineFunctionPass(ID) {}
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AliasAnalysis *AA;
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const AArch64InstrInfo *TII;
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@ -73,10 +73,7 @@ class AArch64LowerHomogeneousPrologEpilog : public ModulePass {
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public:
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static char ID;
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AArch64LowerHomogeneousPrologEpilog() : ModulePass(ID) {
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initializeAArch64LowerHomogeneousPrologEpilogPass(
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*PassRegistry::getPassRegistry());
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}
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AArch64LowerHomogeneousPrologEpilog() : ModulePass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<MachineModuleInfoWrapperPass>();
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AU.addPreserved<MachineModuleInfoWrapperPass>();
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@ -84,9 +84,7 @@ namespace {
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struct AArch64MIPeepholeOpt : public MachineFunctionPass {
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static char ID;
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AArch64MIPeepholeOpt() : MachineFunctionPass(ID) {
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initializeAArch64MIPeepholeOptPass(*PassRegistry::getPassRegistry());
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}
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AArch64MIPeepholeOpt() : MachineFunctionPass(ID) {}
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const AArch64InstrInfo *TII;
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const AArch64RegisterInfo *TRI;
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@ -21,9 +21,7 @@ namespace {
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struct AArch64PostCoalescer : public MachineFunctionPass {
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static char ID;
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AArch64PostCoalescer() : MachineFunctionPass(ID) {
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initializeAArch64PostCoalescerPass(*PassRegistry::getPassRegistry());
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}
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AArch64PostCoalescer() : MachineFunctionPass(ID) {}
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LiveIntervals *LIS;
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MachineRegisterInfo *MRI;
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@ -108,9 +108,7 @@ public:
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static char ID;
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AArch64PromoteConstant() : ModulePass(ID) {
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initializeAArch64PromoteConstantPass(*PassRegistry::getPassRegistry());
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}
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AArch64PromoteConstant() : ModulePass(ID) {}
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StringRef getPassName() const override { return "AArch64 Promote Constant"; }
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@ -78,10 +78,7 @@ class AArch64RedundantCopyElimination : public MachineFunctionPass {
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public:
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static char ID;
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AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {
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initializeAArch64RedundantCopyEliminationPass(
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*PassRegistry::getPassRegistry());
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}
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AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {}
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struct RegImm {
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MCPhysReg Reg;
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@ -150,9 +150,7 @@ struct AArch64SIMDInstrOpt : public MachineFunctionPass {
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// The maximum of N is curently 10 and it is for ST4 case.
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static const unsigned MaxNumRepl = 10;
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AArch64SIMDInstrOpt() : MachineFunctionPass(ID) {
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initializeAArch64SIMDInstrOptPass(*PassRegistry::getPassRegistry());
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}
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AArch64SIMDInstrOpt() : MachineFunctionPass(ID) {}
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/// Based only on latency of instructions, determine if it is cost efficient
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/// to replace the instruction InstDesc by the instructions stored in the
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@ -126,9 +126,7 @@ public:
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static char ID;
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AArch64SpeculationHardening() : MachineFunctionPass(ID) {
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initializeAArch64SpeculationHardeningPass(*PassRegistry::getPassRegistry());
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}
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AArch64SpeculationHardening() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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@ -309,9 +309,7 @@ public:
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: FunctionPass(ID),
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MergeInit(ClMergeInit.getNumOccurrences() ? ClMergeInit : !IsOptNone),
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UseStackSafety(ClUseStackSafety.getNumOccurrences() ? ClUseStackSafety
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: !IsOptNone) {
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initializeAArch64StackTaggingPass(*PassRegistry::getPassRegistry());
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}
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: !IsOptNone) {}
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void tagAlloca(AllocaInst *AI, Instruction *InsertBefore, Value *Ptr,
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uint64_t Size);
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@ -62,9 +62,7 @@ class AArch64StackTaggingPreRA : public MachineFunctionPass {
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public:
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static char ID;
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AArch64StackTaggingPreRA() : MachineFunctionPass(ID) {
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initializeAArch64StackTaggingPreRAPass(*PassRegistry::getPassRegistry());
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}
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AArch64StackTaggingPreRA() : MachineFunctionPass(ID) {}
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bool mayUseUncheckedLoadStore();
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void uncheckUsesOf(unsigned TaggedReg, int FI);
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@ -38,9 +38,7 @@ class AArch64StorePairSuppress : public MachineFunctionPass {
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public:
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static char ID;
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AArch64StorePairSuppress() : MachineFunctionPass(ID) {
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initializeAArch64StorePairSuppressPass(*PassRegistry::getPassRegistry());
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}
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AArch64StorePairSuppress() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return STPSUPPRESS_PASS_NAME; }
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@ -230,45 +230,46 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64Target() {
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RegisterTargetMachine<AArch64leTargetMachine> Z(getTheARM64Target());
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RegisterTargetMachine<AArch64leTargetMachine> W(getTheARM64_32Target());
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RegisterTargetMachine<AArch64leTargetMachine> V(getTheAArch64_32Target());
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auto PR = PassRegistry::getPassRegistry();
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initializeGlobalISel(*PR);
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initializeAArch64A53Fix835769Pass(*PR);
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initializeAArch64A57FPLoadBalancingPass(*PR);
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initializeAArch64AdvSIMDScalarPass(*PR);
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initializeAArch64BranchTargetsPass(*PR);
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initializeAArch64CollectLOHPass(*PR);
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initializeAArch64CompressJumpTablesPass(*PR);
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initializeAArch64ConditionalComparesPass(*PR);
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initializeAArch64ConditionOptimizerPass(*PR);
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initializeAArch64DeadRegisterDefinitionsPass(*PR);
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initializeAArch64ExpandPseudoPass(*PR);
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initializeAArch64LoadStoreOptPass(*PR);
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initializeAArch64MIPeepholeOptPass(*PR);
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initializeAArch64SIMDInstrOptPass(*PR);
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initializeAArch64O0PreLegalizerCombinerPass(*PR);
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initializeAArch64PreLegalizerCombinerPass(*PR);
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initializeAArch64PointerAuthPass(*PR);
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initializeAArch64PostCoalescerPass(*PR);
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initializeAArch64PostLegalizerCombinerPass(*PR);
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initializeAArch64PostLegalizerLoweringPass(*PR);
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initializeAArch64PostSelectOptimizePass(*PR);
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initializeAArch64PromoteConstantPass(*PR);
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initializeAArch64RedundantCopyEliminationPass(*PR);
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initializeAArch64StorePairSuppressPass(*PR);
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initializeFalkorHWPFFixPass(*PR);
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initializeFalkorMarkStridedAccessesLegacyPass(*PR);
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initializeLDTLSCleanupPass(*PR);
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initializeKCFIPass(*PR);
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initializeSMEABIPass(*PR);
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initializeSMEPeepholeOptPass(*PR);
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initializeSVEIntrinsicOptsPass(*PR);
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initializeAArch64SpeculationHardeningPass(*PR);
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initializeAArch64SLSHardeningPass(*PR);
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initializeAArch64StackTaggingPass(*PR);
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initializeAArch64StackTaggingPreRAPass(*PR);
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initializeAArch64LowerHomogeneousPrologEpilogPass(*PR);
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initializeAArch64DAGToDAGISelLegacyPass(*PR);
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initializeAArch64CondBrTuningPass(*PR);
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auto &PR = *PassRegistry::getPassRegistry();
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initializeGlobalISel(PR);
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initializeAArch64A53Fix835769Pass(PR);
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initializeAArch64A57FPLoadBalancingPass(PR);
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initializeAArch64AdvSIMDScalarPass(PR);
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initializeAArch64BranchTargetsPass(PR);
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initializeAArch64CollectLOHPass(PR);
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initializeAArch64CompressJumpTablesPass(PR);
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initializeAArch64ConditionalComparesPass(PR);
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initializeAArch64ConditionOptimizerPass(PR);
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initializeAArch64DeadRegisterDefinitionsPass(PR);
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initializeAArch64ExpandPseudoPass(PR);
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initializeAArch64LoadStoreOptPass(PR);
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initializeAArch64MIPeepholeOptPass(PR);
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initializeAArch64SIMDInstrOptPass(PR);
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initializeAArch64O0PreLegalizerCombinerPass(PR);
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initializeAArch64PreLegalizerCombinerPass(PR);
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initializeAArch64PointerAuthPass(PR);
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initializeAArch64PostCoalescerPass(PR);
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initializeAArch64PostLegalizerCombinerPass(PR);
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initializeAArch64PostLegalizerLoweringPass(PR);
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initializeAArch64PostSelectOptimizePass(PR);
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initializeAArch64PromoteConstantPass(PR);
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initializeAArch64RedundantCopyEliminationPass(PR);
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initializeAArch64StorePairSuppressPass(PR);
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initializeFalkorHWPFFixPass(PR);
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initializeFalkorMarkStridedAccessesLegacyPass(PR);
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initializeLDTLSCleanupPass(PR);
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initializeKCFIPass(PR);
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initializeSMEABIPass(PR);
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initializeSMEPeepholeOptPass(PR);
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initializeSVEIntrinsicOptsPass(PR);
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initializeAArch64SpeculationHardeningPass(PR);
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initializeAArch64SLSHardeningPass(PR);
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initializeAArch64StackTaggingPass(PR);
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initializeAArch64StackTaggingPreRAPass(PR);
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initializeAArch64LowerHomogeneousPrologEpilogPass(PR);
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initializeAArch64DAGToDAGISelLegacyPass(PR);
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initializeAArch64CondBrTuningPass(PR);
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initializeAArch64Arm64ECCallLoweringPass(PR);
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}
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void AArch64TargetMachine::reset() { SubtargetMap.clear(); }
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@ -333,8 +334,9 @@ getEffectiveAArch64CodeModel(const Triple &TT,
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*CM != CodeModel::Large) {
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report_fatal_error(
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"Only small, tiny and large code models are allowed on AArch64");
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} else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF())
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} else if (*CM == CodeModel::Tiny && !TT.isOSBinFormatELF()) {
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report_fatal_error("tiny code model is only supported on ELF");
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}
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return *CM;
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}
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// The default MCJIT memory managers make no guarantees about where they can
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@ -142,8 +142,6 @@ void AArch64O0PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AArch64O0PreLegalizerCombiner::AArch64O0PreLegalizerCombiner()
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: MachineFunctionPass(ID) {
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initializeAArch64O0PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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if (!RuleConfig.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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@ -533,8 +533,6 @@ void AArch64PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
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: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
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initializeAArch64PostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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if (!RuleConfig.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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@ -1322,8 +1322,6 @@ void AArch64PostLegalizerLowering::getAnalysisUsage(AnalysisUsage &AU) const {
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AArch64PostLegalizerLowering::AArch64PostLegalizerLowering()
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: MachineFunctionPass(ID) {
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initializeAArch64PostLegalizerLoweringPass(*PassRegistry::getPassRegistry());
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if (!RuleConfig.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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@ -33,7 +33,7 @@ class AArch64PostSelectOptimize : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PostSelectOptimize();
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AArch64PostSelectOptimize() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "AArch64 Post Select Optimizer";
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@ -59,11 +59,6 @@ void AArch64PostSelectOptimize::getAnalysisUsage(AnalysisUsage &AU) const {
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AArch64PostSelectOptimize::AArch64PostSelectOptimize()
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: MachineFunctionPass(ID) {
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initializeAArch64PostSelectOptimizePass(*PassRegistry::getPassRegistry());
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}
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unsigned getNonFlagSettingVariant(unsigned Opc) {
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switch (Opc) {
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default:
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@ -831,8 +831,6 @@ void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner()
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: MachineFunctionPass(ID) {
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initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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if (!RuleConfig.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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