[LV] Add more tests for costs of predicated udivs and calls.
Adds missing test coverage for the cost model. Also reduce the size of check lines a bit, by using a common prefix and filtering out after scalar.ph.
This commit is contained in:
Florian Hahn
parent
ed26993976
commit
23ea79de61
@ -1,48 +1,29 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefix=DEFAULT %s
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; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefix=PRED %s
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --filter-out-after "scalar.ph\:" --version 5
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; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=COMMON,DEFAULT %s
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; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=COMMON,PRED %s
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "arm64-apple-macosx14.0.0"
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define void @invar_cond_gep_store(ptr %dst, i32 %0) {
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; DEFAULT-LABEL: define void @invar_cond_gep_store(
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; DEFAULT-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) {
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; DEFAULT-NEXT: [[ENTRY:.*]]:
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; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
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; DEFAULT: [[LOOP_HEADER]]:
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; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; DEFAULT-NEXT: [[CMP9:%.*]] = icmp eq i32 [[TMP0]], 0
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; DEFAULT-NEXT: br i1 [[CMP9]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
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; DEFAULT: [[THEN]]:
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; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_NEXT]]
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; DEFAULT-NEXT: store i32 1, ptr [[GEP]], align 4
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; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
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; DEFAULT: [[LOOP_LATCH]]:
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; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100
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; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; DEFAULT: [[EXIT]]:
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; DEFAULT-NEXT: ret void
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;
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; PRED-LABEL: define void @invar_cond_gep_store(
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; PRED-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) {
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; PRED-NEXT: [[ENTRY:.*]]:
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; PRED-NEXT: br label %[[LOOP_HEADER:.*]]
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; PRED: [[LOOP_HEADER]]:
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; PRED-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; PRED-NEXT: [[CMP9:%.*]] = icmp eq i32 [[TMP0]], 0
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; PRED-NEXT: br i1 [[CMP9]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
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; PRED: [[THEN]]:
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; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_NEXT]]
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; PRED-NEXT: store i32 1, ptr [[GEP]], align 4
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; PRED-NEXT: br label %[[LOOP_LATCH]]
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; PRED: [[LOOP_LATCH]]:
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; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100
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; PRED-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; PRED: [[EXIT]]:
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; PRED-NEXT: ret void
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; COMMON-LABEL: define void @invar_cond_gep_store(
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; COMMON-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) {
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; COMMON-NEXT: [[ENTRY:.*]]:
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; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]
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; COMMON: [[LOOP_HEADER]]:
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; COMMON-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; COMMON-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; COMMON-NEXT: [[CMP9:%.*]] = icmp eq i32 [[TMP0]], 0
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; COMMON-NEXT: br i1 [[CMP9]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
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; COMMON: [[THEN]]:
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; COMMON-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_NEXT]]
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; COMMON-NEXT: store i32 1, ptr [[GEP]], align 4
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; COMMON-NEXT: br label %[[LOOP_LATCH]]
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; COMMON: [[LOOP_LATCH]]:
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; COMMON-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100
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; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; COMMON: [[EXIT]]:
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; COMMON-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -71,7 +52,7 @@ declare double @llvm.fabs.f64(double) #0
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define void @loop_dependent_cond(ptr %src, ptr noalias %dst, i64 %N) {
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; DEFAULT-LABEL: define void @loop_dependent_cond(
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; DEFAULT-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
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; DEFAULT-NEXT: [[ENTRY:.*]]:
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; DEFAULT-NEXT: [[ENTRY:.*:]]
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; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
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; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
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; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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@ -118,26 +99,8 @@ define void @loop_dependent_cond(ptr %src, ptr noalias %dst, i64 %N) {
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; DEFAULT-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; DEFAULT: [[MIDDLE_BLOCK]]:
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; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
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; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
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; DEFAULT: [[SCALAR_PH]]:
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; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
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; DEFAULT: [[LOOP_HEADER]]:
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; DEFAULT-NEXT: [[IV175:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT176:%.*]], %[[LOOP_LATCH:.*]] ]
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; DEFAULT-NEXT: [[ARRAYIDX114:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV175]]
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; DEFAULT-NEXT: [[TMP16:%.*]] = load double, ptr [[ARRAYIDX114]], align 8
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; DEFAULT-NEXT: [[TMP17:%.*]] = tail call double @llvm.fabs.f64(double [[TMP16]])
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; DEFAULT-NEXT: [[CMP115:%.*]] = fcmp ogt double [[TMP17]], 1.000000e+00
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; DEFAULT-NEXT: br i1 [[CMP115]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
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; DEFAULT: [[THEN]]:
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; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4
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; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
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; DEFAULT: [[LOOP_LATCH]]:
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; DEFAULT-NEXT: [[IV_NEXT176]] = add i64 [[IV175]], 1
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; DEFAULT-NEXT: [[EXITCOND180_NOT:%.*]] = icmp eq i64 [[IV175]], [[N]]
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; DEFAULT-NEXT: br i1 [[EXITCOND180_NOT]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
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; DEFAULT: [[EXIT]]:
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; DEFAULT-NEXT: ret void
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;
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; PRED-LABEL: define void @loop_dependent_cond(
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; PRED-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) {
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@ -185,53 +148,29 @@ exit:
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}
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define void @invar_cond_chain_1(ptr %I, ptr noalias %src, i1 %c) {
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; DEFAULT-LABEL: define void @invar_cond_chain_1(
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; DEFAULT-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], i1 [[C:%.*]]) {
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; DEFAULT-NEXT: [[ENTRY:.*]]:
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; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
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; DEFAULT: [[LOOP_HEADER]]:
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; DEFAULT-NEXT: [[__BEGIN3_011973:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[INCDEC_PTR329:%.*]], %[[LOOP_LATCH:.*]] ]
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; DEFAULT-NEXT: [[TMP28:%.*]] = load i32, ptr [[__BEGIN3_011973]], align 4
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; DEFAULT-NEXT: br i1 true, label %[[ELSE_1:.*]], label %[[IF:.*]]
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; DEFAULT: [[IF]]:
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; DEFAULT-NEXT: br label %[[SPLIT:.*]]
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; DEFAULT: [[ELSE_1]]:
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; DEFAULT-NEXT: br i1 [[C]], label %[[ELSE_2:.*]], label %[[LOOP_LATCH]]
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; DEFAULT: [[ELSE_2]]:
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; DEFAULT-NEXT: br label %[[SPLIT]]
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; DEFAULT: [[SPLIT]]:
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; DEFAULT-NEXT: store i32 [[TMP28]], ptr [[I]], align 4
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; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
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; DEFAULT: [[LOOP_LATCH]]:
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; DEFAULT-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_011973]], i64 4
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; DEFAULT-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_011973]], [[I]]
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; DEFAULT-NEXT: br i1 [[CMP311_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; DEFAULT: [[EXIT]]:
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; DEFAULT-NEXT: ret void
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;
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; PRED-LABEL: define void @invar_cond_chain_1(
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; PRED-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], i1 [[C:%.*]]) {
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; PRED-NEXT: [[ENTRY:.*]]:
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; PRED-NEXT: br label %[[LOOP_HEADER:.*]]
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; PRED: [[LOOP_HEADER]]:
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; PRED-NEXT: [[__BEGIN3_011973:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[INCDEC_PTR329:%.*]], %[[LOOP_LATCH:.*]] ]
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; PRED-NEXT: [[TMP0:%.*]] = load i32, ptr [[__BEGIN3_011973]], align 4
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; PRED-NEXT: br i1 true, label %[[ELSE_1:.*]], label %[[IF:.*]]
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; PRED: [[IF]]:
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; PRED-NEXT: br label %[[SPLIT:.*]]
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; PRED: [[ELSE_1]]:
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; PRED-NEXT: br i1 [[C]], label %[[ELSE_2:.*]], label %[[LOOP_LATCH]]
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; PRED: [[ELSE_2]]:
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; PRED-NEXT: br label %[[SPLIT]]
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; PRED: [[SPLIT]]:
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; PRED-NEXT: store i32 [[TMP0]], ptr [[I]], align 4
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; PRED-NEXT: br label %[[LOOP_LATCH]]
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; PRED: [[LOOP_LATCH]]:
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; PRED-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_011973]], i64 4
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; PRED-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_011973]], [[I]]
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; PRED-NEXT: br i1 [[CMP311_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; PRED: [[EXIT]]:
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; PRED-NEXT: ret void
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; COMMON-LABEL: define void @invar_cond_chain_1(
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; COMMON-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], i1 [[C:%.*]]) {
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; COMMON-NEXT: [[ENTRY:.*]]:
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; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]
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; COMMON: [[LOOP_HEADER]]:
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; COMMON-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; COMMON-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4
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; COMMON-NEXT: br i1 true, label %[[ELSE_1:.*]], label %[[IF:.*]]
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; COMMON: [[IF]]:
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; COMMON-NEXT: br label %[[SPLIT:.*]]
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; COMMON: [[ELSE_1]]:
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; COMMON-NEXT: br i1 [[C]], label %[[ELSE_2:.*]], label %[[LOOP_LATCH]]
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; COMMON: [[ELSE_2]]:
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; COMMON-NEXT: br label %[[SPLIT]]
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; COMMON: [[SPLIT]]:
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; COMMON-NEXT: store i32 [[L]], ptr [[I]], align 4
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; COMMON-NEXT: br label %[[LOOP_LATCH]]
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; COMMON: [[LOOP_LATCH]]:
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; COMMON-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 4
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; COMMON-NEXT: [[EC:%.*]] = icmp eq ptr [[PTR_IV]], [[I]]
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; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; COMMON: [[EXIT]]:
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; COMMON-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -264,45 +203,25 @@ exit:
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}
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define void @invar_cond_chain_2(ptr %I, ptr noalias %src, ptr noalias %dst, i32 %a) {
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; DEFAULT-LABEL: define void @invar_cond_chain_2(
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; DEFAULT-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[A:%.*]]) {
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; DEFAULT-NEXT: [[ENTRY:.*]]:
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; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
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; DEFAULT: [[LOOP_HEADER]]:
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; DEFAULT-NEXT: [[__BEGIN3_01197:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[INCDEC_PTR329:%.*]], %[[LOOP_LATCH:.*]] ]
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; DEFAULT-NEXT: [[CMP315_NOT:%.*]] = icmp sgt i32 [[A]], 0
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; DEFAULT-NEXT: br i1 [[CMP315_NOT]], label %[[LOOP_LATCH]], label %[[IF:.*]]
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; DEFAULT: [[IF]]:
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; DEFAULT-NEXT: br label %[[ELSE:.*]]
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; DEFAULT: [[ELSE]]:
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; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4
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; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
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; DEFAULT: [[LOOP_LATCH]]:
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; DEFAULT-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_01197]], i64 4
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; DEFAULT-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_01197]], [[I]]
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; DEFAULT-NEXT: br i1 [[CMP311_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; DEFAULT: [[EXIT]]:
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; DEFAULT-NEXT: ret void
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;
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; PRED-LABEL: define void @invar_cond_chain_2(
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; PRED-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[A:%.*]]) {
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; PRED-NEXT: [[ENTRY:.*]]:
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; PRED-NEXT: br label %[[LOOP_HEADER:.*]]
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; PRED: [[LOOP_HEADER]]:
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; PRED-NEXT: [[__BEGIN3_01197:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[INCDEC_PTR329:%.*]], %[[LOOP_LATCH:.*]] ]
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; PRED-NEXT: [[CMP315_NOT:%.*]] = icmp sgt i32 [[A]], 0
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; PRED-NEXT: br i1 [[CMP315_NOT]], label %[[LOOP_LATCH]], label %[[IF:.*]]
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; PRED: [[IF]]:
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; PRED-NEXT: br label %[[ELSE:.*]]
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; PRED: [[ELSE]]:
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; PRED-NEXT: store i32 0, ptr [[DST]], align 4
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; PRED-NEXT: br label %[[LOOP_LATCH]]
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; PRED: [[LOOP_LATCH]]:
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; PRED-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_01197]], i64 4
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; PRED-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_01197]], [[I]]
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; PRED-NEXT: br i1 [[CMP311_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; PRED: [[EXIT]]:
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; PRED-NEXT: ret void
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; COMMON-LABEL: define void @invar_cond_chain_2(
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; COMMON-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[A:%.*]]) {
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; COMMON-NEXT: [[ENTRY:.*]]:
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; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]
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; COMMON: [[LOOP_HEADER]]:
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; COMMON-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[SRC]], %[[ENTRY]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
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; COMMON-NEXT: [[CMP315_NOT:%.*]] = icmp sgt i32 [[A]], 0
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; COMMON-NEXT: br i1 [[CMP315_NOT]], label %[[LOOP_LATCH]], label %[[IF:.*]]
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; COMMON: [[IF]]:
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; COMMON-NEXT: br label %[[ELSE:.*]]
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; COMMON: [[ELSE]]:
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; COMMON-NEXT: store i32 0, ptr [[DST]], align 4
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; COMMON-NEXT: br label %[[LOOP_LATCH]]
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; COMMON: [[LOOP_LATCH]]:
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; COMMON-NEXT: [[PTR_IV_NEXT]] = getelementptr inbounds i8, ptr [[PTR_IV]], i64 4
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; COMMON-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[PTR_IV]], [[I]]
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; COMMON-NEXT: br i1 [[CMP311_NOT]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
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; COMMON: [[EXIT]]:
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; COMMON-NEXT: ret void
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;
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entry:
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br label %loop.header
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@ -331,7 +250,7 @@ exit:
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define void @latch_branch_cost(ptr %dst) {
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; DEFAULT-LABEL: define void @latch_branch_cost(
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; DEFAULT-SAME: ptr [[DST:%.*]]) {
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; DEFAULT-NEXT: [[ITER_CHECK:.*]]:
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; DEFAULT-NEXT: [[ITER_CHECK:.*:]]
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; DEFAULT-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
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; DEFAULT: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
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; DEFAULT-NEXT: br i1 false, label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
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@ -347,7 +266,7 @@ define void @latch_branch_cost(ptr %dst) {
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; DEFAULT-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96
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; DEFAULT-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; DEFAULT: [[MIDDLE_BLOCK]]:
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; DEFAULT-NEXT: br i1 false, label %[[EXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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; DEFAULT-NEXT: br i1 false, [[EXIT:label %.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
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; DEFAULT: [[VEC_EPILOG_ITER_CHECK]]:
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; DEFAULT-NEXT: br i1 false, label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]]
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; DEFAULT: [[VEC_EPILOG_PH]]:
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@ -361,19 +280,8 @@ define void @latch_branch_cost(ptr %dst) {
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; DEFAULT-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT2]], 100
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; DEFAULT-NEXT: br i1 [[TMP10]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
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; DEFAULT: [[VEC_EPILOG_MIDDLE_BLOCK]]:
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; DEFAULT-NEXT: br i1 true, label %[[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
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; DEFAULT-NEXT: br i1 true, [[EXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
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; DEFAULT: [[VEC_EPILOG_SCALAR_PH]]:
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; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 96, %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
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; DEFAULT-NEXT: br label %[[LOOP:.*]]
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; DEFAULT: [[LOOP]]:
|
||||
; DEFAULT-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; DEFAULT-NEXT: [[ARRAYIDX:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDVARS_IV]]
|
||||
; DEFAULT-NEXT: store i8 0, ptr [[ARRAYIDX]], align 1
|
||||
; DEFAULT-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
|
||||
; DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 100
|
||||
; DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
; DEFAULT: [[EXIT]]:
|
||||
; DEFAULT-NEXT: ret void
|
||||
;
|
||||
; PRED-LABEL: define void @latch_branch_cost(
|
||||
; PRED-SAME: ptr [[DST:%.*]]) {
|
||||
@ -454,18 +362,8 @@ define void @latch_branch_cost(ptr %dst) {
|
||||
; PRED-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], 104
|
||||
; PRED-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
|
||||
; PRED: [[MIDDLE_BLOCK]]:
|
||||
; PRED-NEXT: br label %[[EXIT:.*]]
|
||||
; PRED-NEXT: br [[EXIT:label %.*]]
|
||||
; PRED: [[SCALAR_PH]]:
|
||||
; PRED-NEXT: br label %[[LOOP:.*]]
|
||||
; PRED: [[LOOP]]:
|
||||
; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; PRED-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]
|
||||
; PRED-NEXT: store i8 0, ptr [[GEP]], align 1
|
||||
; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 100
|
||||
; PRED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
; PRED: [[EXIT]]:
|
||||
; PRED-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop
|
||||
@ -485,7 +383,7 @@ exit:
|
||||
define i32 @header_mask_and_invariant_compare(ptr %A, ptr %B, ptr %C, ptr %D, ptr %E, i64 %N) "target-features"="+sve" {
|
||||
; DEFAULT-LABEL: define i32 @header_mask_and_invariant_compare(
|
||||
; DEFAULT-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
; DEFAULT-NEXT: [[ENTRY:.*]]:
|
||||
; DEFAULT-NEXT: [[ENTRY:.*:]]
|
||||
; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
|
||||
; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 60
|
||||
; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
|
||||
@ -577,29 +475,8 @@ define i32 @header_mask_and_invariant_compare(ptr %A, ptr %B, ptr %C, ptr %D, pt
|
||||
; DEFAULT-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]]
|
||||
; DEFAULT: [[MIDDLE_BLOCK]]:
|
||||
; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
|
||||
; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
|
||||
; DEFAULT: [[SCALAR_PH]]:
|
||||
; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_MEMCHECK]] ]
|
||||
; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
|
||||
; DEFAULT: [[LOOP_HEADER]]:
|
||||
; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
|
||||
; DEFAULT-NEXT: [[L_A:%.*]] = load i32, ptr [[A]], align 4
|
||||
; DEFAULT-NEXT: [[L_B:%.*]] = load i32, ptr [[B]], align 4
|
||||
; DEFAULT-NEXT: [[OR:%.*]] = or i32 [[L_B]], [[L_A]]
|
||||
; DEFAULT-NEXT: [[L_C:%.*]] = load i32, ptr [[C]], align 4
|
||||
; DEFAULT-NEXT: [[C_0:%.*]] = icmp ugt i32 [[L_C]], [[OR]]
|
||||
; DEFAULT-NEXT: br i1 [[C_0]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]]
|
||||
; DEFAULT: [[IF_THEN]]:
|
||||
; DEFAULT-NEXT: [[GEP_D:%.*]] = getelementptr i32, ptr [[D]], i64 [[IV]]
|
||||
; DEFAULT-NEXT: store i32 [[OR]], ptr [[E]], align 4
|
||||
; DEFAULT-NEXT: store i32 0, ptr [[GEP_D]], align 4
|
||||
; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
|
||||
; DEFAULT: [[LOOP_LATCH]]:
|
||||
; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; DEFAULT-NEXT: [[C_1:%.*]] = icmp eq i64 [[IV]], [[N]]
|
||||
; DEFAULT-NEXT: br i1 [[C_1]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP21:![0-9]+]]
|
||||
; DEFAULT: [[EXIT]]:
|
||||
; DEFAULT-NEXT: ret i32 0
|
||||
;
|
||||
; PRED-LABEL: define i32 @header_mask_and_invariant_compare(
|
||||
; PRED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]], ptr [[E:%.*]], i64 [[N:%.*]]) #[[ATTR1:[0-9]+]] {
|
||||
@ -655,7 +532,7 @@ exit:
|
||||
define void @multiple_exit_conditions(ptr %src, ptr noalias %dst) #1 {
|
||||
; DEFAULT-LABEL: define void @multiple_exit_conditions(
|
||||
; DEFAULT-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
; DEFAULT-NEXT: [[ENTRY:.*]]:
|
||||
; DEFAULT-NEXT: [[ENTRY:.*:]]
|
||||
; DEFAULT-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
|
||||
; DEFAULT: [[VECTOR_PH]]:
|
||||
; DEFAULT-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[DST]], i64 2048
|
||||
@ -676,23 +553,6 @@ define void @multiple_exit_conditions(ptr %src, ptr noalias %dst) #1 {
|
||||
; DEFAULT: [[MIDDLE_BLOCK]]:
|
||||
; DEFAULT-NEXT: br label %[[SCALAR_PH]]
|
||||
; DEFAULT: [[SCALAR_PH]]:
|
||||
; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ [[DST]], %[[ENTRY]] ]
|
||||
; DEFAULT-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ 512, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
|
||||
; DEFAULT-NEXT: br label %[[LOOP:.*]]
|
||||
; DEFAULT: [[LOOP]]:
|
||||
; DEFAULT-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; DEFAULT-NEXT: [[L:%.*]] = load i16, ptr [[SRC]], align 2
|
||||
; DEFAULT-NEXT: [[O:%.*]] = or i16 [[L]], 1
|
||||
; DEFAULT-NEXT: [[CONV:%.*]] = uitofp i16 [[O]] to double
|
||||
; DEFAULT-NEXT: store double [[CONV]], ptr [[PTR_IV]], align 8
|
||||
; DEFAULT-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2
|
||||
; DEFAULT-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 8
|
||||
; DEFAULT-NEXT: [[IV_CLAMP:%.*]] = and i64 [[IV]], 4294967294
|
||||
; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_CLAMP]], 512
|
||||
; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP23:![0-9]+]]
|
||||
; DEFAULT: [[EXIT]]:
|
||||
; DEFAULT-NEXT: ret void
|
||||
;
|
||||
; PRED-LABEL: define void @multiple_exit_conditions(
|
||||
; PRED-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]]) #[[ATTR2:[0-9]+]] {
|
||||
@ -725,23 +585,8 @@ define void @multiple_exit_conditions(ptr %src, ptr noalias %dst) #1 {
|
||||
; PRED-NEXT: [[TMP16:%.*]] = xor i1 [[TMP15]], true
|
||||
; PRED-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
|
||||
; PRED: [[MIDDLE_BLOCK]]:
|
||||
; PRED-NEXT: br label %[[EXIT:.*]]
|
||||
; PRED-NEXT: br [[EXIT:label %.*]]
|
||||
; PRED: [[SCALAR_PH]]:
|
||||
; PRED-NEXT: br label %[[LOOP:.*]]
|
||||
; PRED: [[LOOP]]:
|
||||
; PRED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[DST]], %[[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; PRED-NEXT: [[L:%.*]] = load i16, ptr [[SRC]], align 2
|
||||
; PRED-NEXT: [[O:%.*]] = or i16 [[L]], 1
|
||||
; PRED-NEXT: [[CONV:%.*]] = uitofp i16 [[O]] to double
|
||||
; PRED-NEXT: store double [[CONV]], ptr [[PTR_IV]], align 8
|
||||
; PRED-NEXT: [[IV_NEXT]] = add nsw i64 [[IV]], 2
|
||||
; PRED-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 8
|
||||
; PRED-NEXT: [[IV_CLAMP:%.*]] = and i64 [[IV]], 4294967294
|
||||
; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_CLAMP]], 512
|
||||
; PRED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
|
||||
; PRED: [[EXIT]]:
|
||||
; PRED-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop
|
||||
@ -851,19 +696,8 @@ define void @low_trip_count_fold_tail_scalarized_store(ptr %dst) {
|
||||
; DEFAULT-NEXT: [[VEC_IND_NEXT]] = add <8 x i8> [[VEC_IND]], splat (i8 8)
|
||||
; DEFAULT-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]]
|
||||
; DEFAULT: [[MIDDLE_BLOCK]]:
|
||||
; DEFAULT-NEXT: br label %[[EXIT:.*]]
|
||||
; DEFAULT-NEXT: br [[EXIT:label %.*]]
|
||||
; DEFAULT: [[SCALAR_PH]]:
|
||||
; DEFAULT-NEXT: br label %[[LOOP:.*]]
|
||||
; DEFAULT: [[LOOP]]:
|
||||
; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; DEFAULT-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i8
|
||||
; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]
|
||||
; DEFAULT-NEXT: store i8 [[IV_TRUNC]], ptr [[GEP]], align 1
|
||||
; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 7
|
||||
; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP25:![0-9]+]]
|
||||
; DEFAULT: [[EXIT]]:
|
||||
; DEFAULT-NEXT: ret void
|
||||
;
|
||||
; PRED-LABEL: define void @low_trip_count_fold_tail_scalarized_store(
|
||||
; PRED-SAME: ptr [[DST:%.*]]) {
|
||||
@ -952,19 +786,8 @@ define void @low_trip_count_fold_tail_scalarized_store(ptr %dst) {
|
||||
; PRED-NEXT: [[VEC_IND_NEXT]] = add <8 x i8> [[VEC_IND]], splat (i8 8)
|
||||
; PRED-NEXT: br i1 true, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
; PRED: [[MIDDLE_BLOCK]]:
|
||||
; PRED-NEXT: br label %[[EXIT:.*]]
|
||||
; PRED-NEXT: br [[EXIT:label %.*]]
|
||||
; PRED: [[SCALAR_PH]]:
|
||||
; PRED-NEXT: br label %[[LOOP:.*]]
|
||||
; PRED: [[LOOP]]:
|
||||
; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
|
||||
; PRED-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV]] to i8
|
||||
; PRED-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]]
|
||||
; PRED-NEXT: store i8 [[IV_TRUNC]], ptr [[GEP]], align 1
|
||||
; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 7
|
||||
; PRED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
; PRED: [[EXIT]]:
|
||||
; PRED-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop
|
||||
@ -985,7 +808,7 @@ exit:
|
||||
define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias %src.2, ptr noalias %src.3, ptr noalias %src.4, ptr noalias %dst, i64 %N) #2 {
|
||||
; DEFAULT-LABEL: define void @test_conditional_interleave_group(
|
||||
; DEFAULT-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[SRC_3:%.*]], ptr noalias [[SRC_4:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; DEFAULT-NEXT: [[ENTRY:.*]]:
|
||||
; DEFAULT-NEXT: [[ENTRY:.*:]]
|
||||
; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
|
||||
; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
|
||||
; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
|
||||
@ -1166,41 +989,12 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
|
||||
; DEFAULT-NEXT: br i1 [[TMP80]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]]
|
||||
; DEFAULT: [[MIDDLE_BLOCK]]:
|
||||
; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
|
||||
; DEFAULT-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
|
||||
; DEFAULT: [[SCALAR_PH]]:
|
||||
; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
|
||||
; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
|
||||
; DEFAULT: [[LOOP_HEADER]]:
|
||||
; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
|
||||
; DEFAULT-NEXT: [[TMP81:%.*]] = load float, ptr [[SRC_1]], align 4
|
||||
; DEFAULT-NEXT: [[TMP82:%.*]] = load float, ptr [[SRC_2]], align 4
|
||||
; DEFAULT-NEXT: [[MUL8_I_US:%.*]] = fmul float [[TMP82]], 0.000000e+00
|
||||
; DEFAULT-NEXT: [[TMP83:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP81]], float 0.000000e+00, float [[MUL8_I_US]])
|
||||
; DEFAULT-NEXT: [[TMP84:%.*]] = load float, ptr [[SRC_3]], align 4
|
||||
; DEFAULT-NEXT: [[TMP85:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP84]], float 0.000000e+00, float [[TMP83]])
|
||||
; DEFAULT-NEXT: [[TMP86:%.*]] = load float, ptr [[SRC_3]], align 4
|
||||
; DEFAULT-NEXT: [[C:%.*]] = fcmp ogt float [[TMP85]], [[TMP86]]
|
||||
; DEFAULT-NEXT: br i1 [[C]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]]
|
||||
; DEFAULT: [[IF_THEN]]:
|
||||
; DEFAULT-NEXT: [[DST_0:%.*]] = getelementptr { [4 x float] }, ptr [[DST]], i64 [[IV]]
|
||||
; DEFAULT-NEXT: store float 0.000000e+00, ptr [[DST_0]], align 4
|
||||
; DEFAULT-NEXT: [[DST_1:%.*]] = getelementptr i8, ptr [[DST_0]], i64 4
|
||||
; DEFAULT-NEXT: store float 0.000000e+00, ptr [[DST_1]], align 4
|
||||
; DEFAULT-NEXT: [[DST_2:%.*]] = getelementptr i8, ptr [[DST_0]], i64 8
|
||||
; DEFAULT-NEXT: store float 0.000000e+00, ptr [[DST_2]], align 4
|
||||
; DEFAULT-NEXT: [[DST_3:%.*]] = getelementptr i8, ptr [[DST_0]], i64 16
|
||||
; DEFAULT-NEXT: store float 0.000000e+00, ptr [[DST_0]], align 4
|
||||
; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
|
||||
; DEFAULT: [[LOOP_LATCH]]:
|
||||
; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
|
||||
; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP27:![0-9]+]]
|
||||
; DEFAULT: [[EXIT]]:
|
||||
; DEFAULT-NEXT: ret void
|
||||
;
|
||||
; PRED-LABEL: define void @test_conditional_interleave_group(
|
||||
; PRED-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[SRC_3:%.*]], ptr noalias [[SRC_4:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR3:[0-9]+]] {
|
||||
; PRED-NEXT: [[ENTRY:.*]]:
|
||||
; PRED-NEXT: [[ENTRY:.*:]]
|
||||
; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
|
||||
; PRED-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
|
||||
; PRED: [[VECTOR_SCEVCHECK]]:
|
||||
@ -1385,37 +1179,8 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
|
||||
; PRED-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[VEC_IND]], splat (i64 8)
|
||||
; PRED-NEXT: br i1 [[TMP85]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
; PRED: [[MIDDLE_BLOCK]]:
|
||||
; PRED-NEXT: br label %[[EXIT:.*]]
|
||||
; PRED-NEXT: br [[EXIT:label %.*]]
|
||||
; PRED: [[SCALAR_PH]]:
|
||||
; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ 0, %[[VECTOR_SCEVCHECK]] ]
|
||||
; PRED-NEXT: br label %[[LOOP_HEADER:.*]]
|
||||
; PRED: [[LOOP_HEADER]]:
|
||||
; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
|
||||
; PRED-NEXT: [[TMP86:%.*]] = load float, ptr [[SRC_1]], align 4
|
||||
; PRED-NEXT: [[TMP87:%.*]] = load float, ptr [[SRC_2]], align 4
|
||||
; PRED-NEXT: [[MUL8_I_US:%.*]] = fmul float [[TMP87]], 0.000000e+00
|
||||
; PRED-NEXT: [[TMP88:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP86]], float 0.000000e+00, float [[MUL8_I_US]])
|
||||
; PRED-NEXT: [[TMP89:%.*]] = load float, ptr [[SRC_3]], align 4
|
||||
; PRED-NEXT: [[TMP90:%.*]] = tail call float @llvm.fmuladd.f32(float [[TMP89]], float 0.000000e+00, float [[TMP88]])
|
||||
; PRED-NEXT: [[TMP91:%.*]] = load float, ptr [[SRC_3]], align 4
|
||||
; PRED-NEXT: [[C:%.*]] = fcmp ogt float [[TMP90]], [[TMP91]]
|
||||
; PRED-NEXT: br i1 [[C]], label %[[IF_THEN:.*]], label %[[LOOP_LATCH]]
|
||||
; PRED: [[IF_THEN]]:
|
||||
; PRED-NEXT: [[DST_0:%.*]] = getelementptr { [4 x float] }, ptr [[DST]], i64 [[IV]]
|
||||
; PRED-NEXT: store float 0.000000e+00, ptr [[DST_0]], align 4
|
||||
; PRED-NEXT: [[DST_1:%.*]] = getelementptr i8, ptr [[DST_0]], i64 4
|
||||
; PRED-NEXT: store float 0.000000e+00, ptr [[DST_1]], align 4
|
||||
; PRED-NEXT: [[DST_2:%.*]] = getelementptr i8, ptr [[DST_0]], i64 8
|
||||
; PRED-NEXT: store float 0.000000e+00, ptr [[DST_2]], align 4
|
||||
; PRED-NEXT: [[DST_3:%.*]] = getelementptr i8, ptr [[DST_0]], i64 16
|
||||
; PRED-NEXT: store float 0.000000e+00, ptr [[DST_0]], align 4
|
||||
; PRED-NEXT: br label %[[LOOP_LATCH]]
|
||||
; PRED: [[LOOP_LATCH]]:
|
||||
; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]]
|
||||
; PRED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
; PRED: [[EXIT]]:
|
||||
; PRED-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop.header
|
||||
@ -1455,7 +1220,7 @@ exit:
|
||||
define void @redundant_branch_and_tail_folding(ptr %dst, i1 %c) {
|
||||
; DEFAULT-LABEL: define void @redundant_branch_and_tail_folding(
|
||||
; DEFAULT-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) {
|
||||
; DEFAULT-NEXT: [[ENTRY:.*]]:
|
||||
; DEFAULT-NEXT: [[ENTRY:.*:]]
|
||||
; DEFAULT-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
|
||||
; DEFAULT: [[VECTOR_PH]]:
|
||||
; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
@ -1474,21 +1239,6 @@ define void @redundant_branch_and_tail_folding(ptr %dst, i1 %c) {
|
||||
; DEFAULT: [[MIDDLE_BLOCK]]:
|
||||
; DEFAULT-NEXT: br label %[[SCALAR_PH]]
|
||||
; DEFAULT: [[SCALAR_PH]]:
|
||||
; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 16, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
|
||||
; DEFAULT-NEXT: br label %[[LOOP_HEADER:.*]]
|
||||
; DEFAULT: [[LOOP_HEADER]]:
|
||||
; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
|
||||
; DEFAULT-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[THEN:.*]]
|
||||
; DEFAULT: [[THEN]]:
|
||||
; DEFAULT-NEXT: br label %[[LOOP_LATCH]]
|
||||
; DEFAULT: [[LOOP_LATCH]]:
|
||||
; DEFAULT-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
|
||||
; DEFAULT-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[IV_NEXT]] to i32
|
||||
; DEFAULT-NEXT: store i32 [[T]], ptr [[DST]], align 4
|
||||
; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 21
|
||||
; DEFAULT-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP29:![0-9]+]]
|
||||
; DEFAULT: [[EXIT]]:
|
||||
; DEFAULT-NEXT: ret void
|
||||
;
|
||||
; PRED-LABEL: define void @redundant_branch_and_tail_folding(
|
||||
; PRED-SAME: ptr [[DST:%.*]], i1 [[C:%.*]]) {
|
||||
@ -1535,22 +1285,8 @@ define void @redundant_branch_and_tail_folding(ptr %dst, i1 %c) {
|
||||
; PRED-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24
|
||||
; PRED-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
|
||||
; PRED: [[MIDDLE_BLOCK]]:
|
||||
; PRED-NEXT: br label %[[EXIT:.*]]
|
||||
; PRED-NEXT: br [[EXIT:label %.*]]
|
||||
; PRED: [[SCALAR_PH]]:
|
||||
; PRED-NEXT: br label %[[LOOP_HEADER:.*]]
|
||||
; PRED: [[LOOP_HEADER]]:
|
||||
; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
|
||||
; PRED-NEXT: br i1 [[C]], label %[[LOOP_LATCH]], label %[[THEN:.*]]
|
||||
; PRED: [[THEN]]:
|
||||
; PRED-NEXT: br label %[[LOOP_LATCH]]
|
||||
; PRED: [[LOOP_LATCH]]:
|
||||
; PRED-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
|
||||
; PRED-NEXT: [[T:%.*]] = trunc nuw nsw i64 [[IV_NEXT]] to i32
|
||||
; PRED-NEXT: store i32 [[T]], ptr [[DST]], align 4
|
||||
; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 21
|
||||
; PRED-NEXT: br i1 [[EC]], label %[[EXIT]], label %[[LOOP_HEADER]], !llvm.loop [[LOOP11:![0-9]+]]
|
||||
; PRED: [[EXIT]]:
|
||||
; PRED-NEXT: ret void
|
||||
;
|
||||
entry:
|
||||
br label %loop.header
|
||||
@ -1573,8 +1309,212 @@ exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
|
||||
define double @test_cond_intrinsics(ptr %A, i1 %c) {
|
||||
; COMMON-LABEL: define double @test_cond_intrinsics(
|
||||
; COMMON-SAME: ptr [[A:%.*]], i1 [[C:%.*]]) {
|
||||
; COMMON-NEXT: [[ENTRY:.*]]:
|
||||
; COMMON-NEXT: br label %[[LOOP_HEADER:.*]]
|
||||
; COMMON: [[LOOP_HEADER]]:
|
||||
; COMMON-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_LATCH:.*]] ]
|
||||
; COMMON-NEXT: br i1 [[C]], label %[[THEN:.*]], label %[[LOOP_LATCH]]
|
||||
; COMMON: [[THEN]]:
|
||||
; COMMON-NEXT: [[GEP:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[IV]]
|
||||
; COMMON-NEXT: [[L:%.*]] = load double, ptr [[GEP]], align 8
|
||||
; COMMON-NEXT: [[POW:%.*]] = tail call double @llvm.pow.f64(double 2.000000e+00, double [[L]])
|
||||
; COMMON-NEXT: store double [[POW]], ptr [[GEP]], align 8
|
||||
; COMMON-NEXT: br label %[[LOOP_LATCH]]
|
||||
; COMMON: [[LOOP_LATCH]]:
|
||||
; COMMON-NEXT: [[P:%.*]] = phi double [ 0.000000e+00, %[[LOOP_HEADER]] ], [ [[POW]], %[[THEN]] ]
|
||||
; COMMON-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; COMMON-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 1024
|
||||
; COMMON-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP_HEADER]]
|
||||
; COMMON: [[EXIT]]:
|
||||
; COMMON-NEXT: [[P_LCSSA:%.*]] = phi double [ [[P]], %[[LOOP_LATCH]] ]
|
||||
; COMMON-NEXT: ret double [[P_LCSSA]]
|
||||
;
|
||||
entry:
|
||||
br label %loop.header
|
||||
|
||||
loop.header: ; preds = %loop.latch, %entry
|
||||
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
|
||||
br i1 %c, label %then, label %loop.latch
|
||||
|
||||
then:
|
||||
%gep = getelementptr inbounds double, ptr %A, i64 %iv
|
||||
%l = load double, ptr %gep, align 8
|
||||
%pow = tail call double @llvm.pow.f64(double 2.0, double %l)
|
||||
store double %pow, ptr %gep
|
||||
br label %loop.latch
|
||||
|
||||
loop.latch:
|
||||
%p = phi double [ 0.000000e+00, %loop.header ], [ %pow, %then ]
|
||||
%iv.next = add i64 %iv, 1
|
||||
%ec = icmp eq i64 %iv, 1024
|
||||
br i1 %ec, label %exit, label %loop.header
|
||||
|
||||
exit:
|
||||
ret double %p
|
||||
}
|
||||
|
||||
define void @pred_udiv_select_cost(ptr %A, ptr %B, ptr %C, i64 %n, i8 %y) #1 {
|
||||
; DEFAULT-LABEL: define void @pred_udiv_select_cost(
|
||||
; DEFAULT-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]], i8 [[Y:%.*]]) #[[ATTR2]] {
|
||||
; DEFAULT-NEXT: [[ENTRY:.*:]]
|
||||
; DEFAULT-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
|
||||
; DEFAULT-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
|
||||
; DEFAULT-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
|
||||
; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
|
||||
; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; DEFAULT-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 2
|
||||
; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.umax.i64(i64 8, i64 [[TMP2]])
|
||||
; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP3]]
|
||||
; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
|
||||
; DEFAULT: [[VECTOR_MEMCHECK]]:
|
||||
; DEFAULT-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; DEFAULT-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 4
|
||||
; DEFAULT-NEXT: [[TMP6:%.*]] = sub i64 [[C1]], [[A2]]
|
||||
; DEFAULT-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]]
|
||||
; DEFAULT-NEXT: [[TMP7:%.*]] = sub i64 [[C1]], [[B3]]
|
||||
; DEFAULT-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP7]], [[TMP5]]
|
||||
; DEFAULT-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
|
||||
; DEFAULT-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
|
||||
; DEFAULT: [[VECTOR_PH]]:
|
||||
; DEFAULT-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; DEFAULT-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 4
|
||||
; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP9]]
|
||||
; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
|
||||
; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i8> poison, i8 [[Y]], i64 0
|
||||
; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i8> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
|
||||
; DEFAULT-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; DEFAULT: [[VECTOR_BODY]]:
|
||||
; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
|
||||
; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP10]], align 1
|
||||
; DEFAULT-NEXT: [[TMP11:%.*]] = uitofp <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x float>
|
||||
; DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
|
||||
; DEFAULT-NEXT: [[WIDE_LOAD5:%.*]] = load <vscale x 4 x i8>, ptr [[TMP12]], align 1
|
||||
; DEFAULT-NEXT: [[TMP13:%.*]] = icmp eq <vscale x 4 x i8> [[WIDE_LOAD5]], zeroinitializer
|
||||
; DEFAULT-NEXT: [[TMP14:%.*]] = xor <vscale x 4 x i8> [[WIDE_LOAD]], splat (i8 1)
|
||||
; DEFAULT-NEXT: [[TMP15:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i8> splat (i8 1), <vscale x 4 x i8> [[BROADCAST_SPLAT]]
|
||||
; DEFAULT-NEXT: [[TMP16:%.*]] = udiv <vscale x 4 x i8> [[TMP14]], [[TMP15]]
|
||||
; DEFAULT-NEXT: [[TMP17:%.*]] = icmp ugt <vscale x 4 x i8> [[TMP16]], splat (i8 1)
|
||||
; DEFAULT-NEXT: [[TMP18:%.*]] = select <vscale x 4 x i1> [[TMP17]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> splat (i32 255)
|
||||
; DEFAULT-NEXT: [[PREDPHI:%.*]] = select <vscale x 4 x i1> [[TMP13]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> [[TMP18]]
|
||||
; DEFAULT-NEXT: [[TMP19:%.*]] = zext <vscale x 4 x i8> [[WIDE_LOAD]] to <vscale x 4 x i32>
|
||||
; DEFAULT-NEXT: [[TMP20:%.*]] = sub <vscale x 4 x i32> [[PREDPHI]], [[TMP19]]
|
||||
; DEFAULT-NEXT: [[TMP21:%.*]] = sitofp <vscale x 4 x i32> [[TMP20]] to <vscale x 4 x float>
|
||||
; DEFAULT-NEXT: [[TMP22:%.*]] = call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> [[TMP21]], <vscale x 4 x float> splat (float 3.000000e+00), <vscale x 4 x float> [[TMP11]])
|
||||
; DEFAULT-NEXT: [[TMP23:%.*]] = fptoui <vscale x 4 x float> [[TMP22]] to <vscale x 4 x i8>
|
||||
; DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[C]], i64 [[INDEX]]
|
||||
; DEFAULT-NEXT: store <vscale x 4 x i8> [[TMP23]], ptr [[TMP24]], align 1
|
||||
; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP9]]
|
||||
; DEFAULT-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
||||
; DEFAULT-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP30:![0-9]+]]
|
||||
; DEFAULT: [[MIDDLE_BLOCK]]:
|
||||
; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
|
||||
; DEFAULT-NEXT: br i1 [[CMP_N]], [[EXIT:label %.*]], label %[[SCALAR_PH]]
|
||||
; DEFAULT: [[SCALAR_PH]]:
|
||||
;
|
||||
; PRED-LABEL: define void @pred_udiv_select_cost(
|
||||
; PRED-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]], i8 [[Y:%.*]]) #[[ATTR2]] {
|
||||
; PRED-NEXT: [[ENTRY:.*:]]
|
||||
; PRED-NEXT: [[B3:%.*]] = ptrtoint ptr [[B]] to i64
|
||||
; PRED-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
|
||||
; PRED-NEXT: [[C1:%.*]] = ptrtoint ptr [[C]] to i64
|
||||
; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
|
||||
; PRED-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
|
||||
; PRED: [[VECTOR_MEMCHECK]]:
|
||||
; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; PRED-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 16
|
||||
; PRED-NEXT: [[TMP3:%.*]] = sub i64 [[C1]], [[A2]]
|
||||
; PRED-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]]
|
||||
; PRED-NEXT: [[TMP4:%.*]] = sub i64 [[C1]], [[B3]]
|
||||
; PRED-NEXT: [[DIFF_CHECK4:%.*]] = icmp ult i64 [[TMP4]], [[TMP2]]
|
||||
; PRED-NEXT: [[CONFLICT_RDX:%.*]] = or i1 [[DIFF_CHECK]], [[DIFF_CHECK4]]
|
||||
; PRED-NEXT: br i1 [[CONFLICT_RDX]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
|
||||
; PRED: [[VECTOR_PH]]:
|
||||
; PRED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; PRED-NEXT: [[TMP6:%.*]] = mul nuw i64 [[TMP5]], 16
|
||||
; PRED-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; PRED-NEXT: [[TMP8:%.*]] = shl nuw i64 [[TMP7]], 4
|
||||
; PRED-NEXT: [[TMP9:%.*]] = sub i64 [[TMP0]], [[TMP8]]
|
||||
; PRED-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], [[TMP8]]
|
||||
; PRED-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 0
|
||||
; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 [[TMP0]])
|
||||
; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i8> poison, i8 [[Y]], i64 0
|
||||
; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i8> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
|
||||
; PRED-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; PRED: [[VECTOR_BODY]]:
|
||||
; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 16 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; PRED-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[A]], i64 [[INDEX]]
|
||||
; PRED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr [[TMP12]], i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)
|
||||
; PRED-NEXT: [[TMP13:%.*]] = uitofp <vscale x 16 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 16 x float>
|
||||
; PRED-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[B]], i64 [[INDEX]]
|
||||
; PRED-NEXT: [[WIDE_MASKED_LOAD5:%.*]] = call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr [[TMP14]], i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i8> poison)
|
||||
; PRED-NEXT: [[TMP15:%.*]] = icmp ne <vscale x 16 x i8> [[WIDE_MASKED_LOAD5]], zeroinitializer
|
||||
; PRED-NEXT: [[TMP16:%.*]] = select <vscale x 16 x i1> [[ACTIVE_LANE_MASK]], <vscale x 16 x i1> [[TMP15]], <vscale x 16 x i1> zeroinitializer
|
||||
; PRED-NEXT: [[TMP17:%.*]] = xor <vscale x 16 x i8> [[WIDE_MASKED_LOAD]], splat (i8 1)
|
||||
; PRED-NEXT: [[TMP18:%.*]] = select <vscale x 16 x i1> [[TMP16]], <vscale x 16 x i8> [[BROADCAST_SPLAT]], <vscale x 16 x i8> splat (i8 1)
|
||||
; PRED-NEXT: [[TMP19:%.*]] = udiv <vscale x 16 x i8> [[TMP17]], [[TMP18]]
|
||||
; PRED-NEXT: [[TMP20:%.*]] = icmp ugt <vscale x 16 x i8> [[TMP19]], splat (i8 1)
|
||||
; PRED-NEXT: [[TMP21:%.*]] = select <vscale x 16 x i1> [[TMP20]], <vscale x 16 x i32> zeroinitializer, <vscale x 16 x i32> splat (i32 255)
|
||||
; PRED-NEXT: [[PREDPHI:%.*]] = select <vscale x 16 x i1> [[TMP16]], <vscale x 16 x i32> [[TMP21]], <vscale x 16 x i32> zeroinitializer
|
||||
; PRED-NEXT: [[TMP22:%.*]] = zext <vscale x 16 x i8> [[WIDE_MASKED_LOAD]] to <vscale x 16 x i32>
|
||||
; PRED-NEXT: [[TMP23:%.*]] = sub <vscale x 16 x i32> [[PREDPHI]], [[TMP22]]
|
||||
; PRED-NEXT: [[TMP24:%.*]] = sitofp <vscale x 16 x i32> [[TMP23]] to <vscale x 16 x float>
|
||||
; PRED-NEXT: [[TMP25:%.*]] = call <vscale x 16 x float> @llvm.fmuladd.nxv16f32(<vscale x 16 x float> [[TMP24]], <vscale x 16 x float> splat (float 3.000000e+00), <vscale x 16 x float> [[TMP13]])
|
||||
; PRED-NEXT: [[TMP26:%.*]] = fptoui <vscale x 16 x float> [[TMP25]] to <vscale x 16 x i8>
|
||||
; PRED-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[C]], i64 [[INDEX]]
|
||||
; PRED-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> [[TMP26]], ptr [[TMP27]], i32 1, <vscale x 16 x i1> [[ACTIVE_LANE_MASK]])
|
||||
; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]]
|
||||
; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX]], i64 [[TMP11]])
|
||||
; PRED-NEXT: [[TMP28:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0
|
||||
; PRED-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], true
|
||||
; PRED-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
|
||||
; PRED: [[MIDDLE_BLOCK]]:
|
||||
; PRED-NEXT: br [[EXIT:label %.*]]
|
||||
; PRED: [[SCALAR_PH]]:
|
||||
;
|
||||
entry:
|
||||
br label %loop.header
|
||||
|
||||
loop.header: ; preds = %loop.latch, %entry
|
||||
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ]
|
||||
%gep.A = getelementptr i8, ptr %A, i64 %iv
|
||||
%l.1 = load i8, ptr %gep.A, align 1
|
||||
%l.1.to.float = uitofp i8 %l.1 to float
|
||||
%gep.B = getelementptr i8, ptr %B, i64 %iv
|
||||
%l.2 = load i8, ptr %gep.B, align 1
|
||||
%c = icmp eq i8 %l.2, 0
|
||||
br i1 %c, label %loop.latch, label %else
|
||||
|
||||
else:
|
||||
%x = xor i8 %l.1, 1
|
||||
%ud = udiv i8 %x, %y
|
||||
%c.sel = icmp ugt i8 %ud, 1
|
||||
%sel = select i1 %c.sel, i32 0, i32 255
|
||||
br label %loop.latch
|
||||
|
||||
loop.latch:
|
||||
%p = phi i32 [ %sel, %else ], [ 0, %loop.header ]
|
||||
%l.1.ext = zext i8 %l.1 to i32
|
||||
%sub = sub i32 %p, %l.1.ext
|
||||
%sub.to.float = sitofp i32 %sub to float
|
||||
%muladd = tail call float @llvm.fmuladd.f32(float %sub.to.float, float 3.000000e+00, float %l.1.to.float)
|
||||
%muladd.conv = fptoui float %muladd to i8
|
||||
%gep.C = getelementptr i8, ptr %C, i64 %iv
|
||||
store i8 %muladd.conv, ptr %gep.C, align 1
|
||||
%iv.next = add i64 %iv, 1
|
||||
%ec = icmp eq i64 %iv, %n
|
||||
br i1 %ec, label %exit, label %loop.header
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.fmuladd.f32(float, float, float) #1
|
||||
declare double @llvm.pow.f64(double, double)
|
||||
|
||||
attributes #1 = { "target-cpu"="neoverse-512tvb" }
|
||||
attributes #2 = { vscale_range(2,2) "target-cpu"="neoverse-512tvb" }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user