[LegalizeDAG] Truncate condition operand of ISD::SELECT
Differential revision: https://reviews.llvm.org/D42737 llvm-svn: 324447
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@ -343,8 +343,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
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ScalarBool = TargetLowering::UndefinedBooleanContent;
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}
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EVT CondVT = Cond.getValueType();
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if (ScalarBool != VecBool) {
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EVT CondVT = Cond.getValueType();
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switch (ScalarBool) {
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case TargetLowering::UndefinedBooleanContent:
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break;
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@ -365,6 +365,11 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSELECT(SDNode *N) {
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}
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}
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// Truncate the condition if needed
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auto BoolVT = getSetCCResultType(CondVT);
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if (BoolVT.bitsLT(CondVT))
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Cond = DAG.getNode(ISD::TRUNCATE, SDLoc(N), BoolVT, Cond);
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return DAG.getSelect(SDLoc(N),
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LHS.getValueType(), Cond, LHS,
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GetScalarizedVector(N->getOperand(2)));
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61
llvm/test/CodeGen/AArch64/expand-select.ll
Normal file
61
llvm/test/CodeGen/AArch64/expand-select.ll
Normal file
@ -0,0 +1,61 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu -O3 %s -o - | FileCheck %s
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define void @foo(i32 %In1, <2 x i128> %In2, <2 x i128> %In3, <2 x i128> *%Out) {
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; CHECK-LABEL: foo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w0, #0x1
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; CHECK-NEXT: fmov s0, wzr
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; CHECK-NEXT: ldp x10, x8, [sp, #8]
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; CHECK-NEXT: fmov s1, w9
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; CHECK-NEXT: ldr x9, [sp]
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; CHECK-NEXT: cmeq v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: fmov w11, s0
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; CHECK-NEXT: tst w11, #0x1
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; CHECK-NEXT: csel x11, x2, x6, ne
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; CHECK-NEXT: csel x12, x3, x7, ne
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; CHECK-NEXT: csel x9, x4, x9, ne
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; CHECK-NEXT: csel x10, x5, x10, ne
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; CHECK-NEXT: stp x9, x10, [x8, #16]
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; CHECK-NEXT: stp x11, x12, [x8]
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; CHECK-NEXT: ret
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%cond = and i32 %In1, 1
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%cbool = icmp eq i32 %cond, 0
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%res = select i1 %cbool, <2 x i128> %In2, <2 x i128> %In3
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store <2 x i128> %res, <2 x i128> *%Out
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ret void
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}
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; Check case when scalar size is not power of 2.
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define void @bar(i32 %In1, <2 x i96> %In2, <2 x i96> %In3, <2 x i96> *%Out) {
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; CHECK-LABEL: bar:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w10, w0, #0x1
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; CHECK-NEXT: fmov s0, wzr
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; CHECK-NEXT: fmov s1, w10
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; CHECK-NEXT: cmeq v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ldp x11, x8, [sp, #8]
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; CHECK-NEXT: ldr x9, [sp]
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; CHECK-NEXT: dup v1.4s, v0.s[0]
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; CHECK-NEXT: mov x10, v1.d[1]
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; CHECK-NEXT: lsr x10, x10, #32
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; CHECK-NEXT: tst w10, #0x1
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; CHECK-NEXT: fmov w10, s0
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; CHECK-NEXT: csel x11, x5, x11, ne
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; CHECK-NEXT: csel x9, x4, x9, ne
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; CHECK-NEXT: tst w10, #0x1
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; CHECK-NEXT: csel x10, x3, x7, ne
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; CHECK-NEXT: csel x12, x2, x6, ne
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; CHECK-NEXT: stur x9, [x8, #12]
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; CHECK-NEXT: str x12, [x8]
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; CHECK-NEXT: str w10, [x8, #8]
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; CHECK-NEXT: str w11, [x8, #20]
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; CHECK-NEXT: ret
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%cond = and i32 %In1, 1
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%cbool = icmp eq i32 %cond, 0
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%res = select i1 %cbool, <2 x i96> %In2, <2 x i96> %In3
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store <2 x i96> %res, <2 x i96> *%Out
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ret void
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}
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