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[PowerPC] Use getSignedTargetConstant in SelectOptimalAddrMode. (#127305)

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Fixes #127298.
This commit is contained in:
Craig Topper 2025-02-15 14:13:32 -08:00 committed by GitHub
parent e5f5517f91
commit 256145b4b0
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GPG Key ID: B5690EEEBB952194
2 changed files with 15 additions and 2 deletions
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4
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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@ -19110,8 +19110,8 @@ PPC::AddrMode PPCTargetLowering::SelectOptimalAddrMode(const SDNode *Parent,
int32_t Addr = (int32_t)CNImm;
// Otherwise, break this down into LIS + Disp.
Disp = DAG.getSignedTargetConstant((int16_t)Addr, DL, MVT::i32);
Base =
DAG.getTargetConstant((Addr - (int16_t)Addr) >> 16, DL, MVT::i32);
Base = DAG.getSignedTargetConstant((Addr - (int16_t)Addr) >> 16, DL,
MVT::i32);
uint32_t LIS = CNType == MVT::i32 ? PPC::LIS : PPC::LIS8;
Base = SDValue(DAG.getMachineNode(LIS, DL, CNType, Base), 0);
break;

13
llvm/test/CodeGen/PowerPC/pr127298.ll Normal file
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@ -0,0 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=powerpc | FileCheck %s
define void @foo() {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %Entry
; CHECK-NEXT: lis 3, -8530
; CHECK-NEXT: lbz 3, -16657(3)
; CHECK-NEXT: blr
Entry:
%0 = load volatile i8, ptr inttoptr (i32 -559038737 to ptr), align 1
ret void
}