[SPIR-V] Address comments on SPV_INTEL_masked_gather_scatter extension implementation (#186336)

Address comments left after merge of #185418

llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp

@@ -3306,7 +3306,7 @@ bool SPIRVEmitIntrinsics::processMaskedMemIntrinsic(IntrinsicInst &I) {
     Value *Mask = I.getArgOperand(1);
     Value *Passthru = I.getArgOperand(2);
 
-    // Alignment is stored as a parameter attribute, not as a regular parameter
+    // Alignment is stored as a parameter attribute, not as a regular parameter.
     uint32_t Alignment = I.getParamAlign(0).valueOrOne().value();
 
     SmallVector<Value *, 4> Args = {Ptrs, B.getInt32(Alignment), Mask,
@@ -3338,7 +3338,7 @@ bool SPIRVEmitIntrinsics::processMaskedMemIntrinsic(IntrinsicInst &I) {
     Value *Mask = I.getArgOperand(2);
 
     // Alignment is stored as a parameter attribute on the ptrs parameter (arg
-    // 1)
+    // 1).
     uint32_t Alignment = I.getParamAlign(1).valueOrOne().value();
 
     SmallVector<Value *, 4> Args = {Values, Ptrs, B.getInt32(Alignment), Mask};

llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

@@ -316,7 +316,6 @@ SPIRVTypeInst
 SPIRVGlobalRegistry::getOpTypeVector(uint32_t NumElems, SPIRVTypeInst ElemType,
                                      MachineIRBuilder &MIRBuilder) {
   auto EleOpc = ElemType->getOpcode();
-  (void)EleOpc;
   assert(NumElems >= 2 && "SPIR-V OpTypeVector requires at least 2 components");
 
   if (EleOpc == SPIRV::OpTypePointer) {

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -1760,11 +1760,11 @@ bool SPIRVInstructionSelector::selectMaskedGather(Register ResVReg,
   // 3: alignment (i32 immediate)
   // 4: mask (vector of i1)
   // 5: passthru/fill value
-  Register PtrsReg = I.getOperand(2).getReg();
-  uint32_t Alignment = I.getOperand(3).getImm();
-  Register MaskReg = I.getOperand(4).getReg();
-  Register PassthruReg = I.getOperand(5).getReg();
-  Register AlignmentReg = buildI32Constant(Alignment, I);
+  const Register PtrsReg = I.getOperand(2).getReg();
+  const uint32_t Alignment = I.getOperand(3).getImm();
+  const Register MaskReg = I.getOperand(4).getReg();
+  const Register PassthruReg = I.getOperand(5).getReg();
+  const Register AlignmentReg = buildI32Constant(Alignment, I);
 
   MachineBasicBlock &BB = *I.getParent();
   auto MIB =
@@ -1787,11 +1787,11 @@ bool SPIRVInstructionSelector::selectMaskedScatter(MachineInstr &I) const {
   // 2: vector of pointers
   // 3: alignment (i32 immediate)
   // 4: mask (vector of i1)
-  Register ValuesReg = I.getOperand(1).getReg();
-  Register PtrsReg = I.getOperand(2).getReg();
-  uint32_t Alignment = I.getOperand(3).getImm();
-  Register MaskReg = I.getOperand(4).getReg();
-  Register AlignmentReg = buildI32Constant(Alignment, I);
+  const Register ValuesReg = I.getOperand(1).getReg();
+  const Register PtrsReg = I.getOperand(2).getReg();
+  const uint32_t Alignment = I.getOperand(3).getImm();
+  const Register MaskReg = I.getOperand(4).getReg();
+  const Register AlignmentReg = buildI32Constant(Alignment, I);
   MachineBasicBlock &BB = *I.getParent();
 
   auto MIB =

llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/masked-gather-no-extension.ll

@@ -1,3 +1,7 @@
+; Test that llvm.masked.gather produces an error when the
+; SPV_INTEL_masked_gather_scatter extension is not enabled, since vector of
+; pointers is not supported in SPIR-V without this extension.
+
 ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
 
 declare <4 x i32> @llvm.masked.gather.v4i32.v4p1(<4 x ptr addrspace(1)>, i32, <4 x i1>, <4 x i32>)

llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/masked-gather-scatter.ll

@@ -1,3 +1,7 @@
+; Test that llvm.masked.gather and llvm.masked.scatter intrinsics are correctly
+; lowered to OpMaskedGatherINTEL and OpMaskedScatterINTEL SPIR-V instructions
+; when the SPV_INTEL_masked_gather_scatter extension is enabled.
+
 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_masked_gather_scatter %s -o - | FileCheck %s
 ; TODO: spirv-val does not support vector operands in OpConvertPtrToU and OpConvertUToPtr with SPV_INTEL_masked_gather_scatter
 ; RUNx: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_masked_gather_scatter %s -o - -filetype=obj | spirv-val %}

llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/masked-scatter-no-extension.ll

@@ -1,3 +1,7 @@
+; Test that llvm.masked.scatter produces an error when the
+; SPV_INTEL_masked_gather_scatter extension is not enabled, since vector of
+; pointers is not supported in SPIR-V without this extension.
+
 ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
 
 declare void @llvm.masked.scatter.v4i32.v4p1(<4 x i32>, <4 x ptr addrspace(1)>, i32, <4 x i1>)

llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/vector-of-pointers-no-extension.ll

@@ -1,3 +1,6 @@
+; Test that ptrtoint on a vector of pointers without the
+; SPV_INTEL_masked_gather_scatter extension produces an error.
+
 ; RUN: not llc -O0 -mtriple=spirv64-unknown-unknown %s -o /dev/null 2>&1 | FileCheck %s
 
 ; CHECK: error:{{.*}}Vector of pointers requires SPV_INTEL_masked_gather_scatter extension

llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_masked_gather_scatter/vector-of-pointers-ptrtoint.ll

@@ -1,3 +1,7 @@
+; Test that ptrtoint and inttoptr on vectors of pointers are correctly lowered
+; to OpConvertPtrToU and OpConvertUToPtr when SPV_INTEL_masked_gather_scatter
+; extension is enabled.
+
 ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_masked_gather_scatter %s -o - | FileCheck %s
 ; TODO: spirv-val does not support vector operands in OpConvertPtrToU and OpConvertUToPtr with SPV_INTEL_masked_gather_scatter
 ; RUNx: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown --spirv-ext=+SPV_INTEL_masked_gather_scatter %s -o - -filetype=obj | spirv-val %}