[AArch64] Additional saddlv store tests. NFC
The select-intrinsic-uaddlv.mir test now lower via G_SADDLV / G_UADDLV so is no longer needed.
This commit is contained in:
David Green
parent
fa9f6b5828
commit
277ca48f2f
@ -1,109 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: uaddlv_v8s8
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: uaddlv_v8s8
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; CHECK: %copy:fpr64 = COPY $d0
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; CHECK: [[UADDLVv8i8v:%[0-9]+]]:fpr16 = UADDLVv8i8v %copy
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UADDLVv8i8v]], %subreg.hsub
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; CHECK: %intrin:fpr32 = COPY [[INSERT_SUBREG]].ssub
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; CHECK: $w0 = COPY %intrin
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; CHECK: RET_ReallyLR implicit $w0
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%copy:fpr(<8 x s8>) = COPY $d0
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%intrin:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), %copy(<8 x s8>)
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$w0 = COPY %intrin(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddlv_v16s8
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: uaddlv_v16s8
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; CHECK: %copy:fpr128 = COPY $q0
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; CHECK: [[UADDLVv16i8v:%[0-9]+]]:fpr16 = UADDLVv16i8v %copy
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UADDLVv16i8v]], %subreg.hsub
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; CHECK: %intrin:fpr32 = COPY [[INSERT_SUBREG]].ssub
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; CHECK: $w0 = COPY %intrin
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; CHECK: RET_ReallyLR implicit $w0
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%copy:fpr(<16 x s8>) = COPY $q0
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%intrin:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), %copy(<16 x s8>)
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$w0 = COPY %intrin(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddlv_v4s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $d0
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; CHECK-LABEL: name: uaddlv_v4s16
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; CHECK: %copy:fpr64 = COPY $d0
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; CHECK: [[UADDLVv4i16v:%[0-9]+]]:fpr32 = UADDLVv4i16v %copy
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UADDLVv4i16v]], %subreg.ssub
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; CHECK: %intrin:fpr32 = COPY [[INSERT_SUBREG]].ssub
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; CHECK: $w0 = COPY %intrin
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; CHECK: RET_ReallyLR implicit $w0
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%copy:fpr(<4 x s16>) = COPY $d0
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%intrin:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), %copy(<4 x s16>)
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$w0 = COPY %intrin(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddlv_v8s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: uaddlv_v8s16
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; CHECK: %copy:fpr128 = COPY $q0
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; CHECK: [[UADDLVv8i16v:%[0-9]+]]:fpr32 = UADDLVv8i16v %copy
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UADDLVv8i16v]], %subreg.ssub
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; CHECK: %intrin:fpr32 = COPY [[INSERT_SUBREG]].ssub
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; CHECK: $w0 = COPY %intrin
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; CHECK: RET_ReallyLR implicit $w0
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%copy:fpr(<8 x s16>) = COPY $q0
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%intrin:fpr(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), %copy(<8 x s16>)
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$w0 = COPY %intrin(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddlv_v4s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $q0
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; CHECK-LABEL: name: uaddlv_v4s32
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; CHECK: %copy:fpr128 = COPY $q0
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; CHECK: [[UADDLVv4i32v:%[0-9]+]]:fpr64 = UADDLVv4i32v %copy
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[UADDLVv4i32v]], %subreg.dsub
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; CHECK: %intrin:fpr64 = COPY [[INSERT_SUBREG]].dsub
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; CHECK: $x0 = COPY %intrin
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; CHECK: RET_ReallyLR implicit $x0
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%copy:fpr(<4 x s32>) = COPY $q0
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%intrin:fpr(s64) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), %copy(<4 x s32>)
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$x0 = COPY %intrin(s64)
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RET_ReallyLR implicit $x0
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@ -485,3 +485,101 @@ entry:
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store <4 x float> %2, ptr %0, align 8
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ret void
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}
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define void @store_saddlv_v8i8(ptr %H, <8 x i8> %sum_h, i32 %idx) {
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; CHECK-LABEL: store_saddlv_v8i8:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: saddlv.8b h0, v0
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; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: sbfiz x9, x1, #3, #32
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; CHECK-NEXT: smov.h w8, v0[0]
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; CHECK-NEXT: str w8, [x0, x9]
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; CHECK-NEXT: ret
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entry:
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%vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8> %sum_h)
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom
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store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8
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ret void
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}
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define void @store_saddlv_v16i8(ptr %H, <16 x i8> %sum_h, i32 %idx) {
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; CHECK-LABEL: store_saddlv_v16i8:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: saddlv.16b h0, v0
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; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: sbfiz x9, x1, #3, #32
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; CHECK-NEXT: smov.h w8, v0[0]
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; CHECK-NEXT: str w8, [x0, x9]
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; CHECK-NEXT: ret
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entry:
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%vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8> %sum_h)
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom
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store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8
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ret void
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}
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define void @store_saddlv_v4i16(ptr %H, <4 x i16> %sum_h, i32 %idx) {
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; CHECK-LABEL: store_saddlv_v4i16:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: saddlv.4h s0, v0
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; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: sbfiz x8, x1, #3, #32
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: str w9, [x0, x8]
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; CHECK-NEXT: ret
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entry:
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%vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16> %sum_h)
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom
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store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8
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ret void
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}
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define void @store_saddlv_v8i16(ptr %H, <8 x i16> %sum_h, i32 %idx) {
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; CHECK-LABEL: store_saddlv_v8i16:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: saddlv.8h s0, v0
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; CHECK-NEXT: ; kill: def $w1 killed $w1 def $x1
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; CHECK-NEXT: sbfiz x8, x1, #3, #32
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: str w9, [x0, x8]
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; CHECK-NEXT: ret
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entry:
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%vaddlvq_s32.i = tail call i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16> %sum_h)
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom
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store i32 %vaddlvq_s32.i, ptr %arrayidx, align 8
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ret void
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}
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define void @store_saddlv_v2i32(ptr %H, <2 x i32> %sum_h, i32 %idx) {
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; CHECK-LABEL: store_saddlv_v2i32:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: saddlp.1d v0, v0
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: str x8, [x0, w1, sxtw #3]
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; CHECK-NEXT: ret
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entry:
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%vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v2i32(<2 x i32> %sum_h)
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom
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store i64 %vaddlvq_s32.i, ptr %arrayidx, align 8
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ret void
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}
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define void @store_saddlv_v4i32(ptr %H, <4 x i32> %sum_h, i32 %idx) {
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; CHECK-LABEL: store_saddlv_v4i32:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: saddlv.4s d0, v0
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: str x8, [x0, w1, sxtw #3]
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; CHECK-NEXT: ret
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entry:
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%vaddlvq_s32.i = tail call i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32> %sum_h)
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%idxprom = sext i32 %idx to i64
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%arrayidx = getelementptr inbounds i64, ptr %H, i64 %idxprom
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store i64 %vaddlvq_s32.i, ptr %arrayidx, align 8
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ret void
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}
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@ -1,83 +1,45 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -global-isel=1 -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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; RUN: llc < %s -mtriple=arm64-none-linux-gnu -mattr=+neon -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)
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declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)
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declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)
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declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)
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declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
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declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
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declare i64 @llvm.aarch64.neon.uaddlv.i64.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.uaddlv.i32.v16i8(<16 x i8>)
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declare i64 @llvm.aarch64.neon.saddlv.i64.v4i32(<4 x i32>)
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declare i32 @llvm.aarch64.neon.saddlv.i32.v8i16(<8 x i16>)
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declare i32 @llvm.aarch64.neon.saddlv.i32.v16i8(<16 x i8>)
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declare i32 @llvm.aarch64.neon.uaddlv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.uaddlv.i32.v8i8(<8 x i8>)
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declare i32 @llvm.aarch64.neon.saddlv.i32.v4i16(<4 x i16>)
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declare i32 @llvm.aarch64.neon.saddlv.i32.v8i8(<8 x i8>)
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define i16 @test_vaddlv_s8(<8 x i8> %a) {
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