diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td index 807b69dc85eb..701a4c7923ef 100644 --- a/llvm/lib/Target/AMDGPU/EXPInstructions.td +++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td @@ -38,7 +38,7 @@ class EXP_Pseudo // Real instruction with optional asm operands "compr" and "vm". class EXP_Real_ComprVM - : EXPCommon<0, ps.done, "exp$tgt $src0, $src1, $src2, $src3" + : EXPCommon<0, ps.done, "exp$tgt, $src0, $src1, $src2, $src3" #!if(ps.done, " done", "")#"$compr$vm">, SIMCInstr { let AsmMatchConverter = "cvtExp"; @@ -46,7 +46,7 @@ class EXP_Real_ComprVM // Real instruction with optional asm operand "row_en". class EXP_Real_Row - : EXPCommon, SIMCInstr { let AsmMatchConverter = "cvtExp"; diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll index f88d0e07f284..4406144be8d5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/i1-copy.ll @@ -8,7 +8,7 @@ define amdgpu_ps void @i1_vcc_to_vcc_copy(i32 %val, float %a0, float %a1, float ; WAVE64-NEXT: v_cmp_eq_u32_e32 vcc, 2, v0 ; WAVE64-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; WAVE64-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm +; WAVE64-NEXT: exp mrt0, v0, v1, v0, v0 done vm ; WAVE64-NEXT: s_endpgm ; ; WAVE32-LABEL: i1_vcc_to_vcc_copy: @@ -16,7 +16,7 @@ define amdgpu_ps void @i1_vcc_to_vcc_copy(i32 %val, float %a0, float %a1, float ; WAVE32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; WAVE32-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo ; WAVE32-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo -; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm +; WAVE32-NEXT: exp mrt0, v0, v1, v0, v0 done vm ; WAVE32-NEXT: s_endpgm main_body: %vcc = icmp eq i32 %val, 2 @@ -35,7 +35,7 @@ define amdgpu_ps void @i1_sgpr_to_vcc_copy(i32 inreg %val, float %a0, float %a1, ; WAVE64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; WAVE64-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; WAVE64-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc -; WAVE64-NEXT: exp mrt0 v0, v1, v0, v0 done vm +; WAVE64-NEXT: exp mrt0, v0, v1, v0, v0 done vm ; WAVE64-NEXT: s_endpgm ; ; WAVE32-LABEL: i1_sgpr_to_vcc_copy: @@ -46,7 +46,7 @@ define amdgpu_ps void @i1_sgpr_to_vcc_copy(i32 inreg %val, float %a0, float %a1, ; WAVE32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; WAVE32-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; WAVE32-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo -; WAVE32-NEXT: exp mrt0 v0, v1, v0, v0 done vm +; WAVE32-NEXT: exp mrt0, v0, v1, v0, v0 done vm ; WAVE32-NEXT: s_endpgm main_body: %uniform_i1 = icmp eq i32 %val, 2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll index bd6634f25077..1ad8490c3f2f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll @@ -21,7 +21,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m ; GFX11-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7 -; GFX11-NEXT: exp mrt0 v3, v2, v5, v4 done +; GFX11-NEXT: exp mrt0, v3, v2, v5, v4 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: v_interp_f32: @@ -40,7 +40,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m ; GFX12-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7 -; GFX12-NEXT: export mrt0 v3, v2, v5, v4 done +; GFX12-NEXT: export mrt0, v3, v2, v5, v4 done ; GFX12-NEXT: s_endpgm main_body: %p0 = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %m0) @@ -76,7 +76,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr ; GFX11-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7 -; GFX11-NEXT: exp mrt0 v6, v7, v8, v4 done +; GFX11-NEXT: exp mrt0, v6, v7, v8, v4 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: v_interp_f32_many: @@ -101,7 +101,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr ; GFX12-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7 -; GFX12-NEXT: export mrt0 v6, v7, v8, v4 done +; GFX12-NEXT: export mrt0, v6, v7, v8, v4 done ; GFX12-NEXT: s_endpgm main_body: %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0) @@ -143,7 +143,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7 ; GFX11-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7 -; GFX11-NEXT: exp mrt0 v6, v7, v8, v0 done +; GFX11-NEXT: exp mrt0, v6, v7, v8, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: v_interp_f32_many_vm: @@ -168,7 +168,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7 ; GFX12-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7 -; GFX12-NEXT: export mrt0 v6, v7, v8, v0 done +; GFX12-NEXT: export mrt0, v6, v7, v8, v0 done ; GFX12-NEXT: s_endpgm main_body: %i.ptr = getelementptr float, ptr addrspace(1) %ptr, i32 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll index 8a53c862371c..491f51d0b057 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll @@ -13,11 +13,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB0_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: static_exact: @@ -28,11 +28,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB0_2: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: static_exact: @@ -43,11 +43,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB0_2: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: static_exact: @@ -58,11 +58,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB0_2: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %c0 = fcmp olt float %arg0, 0.000000e+00 @@ -85,11 +85,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: s_and_b64 exec, exec, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB1_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: dynamic_exact: @@ -103,11 +103,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB1_2: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: dynamic_exact: @@ -121,11 +121,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB1_2: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: dynamic_exact: @@ -139,11 +139,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB1_2: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %c0 = fcmp olt float %arg0, 0.000000e+00 @@ -175,11 +175,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; SI-NEXT: .LBB2_3: ; %.continue ; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB2_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: branch: @@ -202,11 +202,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; GFX9-NEXT: .LBB2_3: ; %.continue ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB2_4: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: branch: @@ -229,11 +229,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; GFX10-32-NEXT: .LBB2_3: ; %.continue ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB2_4: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: branch: @@ -256,11 +256,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; GFX10-64-NEXT: .LBB2_3: ; %.continue ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB2_4: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %i0 = fptosi float %arg0 to i32 @@ -306,7 +306,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; SI-NEXT: s_branch .LBB3_5 ; SI-NEXT: .LBB3_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB3_5: ; @@ -335,7 +335,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX9-NEXT: s_branch .LBB3_5 ; GFX9-NEXT: .LBB3_4: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB3_5: ; @@ -364,7 +364,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-32-NEXT: s_branch .LBB3_5 ; GFX10-32-NEXT: .LBB3_4: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB3_5: ; @@ -393,7 +393,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-64-NEXT: s_branch .LBB3_5 ; GFX10-64-NEXT: .LBB3_4: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB3_5: .entry: @@ -440,7 +440,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; SI-NEXT: s_branch .LBB4_5 ; SI-NEXT: .LBB4_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB4_5: ; @@ -469,7 +469,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX9-NEXT: s_branch .LBB4_5 ; GFX9-NEXT: .LBB4_4: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB4_5: ; @@ -498,7 +498,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-32-NEXT: s_branch .LBB4_5 ; GFX10-32-NEXT: .LBB4_4: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB4_5: ; @@ -527,7 +527,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-64-NEXT: s_branch .LBB4_5 ; GFX10-64-NEXT: .LBB4_4: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB4_5: .entry: @@ -569,7 +569,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; SI-NEXT: s_branch .LBB5_3 ; SI-NEXT: .LBB5_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB5_3: ; @@ -593,7 +593,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; GFX9-NEXT: s_branch .LBB5_3 ; GFX9-NEXT: .LBB5_2: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB5_3: ; @@ -617,7 +617,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10-32-NEXT: s_branch .LBB5_3 ; GFX10-32-NEXT: .LBB5_2: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB5_3: ; @@ -641,7 +641,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10-64-NEXT: s_branch .LBB5_3 ; GFX10-64-NEXT: .LBB5_2: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB5_3: .entry: @@ -698,11 +698,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: v_mov_b32_e32 v0, 0x3c00 ; SI-NEXT: v_bfrev_b32_e32 v1, 60 -; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; SI-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB6_7: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: wqm_deriv: @@ -746,11 +746,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 60 -; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; GFX9-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB6_7: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: wqm_deriv: @@ -792,11 +792,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60 -; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; GFX10-32-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB6_7: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: wqm_deriv: @@ -838,11 +838,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60 -; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; GFX10-64-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB6_7: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %p0 = extractelement <2 x float> %input, i32 0 @@ -939,11 +939,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: v_mov_b32_e32 v0, 0x3c00 ; SI-NEXT: v_bfrev_b32_e32 v1, 60 -; SI-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; SI-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB7_9: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: wqm_deriv_loop: @@ -1005,11 +1005,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; GFX9-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX9-NEXT: v_bfrev_b32_e32 v1, 60 -; GFX9-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; GFX9-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB7_9: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: wqm_deriv_loop: @@ -1068,11 +1068,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-32-NEXT: v_bfrev_b32_e32 v1, 60 -; GFX10-32-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; GFX10-32-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB7_9: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: wqm_deriv_loop: @@ -1132,11 +1132,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: v_mov_b32_e32 v0, 0x3c00 ; GFX10-64-NEXT: v_bfrev_b32_e32 v1, 60 -; GFX10-64-NEXT: exp mrt0 v0, v0, v1, v1 done compr vm +; GFX10-64-NEXT: exp mrt0, v0, v0, v1, v1 done compr vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB7_9: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %p0 = extractelement <2 x float> %input, i32 0 diff --git a/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll b/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll index a8f62c8c863d..8170e57b9e75 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic-optimizer-strict-wqm.ll @@ -41,7 +41,7 @@ define amdgpu_ps void @main(i32 %arg) { ; GFX10-NEXT: s_mov_b32 s0, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0 -; GFX10-NEXT: exp mrt0 off, off, off, off +; GFX10-NEXT: exp mrt0, off, off, off, off ; GFX10-NEXT: s_endpgm bb: br label %bb4 diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll index d588c22a8857..92fb34585147 100644 --- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll +++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll @@ -67,7 +67,7 @@ define amdgpu_ps void @main(i32 %0, float %1) { ; ISA-NEXT: v_sqrt_f32_e32 v1, v0 ; ISA-NEXT: ; %bb.9: ; %endloop ; ISA-NEXT: s_or_b64 exec, exec, s[0:1] -; ISA-NEXT: exp mrt0 v1, v1, v1, v1 done vm +; ISA-NEXT: exp mrt0, v1, v1, v1, v1 done vm ; ISA-NEXT: s_endpgm start: %v0 = call float @llvm.amdgcn.interp.p1(float %1, i32 0, i32 0, i32 %0) @@ -162,7 +162,7 @@ define amdgpu_ps void @i1_copy_assert(i1 %v4) { ; ISA-NEXT: s_or_b64 exec, exec, s[0:1] ; ISA-NEXT: v_mov_b32_e32 v0, 0 ; ISA-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[2:3] -; ISA-NEXT: exp mrt0 off, off, off, off +; ISA-NEXT: exp mrt0, off, off, off, off ; ISA-NEXT: s_endpgm start: br label %loop diff --git a/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll b/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll index 04d59131c944..5d50d21d1cc6 100644 --- a/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll +++ b/llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll @@ -38,8 +38,8 @@ define amdgpu_ps void @_amdgpu_ps_main(i32 inreg %PrimMask, <2 x float> %InterpC ; GCN-NEXT: v_mov_b32_dpp v4, v4 dpp8:[1,0,3,2,5,4,7,6] ; GCN-NEXT: v_mov_b32_dpp v5, v5 dpp8:[1,0,3,2,5,4,7,6] ; GCN-NEXT: s_mov_b32 exec_lo, s1 -; GCN-NEXT: exp dual_src_blend0 v3, v2, off, off -; GCN-NEXT: exp dual_src_blend1 v4, v5, off, off done +; GCN-NEXT: exp dual_src_blend0, v3, v2, off, off +; GCN-NEXT: exp dual_src_blend1, v4, v5, off, off done ; GCN-NEXT: s_endpgm .entry: %InterpCenter.i0 = extractelement <2 x float> %InterpCenter, i64 0 diff --git a/llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll b/llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll index 07005fd020e8..4749bcf7ba46 100644 --- a/llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-waitcnt-profiling.ll @@ -861,73 +861,73 @@ define amdgpu_ps void @test_expcnt_exports(float %x, float %y, float %z, float % ; GFX9-EXPAND-LABEL: test_expcnt_exports: ; GFX9-EXPAND: ; %bb.0: ; %entry ; GFX9-EXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX9-EXPAND-NEXT: exp mrt0 v0, v1, v2, v3 -; GFX9-EXPAND-NEXT: exp mrt1 v3, v2, v1, v0 -; GFX9-EXPAND-NEXT: exp mrt2 v0, v3, v1, v2 -; GFX9-EXPAND-NEXT: exp param0 v4, v4, v4, v4 done +; GFX9-EXPAND-NEXT: exp mrt0, v0, v1, v2, v3 +; GFX9-EXPAND-NEXT: exp mrt1, v3, v2, v1, v0 +; GFX9-EXPAND-NEXT: exp mrt2, v0, v3, v1, v2 +; GFX9-EXPAND-NEXT: exp param0, v4, v4, v4, v4 done ; GFX9-EXPAND-NEXT: s_endpgm ; ; GFX9-NOEXPAND-LABEL: test_expcnt_exports: ; GFX9-NOEXPAND: ; %bb.0: ; %entry ; GFX9-NOEXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX9-NOEXPAND-NEXT: exp mrt0 v0, v1, v2, v3 -; GFX9-NOEXPAND-NEXT: exp mrt1 v3, v2, v1, v0 -; GFX9-NOEXPAND-NEXT: exp mrt2 v0, v3, v1, v2 -; GFX9-NOEXPAND-NEXT: exp param0 v4, v4, v4, v4 done +; GFX9-NOEXPAND-NEXT: exp mrt0, v0, v1, v2, v3 +; GFX9-NOEXPAND-NEXT: exp mrt1, v3, v2, v1, v0 +; GFX9-NOEXPAND-NEXT: exp mrt2, v0, v3, v1, v2 +; GFX9-NOEXPAND-NEXT: exp param0, v4, v4, v4, v4 done ; GFX9-NOEXPAND-NEXT: s_endpgm ; ; GFX10-EXPAND-LABEL: test_expcnt_exports: ; GFX10-EXPAND: ; %bb.0: ; %entry ; GFX10-EXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX10-EXPAND-NEXT: exp mrt0 v0, v1, v2, v3 -; GFX10-EXPAND-NEXT: exp mrt1 v3, v2, v1, v0 -; GFX10-EXPAND-NEXT: exp mrt2 v0, v3, v1, v2 -; GFX10-EXPAND-NEXT: exp param0 v4, v4, v4, v4 done +; GFX10-EXPAND-NEXT: exp mrt0, v0, v1, v2, v3 +; GFX10-EXPAND-NEXT: exp mrt1, v3, v2, v1, v0 +; GFX10-EXPAND-NEXT: exp mrt2, v0, v3, v1, v2 +; GFX10-EXPAND-NEXT: exp param0, v4, v4, v4, v4 done ; GFX10-EXPAND-NEXT: s_endpgm ; ; GFX10-NOEXPAND-LABEL: test_expcnt_exports: ; GFX10-NOEXPAND: ; %bb.0: ; %entry ; GFX10-NOEXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX10-NOEXPAND-NEXT: exp mrt0 v0, v1, v2, v3 -; GFX10-NOEXPAND-NEXT: exp mrt1 v3, v2, v1, v0 -; GFX10-NOEXPAND-NEXT: exp mrt2 v0, v3, v1, v2 -; GFX10-NOEXPAND-NEXT: exp param0 v4, v4, v4, v4 done +; GFX10-NOEXPAND-NEXT: exp mrt0, v0, v1, v2, v3 +; GFX10-NOEXPAND-NEXT: exp mrt1, v3, v2, v1, v0 +; GFX10-NOEXPAND-NEXT: exp mrt2, v0, v3, v1, v2 +; GFX10-NOEXPAND-NEXT: exp param0, v4, v4, v4, v4 done ; GFX10-NOEXPAND-NEXT: s_endpgm ; ; GFX11-EXPAND-LABEL: test_expcnt_exports: ; GFX11-EXPAND: ; %bb.0: ; %entry ; GFX11-EXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX11-EXPAND-NEXT: exp mrt0 v0, v1, v2, v3 -; GFX11-EXPAND-NEXT: exp mrt1 v3, v2, v1, v0 -; GFX11-EXPAND-NEXT: exp mrt2 v0, v3, v1, v2 -; GFX11-EXPAND-NEXT: exp invalid_target_32 v4, v4, v4, v4 done +; GFX11-EXPAND-NEXT: exp mrt0, v0, v1, v2, v3 +; GFX11-EXPAND-NEXT: exp mrt1, v3, v2, v1, v0 +; GFX11-EXPAND-NEXT: exp mrt2, v0, v3, v1, v2 +; GFX11-EXPAND-NEXT: exp invalid_target_32, v4, v4, v4, v4 done ; GFX11-EXPAND-NEXT: s_endpgm ; ; GFX11-NOEXPAND-LABEL: test_expcnt_exports: ; GFX11-NOEXPAND: ; %bb.0: ; %entry ; GFX11-NOEXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX11-NOEXPAND-NEXT: exp mrt0 v0, v1, v2, v3 -; GFX11-NOEXPAND-NEXT: exp mrt1 v3, v2, v1, v0 -; GFX11-NOEXPAND-NEXT: exp mrt2 v0, v3, v1, v2 -; GFX11-NOEXPAND-NEXT: exp invalid_target_32 v4, v4, v4, v4 done +; GFX11-NOEXPAND-NEXT: exp mrt0, v0, v1, v2, v3 +; GFX11-NOEXPAND-NEXT: exp mrt1, v3, v2, v1, v0 +; GFX11-NOEXPAND-NEXT: exp mrt2, v0, v3, v1, v2 +; GFX11-NOEXPAND-NEXT: exp invalid_target_32, v4, v4, v4, v4 done ; GFX11-NOEXPAND-NEXT: s_endpgm ; ; GFX12-EXPAND-LABEL: test_expcnt_exports: ; GFX12-EXPAND: ; %bb.0: ; %entry ; GFX12-EXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX12-EXPAND-NEXT: export mrt0 v0, v1, v2, v3 -; GFX12-EXPAND-NEXT: export mrt1 v3, v2, v1, v0 -; GFX12-EXPAND-NEXT: export mrt2 v0, v3, v1, v2 -; GFX12-EXPAND-NEXT: export invalid_target_32 v4, v4, v4, v4 done +; GFX12-EXPAND-NEXT: export mrt0, v0, v1, v2, v3 +; GFX12-EXPAND-NEXT: export mrt1, v3, v2, v1, v0 +; GFX12-EXPAND-NEXT: export mrt2, v0, v3, v1, v2 +; GFX12-EXPAND-NEXT: export invalid_target_32, v4, v4, v4, v4 done ; GFX12-EXPAND-NEXT: s_endpgm ; ; GFX12-NOEXPAND-LABEL: test_expcnt_exports: ; GFX12-NOEXPAND: ; %bb.0: ; %entry ; GFX12-NOEXPAND-NEXT: v_mov_b32_e32 v4, 1.0 -; GFX12-NOEXPAND-NEXT: export mrt0 v0, v1, v2, v3 -; GFX12-NOEXPAND-NEXT: export mrt1 v3, v2, v1, v0 -; GFX12-NOEXPAND-NEXT: export mrt2 v0, v3, v1, v2 -; GFX12-NOEXPAND-NEXT: export invalid_target_32 v4, v4, v4, v4 done +; GFX12-NOEXPAND-NEXT: export mrt0, v0, v1, v2, v3 +; GFX12-NOEXPAND-NEXT: export mrt1, v3, v2, v1, v0 +; GFX12-NOEXPAND-NEXT: export mrt2, v0, v3, v1, v2 +; GFX12-NOEXPAND-NEXT: export invalid_target_32, v4, v4, v4, v4 done ; GFX12-NOEXPAND-NEXT: s_endpgm entry: ; Multiple MRT exports diff --git a/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll b/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll index 80d4fa69be42..ec5a431cde63 100644 --- a/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll +++ b/llvm/test/CodeGen/AMDGPU/group-image-instructions.ll @@ -158,7 +158,7 @@ define amdgpu_ps void @group_image_sample(i32 inreg noundef %globalTable, i32 in ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cvt_pk_rtz_f16_f32_e32 v0, v0, v1 ; GFX11-NEXT: v_cvt_pk_rtz_f16_f32_e32 v1, v4, v5 -; GFX11-NEXT: exp mrt0 v0, v1, off, off done +; GFX11-NEXT: exp mrt0, v0, v1, off, off done ; GFX11-NEXT: s_endpgm .entry: %i = call i64 @llvm.amdgcn.s.getpc() diff --git a/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll b/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll index fe462fb44b4a..0dd4e88b21fe 100644 --- a/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/i1-copy-from-loop.ll @@ -50,7 +50,7 @@ define amdgpu_ps void @i1_copy_from_loop(ptr addrspace(8) inreg %rsrc, i32 %tid) ; SI-NEXT: s_and_saveexec_b64 s[0:1], s[6:7] ; SI-NEXT: s_cbranch_execz .LBB0_9 ; SI-NEXT: ; %bb.8: ; %if -; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt0, v0, v0, v0, v0 done vm ; SI-NEXT: .LBB0_9: ; %end ; SI-NEXT: s_endpgm entry: diff --git a/llvm/test/CodeGen/AMDGPU/imm.ll b/llvm/test/CodeGen/AMDGPU/imm.ll index 21390003ee56..c6e077333ecf 100644 --- a/llvm/test/CodeGen/AMDGPU/imm.ll +++ b/llvm/test/CodeGen/AMDGPU/imm.ll @@ -2623,14 +2623,14 @@ define amdgpu_vs void @literal_folding(float %arg) { ; GCN: ; %bb.0: ; %main_body ; GCN-NEXT: v_mul_f32_e32 v1, 0x3f4353f8, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0xbf4353f8, v0 -; GCN-NEXT: exp pos0 v1, v1, v0, v0 done +; GCN-NEXT: exp pos0, v1, v1, v0, v0 done ; GCN-NEXT: s_endpgm ; ; GFX942-LABEL: literal_folding: ; GFX942: ; %bb.0: ; %main_body ; GFX942-NEXT: v_mul_f32_e32 v1, 0x3f4353f8, v0 ; GFX942-NEXT: v_mul_f32_e32 v0, 0xbf4353f8, v0 -; GFX942-NEXT: exp pos0 v1, v1, v0, v0 done +; GFX942-NEXT: exp pos0, v1, v1, v0, v0 done ; GFX942-NEXT: s_endpgm main_body: %tmp = fmul float %arg, 0x3FE86A7F00000000 diff --git a/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll b/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll index 96ca13f6818c..5079fae8946a 100644 --- a/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll +++ b/llvm/test/CodeGen/AMDGPU/issue98474-need-live-out-undef-subregister-def.ll @@ -17,11 +17,11 @@ define amdgpu_vs void @test(i32 inreg %cmp, i32 %e0) { ; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: buffer_load_format_xy v[1:2], v1, s[0:3], 0 idxen ; CHECK-NEXT: s_waitcnt vmcnt(0) -; CHECK-NEXT: exp mrt0 v0, v1, v2, v0 +; CHECK-NEXT: exp mrt0, v0, v1, v2, v0 ; CHECK-NEXT: s_endpgm ; CHECK-NEXT: .LBB0_2: ; CHECK-NEXT: v_mov_b32_e32 v1, 0 -; CHECK-NEXT: exp mrt0 v0, v1, v2, v0 +; CHECK-NEXT: exp mrt0, v0, v1, v2, v0 ; CHECK-NEXT: s_endpgm entry: %cond = icmp eq i32 %cmp, 0 diff --git a/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll b/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll index 684e3257a129..fdcff3b19f75 100644 --- a/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/kill-infinite-loop.ll @@ -34,12 +34,12 @@ define amdgpu_ps void @return_void(float %0) #0 { ; CHECK-NEXT: ; %bb.4: ; %end ; CHECK-NEXT: v_mov_b32_e32 v0, 1.0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0 -; CHECK-NEXT: exp mrt0 v1, v1, v1, v0 done vm +; CHECK-NEXT: exp mrt0, v1, v1, v1, v0 done vm ; CHECK-NEXT: .LBB0_5: ; %UnifiedReturnBlock ; CHECK-NEXT: s_endpgm ; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: exp null off, off, off, off done vm +; CHECK-NEXT: exp null, off, off, off, off done vm ; CHECK-NEXT: s_endpgm main_body: %cmp = fcmp olt float %0, 1.000000e+01 @@ -77,12 +77,12 @@ define amdgpu_ps void @return_void_compr(float %0) #0 { ; CHECK-NEXT: s_cbranch_execz .LBB1_5 ; CHECK-NEXT: ; %bb.4: ; %end ; CHECK-NEXT: v_mov_b32_e32 v0, 0 -; CHECK-NEXT: exp mrt0 v0, off, v0, off done compr vm +; CHECK-NEXT: exp mrt0, v0, off, v0, off done compr vm ; CHECK-NEXT: .LBB1_5: ; %UnifiedReturnBlock ; CHECK-NEXT: s_endpgm ; CHECK-NEXT: .LBB1_6: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: exp null off, off, off, off done vm +; CHECK-NEXT: exp null, off, off, off, off done vm ; CHECK-NEXT: s_endpgm main_body: %cmp = fcmp olt float %0, 1.000000e+01 @@ -115,7 +115,7 @@ define amdgpu_ps void @only_kill() #0 { ; CHECK-NEXT: s_endpgm ; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: exp null off, off, off, off done vm +; CHECK-NEXT: exp null, off, off, off, off done vm ; CHECK-NEXT: s_endpgm main_body: br label %loop @@ -150,7 +150,7 @@ define amdgpu_ps float @return_nonvoid(float %0) #0 { ; CHECK-NEXT: s_branch .LBB3_5 ; CHECK-NEXT: .LBB3_4: ; CHECK-NEXT: s_mov_b64 exec, 0 -; CHECK-NEXT: exp null off, off, off, off done vm +; CHECK-NEXT: exp null, off, off, off, off done vm ; CHECK-NEXT: s_endpgm ; CHECK-NEXT: .LBB3_5: main_body: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll index 44f5c46954d3..3fc0ad84dd1c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bvh.stack.push.pop.rtn.ll @@ -7,7 +7,7 @@ define amdgpu_gs void @test_ds_bvh_stack_push4_pop1(i32 %addr, i32 %data0, <4 x ; CHECK: ; %bb.0: ; CHECK-NEXT: ds_bvh_stack_push4_pop1_rtn_b32 v1, v0, v1, v[2:5] ; CHECK-NEXT: s_wait_dscnt 0x0 -; CHECK-NEXT: export prim v1, off, off, off done +; CHECK-NEXT: export prim, v1, off, off, off done ; CHECK-NEXT: s_endpgm %pair = call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.push4.pop1.rtn(i32 %addr, i32 %data0, <4 x i32> %data1, i32 0) %vdst = extractvalue { i32, i32 } %pair, 0 @@ -21,7 +21,7 @@ define amdgpu_gs void @test_ds_bvh_stack_push4_pop1_1(i32 %addr, i32 %data0, <4 ; CHECK: ; %bb.0: ; CHECK-NEXT: ds_bvh_stack_push4_pop1_rtn_b32 v1, v0, v1, v[2:5] offset:1 ; CHECK-NEXT: s_wait_dscnt 0x0 -; CHECK-NEXT: export prim v1, off, off, off done +; CHECK-NEXT: export prim, v1, off, off, off done ; CHECK-NEXT: s_endpgm %pair = call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.push4.pop1.rtn(i32 %addr, i32 %data0, <4 x i32> %data1, i32 1) %vdst = extractvalue { i32, i32 } %pair, 0 @@ -35,7 +35,7 @@ define amdgpu_gs void @test_ds_bvh_stack_push8_pop1(i32 %addr, i32 %data0, <8 x ; CHECK: ; %bb.0: ; CHECK-NEXT: ds_bvh_stack_push8_pop1_rtn_b32 v1, v0, v1, v[2:9] ; CHECK-NEXT: s_wait_dscnt 0x0 -; CHECK-NEXT: export prim v1, off, off, off done +; CHECK-NEXT: export prim, v1, off, off, off done ; CHECK-NEXT: s_endpgm %pair = call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.push8.pop1.rtn(i32 %addr, i32 %data0, <8 x i32> %data1, i32 0) %vdst = extractvalue { i32, i32 } %pair, 0 @@ -49,7 +49,7 @@ define amdgpu_gs void @test_ds_bvh_stack_push8_pop1_1(i32 %addr, i32 %data0, <8 ; CHECK: ; %bb.0: ; CHECK-NEXT: ds_bvh_stack_push8_pop1_rtn_b32 v1, v0, v1, v[2:9] offset:1 ; CHECK-NEXT: s_wait_dscnt 0x0 -; CHECK-NEXT: export prim v1, off, off, off done +; CHECK-NEXT: export prim, v1, off, off, off done ; CHECK-NEXT: s_endpgm %pair = call { i32, i32 } @llvm.amdgcn.ds.bvh.stack.push8.pop1.rtn(i32 %addr, i32 %data0, <8 x i32> %data1, i32 1) %vdst = extractvalue { i32, i32 } %pair, 0 @@ -63,7 +63,7 @@ define amdgpu_gs void @test_ds_bvh_stack_push8_pop2(i32 %addr, i32 %data0, <8 x ; CHECK: ; %bb.0: ; CHECK-NEXT: ds_bvh_stack_push8_pop2_rtn_b64 v[1:2], v0, v1, v[2:9] ; CHECK-NEXT: s_wait_dscnt 0x0 -; CHECK-NEXT: export prim v1, off, off, off done +; CHECK-NEXT: export prim, v1, off, off, off done ; CHECK-NEXT: s_endpgm %pair = call { i64, i32 } @llvm.amdgcn.ds.bvh.stack.push8.pop2.rtn(i32 %addr, i32 %data0, <8 x i32> %data1, i32 0) %vdst = extractvalue { i64, i32 } %pair, 0 @@ -80,7 +80,7 @@ define amdgpu_gs void @test_ds_bvh_stack_push8_pop2_1(i32 %addr, i32 %data0, <8 ; CHECK: ; %bb.0: ; CHECK-NEXT: ds_bvh_stack_push8_pop2_rtn_b64 v[1:2], v0, v1, v[2:9] offset:1 ; CHECK-NEXT: s_wait_dscnt 0x0 -; CHECK-NEXT: export prim v1, off, off, off done +; CHECK-NEXT: export prim, v1, off, off, off done ; CHECK-NEXT: s_endpgm %pair = call { i64, i32 } @llvm.amdgcn.ds.bvh.stack.push8.pop2.rtn(i32 %addr, i32 %data0, <8 x i32> %data1, i32 1) %vdst = extractvalue { i64, i32 } %pair, 0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll index 2ec907ed1a8b..67b20e88c041 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.compr.ll @@ -9,8 +9,8 @@ declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, declare void @llvm.amdgcn.exp.compr.v2i16(i32, i32, <2 x i16>, <2 x i16>, i1, i1) #0 ; GCN-LABEL: {{^}}test_export_compr_zeroes_v2f16: -; GCN: exp mrt0 off, off, off, off compr{{$}} -; GCN: exp mrt0 off, off, off, off done compr{{$}} +; GCN: exp mrt0, off, off, off, off compr{{$}} +; GCN: exp mrt0, off, off, off, off done compr{{$}} define amdgpu_kernel void @test_export_compr_zeroes_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> zeroinitializer, <2 x half> zeroinitializer, i1 false, i1 false) call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 0, <2 x half> zeroinitializer, <2 x half> zeroinitializer, i1 true, i1 false) @@ -20,7 +20,7 @@ define amdgpu_kernel void @test_export_compr_zeroes_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_src0_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrt0 [[SRC0]], [[SRC0]], off, off done compr{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], off, off done compr{{$}} define amdgpu_kernel void @test_export_compr_en_src0_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 3, <2 x half> , <2 x half> , i1 true, i1 false) ret void @@ -29,7 +29,7 @@ define amdgpu_kernel void @test_export_compr_en_src0_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_src1_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrt0 off, off, [[SRC1]], [[SRC1]] done compr{{$}} +; GCN: exp mrt0, off, off, [[SRC1]], [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_en_src1_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 12, <2 x half> , <2 x half> , i1 true, i1 false) ret void @@ -38,7 +38,7 @@ define amdgpu_kernel void @test_export_compr_en_src1_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_src0_src1_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_en_src0_src1_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> , <2 x half> , i1 true, i1 false) ret void @@ -47,7 +47,7 @@ define amdgpu_kernel void @test_export_compr_en_src0_src1_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_invalid2_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrt0 off, [[SRC0]], off, off done compr{{$}} +; GCN: exp mrt0, off, [[SRC0]], off, off done compr{{$}} define amdgpu_kernel void @test_export_compr_en_invalid2_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 2, <2 x half> , <2 x half> , i1 true, i1 false) ret void @@ -56,7 +56,7 @@ define amdgpu_kernel void @test_export_compr_en_invalid2_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_invalid10_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrt0 off, [[SRC0]], off, [[SRC1]] done compr{{$}} +; GCN: exp mrt0, off, [[SRC0]], off, [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_en_invalid10_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 10, <2 x half> , <2 x half> , i1 true, i1 false) ret void @@ -64,8 +64,8 @@ define amdgpu_kernel void @test_export_compr_en_invalid10_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_mrt7_v2f16: ; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 0x38003800 -; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] compr{{$}} -; GCN: exp mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done compr{{$}} +; GCN: exp mrt7, [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] compr{{$}} +; GCN: exp mrt7, [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done compr{{$}} define amdgpu_kernel void @test_export_compr_mrt7_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 7, i32 15, <2 x half> , <2 x half> , i1 false, i1 false) call void @llvm.amdgcn.exp.compr.v2f16(i32 7, i32 15, <2 x half> , <2 x half> , i1 true, i1 false) @@ -75,8 +75,8 @@ define amdgpu_kernel void @test_export_compr_mrt7_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_z_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}} -; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} +; GCN: exp mrtz, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}} +; GCN: exp mrtz, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_z_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 8, i32 15, <2 x half> , <2 x half> , i1 false, i1 false) call void @llvm.amdgcn.exp.compr.v2f16(i32 8, i32 15, <2 x half> , <2 x half> , i1 true, i1 false) @@ -86,8 +86,8 @@ define amdgpu_kernel void @test_export_compr_z_v2f16() #0 { ; GCN-LABEL: {{^}}test_export_compr_vm_v2f16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x40003c00 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x44003800 -; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr vm{{$}} -; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr vm{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr vm{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr vm{{$}} define amdgpu_kernel void @test_export_compr_vm_v2f16() #0 { call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> , <2 x half> , i1 false, i1 true) call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> , <2 x half> , i1 true, i1 true) @@ -95,8 +95,8 @@ define amdgpu_kernel void @test_export_compr_vm_v2f16() #0 { } ; GCN-LABEL: {{^}}test_export_compr_zeroes_v2i16: -; GCN: exp mrt0 off, off, off, off compr{{$}} -; GCN: exp mrt0 off, off, off, off done compr{{$}} +; GCN: exp mrt0, off, off, off, off compr{{$}} +; GCN: exp mrt0, off, off, off, off done compr{{$}} define amdgpu_kernel void @test_export_compr_zeroes_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 0, <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i1 false, i1 false) call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 0, <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i1 true, i1 false) @@ -106,7 +106,7 @@ define amdgpu_kernel void @test_export_compr_zeroes_v2i16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_src0_v2i16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005 -; GCN: exp mrt0 [[SRC0]], off, off, off done compr{{$}} +; GCN: exp mrt0, [[SRC0]], off, off, off done compr{{$}} define amdgpu_kernel void @test_export_compr_en_src0_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 1, <2 x i16> , <2 x i16> , i1 true, i1 false) ret void @@ -115,7 +115,7 @@ define amdgpu_kernel void @test_export_compr_en_src0_v2i16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_src1_v2i16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005 -; GCN: exp mrt0 off, off, [[SRC1]], [[SRC1]] done compr{{$}} +; GCN: exp mrt0, off, off, [[SRC1]], [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_en_src1_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 12, <2 x i16> , <2 x i16> , i1 true, i1 false) ret void @@ -124,7 +124,7 @@ define amdgpu_kernel void @test_export_compr_en_src1_v2i16() #0 { ; GCN-LABEL: {{^}}test_export_compr_en_src0_src1_v2i16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005 -; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_en_src0_src1_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> , <2 x i16> , i1 true, i1 false) ret void @@ -132,8 +132,8 @@ define amdgpu_kernel void @test_export_compr_en_src0_src1_v2i16() #0 { ; GCN-LABEL: {{^}}test_export_compr_mrt7_v2i16: ; GCN-DAG: v_mov_b32_e32 [[VI16:v[0-9]+]], 0x50005 -; GCN: exp mrt7 [[VI16]], [[VI16]], [[VI16]], [[VI16]] compr{{$}} -; GCN: exp mrt7 [[VI16]], [[VI16]], [[VI16]], [[VI16]] done compr{{$}} +; GCN: exp mrt7, [[VI16]], [[VI16]], [[VI16]], [[VI16]] compr{{$}} +; GCN: exp mrt7, [[VI16]], [[VI16]], [[VI16]], [[VI16]] done compr{{$}} define amdgpu_kernel void @test_export_compr_mrt7_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 7, i32 15, <2 x i16> , <2 x i16> , i1 false, i1 false) call void @llvm.amdgcn.exp.compr.v2i16(i32 7, i32 15, <2 x i16> , <2 x i16> , i1 true, i1 false) @@ -143,8 +143,8 @@ define amdgpu_kernel void @test_export_compr_mrt7_v2i16() #0 { ; GCN-LABEL: {{^}}test_export_compr_z_v2i16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005 -; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}} -; GCN: exp mrtz [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} +; GCN: exp mrtz, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr{{$}} +; GCN: exp mrtz, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr{{$}} define amdgpu_kernel void @test_export_compr_z_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 8, i32 15, <2 x i16> , <2 x i16> , i1 false, i1 false) call void @llvm.amdgcn.exp.compr.v2i16(i32 8, i32 15, <2 x i16> , <2 x i16> , i1 true, i1 false) @@ -154,8 +154,8 @@ define amdgpu_kernel void @test_export_compr_z_v2i16() #0 { ; GCN-LABEL: {{^}}test_export_compr_vm_v2i16: ; GCN-DAG: v_mov_b32_e32 [[SRC0:v[0-9]+]], 0x20001 ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 0x40005 -; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr vm{{$}} -; GCN: exp mrt0 [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr vm{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] compr vm{{$}} +; GCN: exp mrt0, [[SRC0]], [[SRC0]], [[SRC1]], [[SRC1]] done compr vm{{$}} define amdgpu_kernel void @test_export_compr_vm_v2i16() #0 { call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> , <2 x i16> , i1 false, i1 true) call void @llvm.amdgcn.exp.compr.v2i16(i32 0, i32 15, <2 x i16> , <2 x i16> , i1 true, i1 true) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll index f921ad30e497..d2a29a94f5d0 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.ll @@ -8,8 +8,8 @@ declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1 declare float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8), i32, i32, i32) #2 ; GCN-LABEL: {{^}}test_export_zeroes_f32: -; GCN: {{exp|export}} mrt0 off, off, off, off{{$}} -; GCN: {{exp|export}} mrt0 off, off, off, off done{{$}} +; GCN: {{exp|export}} mrt0, off, off, off, off{{$}} +; GCN: {{exp|export}} mrt0, off, off, off, off done{{$}} define amdgpu_kernel void @test_export_zeroes_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0, i1 false, i1 false) @@ -24,7 +24,7 @@ define amdgpu_kernel void @test_export_zeroes_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, off done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, off, off done{{$}} define amdgpu_kernel void @test_export_en_src0_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 1, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -35,7 +35,7 @@ define amdgpu_kernel void @test_export_en_src0_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 off, [[SRC1]], off, off done{{$}} +; GCN: {{exp|export}} mrt0, off, [[SRC1]], off, off done{{$}} define amdgpu_kernel void @test_export_en_src1_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -46,7 +46,7 @@ define amdgpu_kernel void @test_export_en_src1_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 off, off, [[SRC2]], off done{{$}} +; GCN: {{exp|export}} mrt0, off, off, [[SRC2]], off done{{$}} define amdgpu_kernel void @test_export_en_src2_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 4, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -57,7 +57,7 @@ define amdgpu_kernel void @test_export_en_src2_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 off, off, off, [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrt0, off, off, off, [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_en_src3_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 8, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -68,7 +68,7 @@ define amdgpu_kernel void @test_export_en_src3_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], off, off done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], off, off done{{$}} define amdgpu_kernel void @test_export_en_src0_src1_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 3, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -79,7 +79,7 @@ define amdgpu_kernel void @test_export_en_src0_src1_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 [[SRC0]], off, [[SRC2]], off done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, [[SRC2]], off done{{$}} define amdgpu_kernel void @test_export_en_src0_src2_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 5, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -90,8 +90,8 @@ define amdgpu_kernel void @test_export_en_src0_src2_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]]{{$}} -; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, off, [[SRC3]]{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, off, [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_en_src0_src3_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 9, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 0, i32 9, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -103,8 +103,8 @@ define amdgpu_kernel void @test_export_en_src0_src3_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_en_src0_src1_src2_src3_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -113,8 +113,8 @@ define amdgpu_kernel void @test_export_en_src0_src1_src2_src3_f32() #0 { ; GCN-LABEL: {{^}}test_export_mrt7_f32: ; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 0.5 -; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}} -; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}} +; GCN: {{exp|export}} mrt7, [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}} +; GCN: {{exp|export}} mrt7, [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}} define amdgpu_kernel void @test_export_mrt7_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 7, i32 15, float 0.5, float 0.5, float 0.5, float 0.5, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 7, i32 15, float 0.5, float 0.5, float 0.5, float 0.5, i1 true, i1 false) @@ -126,8 +126,8 @@ define amdgpu_kernel void @test_export_mrt7_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrtz, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} mrtz, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_z_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 8, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 8, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -139,8 +139,8 @@ define amdgpu_kernel void @test_export_z_f32() #0 { ; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} null, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; PREGFX11: {{exp|export}} null, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_null_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 9, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 9, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -152,8 +152,8 @@ define amdgpu_kernel void @test_export_null_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} invalid_target_10, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} invalid_target_10, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_reserved10_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 10, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 10, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -165,8 +165,8 @@ define amdgpu_kernel void @test_export_reserved10_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} invalid_target_11, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} invalid_target_11, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_reserved11_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 11, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 11, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -178,8 +178,8 @@ define amdgpu_kernel void @test_export_reserved11_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} pos0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} pos0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_pos0_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -191,8 +191,8 @@ define amdgpu_kernel void @test_export_pos0_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} pos3, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} pos3, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_pos3_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 15, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 15, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -204,8 +204,8 @@ define amdgpu_kernel void @test_export_pos3_f32() #0 { ; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} param0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; PREGFX11: {{exp|export}} param0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_param0_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -217,8 +217,8 @@ define amdgpu_kernel void @test_export_param0_f32() #0 { ; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} param31, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; PREGFX11: {{exp|export}} param31, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_param31_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 63, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 false) call void @llvm.amdgcn.exp.f32(i32 63, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) @@ -230,10 +230,10 @@ define amdgpu_kernel void @test_export_param31_f32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2.0 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 0.5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4.0 -; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}} -; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}} -; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}} +; PREGFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}} +; GFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_vm_f32() #0 { call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 false, i1 true) call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 true) @@ -255,8 +255,8 @@ define amdgpu_kernel void @test_export_vm_f32() #0 { ; GCN-LABEL: {{^}}test_export_zeroes_i32: -; GCN: {{exp|export}} mrt0 off, off, off, off{{$}} -; GCN: {{exp|export}} mrt0 off, off, off, off done{{$}} +; GCN: {{exp|export}} mrt0, off, off, off, off{{$}} +; GCN: {{exp|export}} mrt0, off, off, off, off done{{$}} define amdgpu_kernel void @test_export_zeroes_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i1 false, i1 false) @@ -271,7 +271,7 @@ define amdgpu_kernel void @test_export_zeroes_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, off done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, off, off done{{$}} define amdgpu_kernel void @test_export_en_src0_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 1, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) ret void @@ -282,7 +282,7 @@ define amdgpu_kernel void @test_export_en_src0_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 off, [[SRC1]], off, off done{{$}} +; GCN: {{exp|export}} mrt0, off, [[SRC1]], off, off done{{$}} define amdgpu_kernel void @test_export_en_src1_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 2, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) ret void @@ -293,7 +293,7 @@ define amdgpu_kernel void @test_export_en_src1_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 off, off, [[SRC2]], off done{{$}} +; GCN: {{exp|export}} mrt0, off, off, [[SRC2]], off done{{$}} define amdgpu_kernel void @test_export_en_src2_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 4, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) ret void @@ -304,7 +304,7 @@ define amdgpu_kernel void @test_export_en_src2_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 off, off, off, [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrt0, off, off, off, [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_en_src3_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 8, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) ret void @@ -315,7 +315,7 @@ define amdgpu_kernel void @test_export_en_src3_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], off, off done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], off, off done{{$}} define amdgpu_kernel void @test_export_en_src0_src1_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 3, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) ret void @@ -326,7 +326,7 @@ define amdgpu_kernel void @test_export_en_src0_src1_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 [[SRC0]], off, [[SRC2]], off done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, [[SRC2]], off done{{$}} define amdgpu_kernel void @test_export_en_src0_src2_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 5, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) ret void @@ -337,8 +337,8 @@ define amdgpu_kernel void @test_export_en_src0_src2_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]]{{$}} -; GCN: {{exp|export}} mrt0 [[SRC0]], off, off, [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, off, [[SRC3]]{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], off, off, [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_en_src0_src3_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 9, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 0, i32 9, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -350,8 +350,8 @@ define amdgpu_kernel void @test_export_en_src0_src3_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_en_src0_src1_src2_src3_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -360,8 +360,8 @@ define amdgpu_kernel void @test_export_en_src0_src1_src2_src3_i32() #0 { ; GCN-LABEL: {{^}}test_export_mrt7_i32: ; GCN-DAG: v_mov_b32_e32 [[VHALF:v[0-9]+]], 5 -; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}} -; GCN: {{exp|export}} mrt7 [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}} +; GCN: {{exp|export}} mrt7, [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]]{{$}} +; GCN: {{exp|export}} mrt7, [[VHALF]], [[VHALF]], [[VHALF]], [[VHALF]] done{{$}} define amdgpu_kernel void @test_export_mrt7_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 7, i32 15, i32 5, i32 5, i32 5, i32 5, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 7, i32 15, i32 5, i32 5, i32 5, i32 5, i1 true, i1 false) @@ -373,8 +373,8 @@ define amdgpu_kernel void @test_export_mrt7_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} mrtz [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} mrtz, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} mrtz, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_z_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 8, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 8, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -386,8 +386,8 @@ define amdgpu_kernel void @test_export_z_i32() #0 { ; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; PREGFX11: {{exp|export}} null [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} null, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; PREGFX11: {{exp|export}} null, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_null_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 9, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 9, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -399,8 +399,8 @@ define amdgpu_kernel void @test_export_null_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} invalid_target_10 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} invalid_target_10, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} invalid_target_10, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_reserved10_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 10, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 10, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -412,8 +412,8 @@ define amdgpu_kernel void @test_export_reserved10_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} invalid_target_11 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} invalid_target_11, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} invalid_target_11, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_reserved11_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 11, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 11, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -425,8 +425,8 @@ define amdgpu_kernel void @test_export_reserved11_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} pos0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} pos0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} pos0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_pos0_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 12, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 12, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -438,8 +438,8 @@ define amdgpu_kernel void @test_export_pos0_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GCN: {{exp|export}} pos3 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; GCN: {{exp|export}} pos3, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GCN: {{exp|export}} pos3, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_pos3_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 15, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 15, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -451,8 +451,8 @@ define amdgpu_kernel void @test_export_pos3_i32() #0 { ; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; PREGFX11: {{exp|export}} param0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} param0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; PREGFX11: {{exp|export}} param0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_param0_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 32, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 32, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -464,8 +464,8 @@ define amdgpu_kernel void @test_export_param0_i32() #0 { ; PREGFX11-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; PREGFX11-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; PREGFX11: {{exp|export}} param31 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} param31, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; PREGFX11: {{exp|export}} param31, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_param31_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 63, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 false) call void @llvm.amdgcn.exp.i32(i32 63, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 false) @@ -477,10 +477,10 @@ define amdgpu_kernel void @test_export_param31_i32() #0 { ; GCN-DAG: v_mov_b32_e32 [[SRC1:v[0-9]+]], 2 ; GCN-DAG: v_mov_b32_e32 [[SRC2:v[0-9]+]], 5 ; GCN-DAG: v_mov_b32_e32 [[SRC3:v[0-9]+]], 4 -; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}} -; PREGFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}} -; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} -; GFX11: {{exp|export}} mrt0 [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} +; PREGFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] vm{{$}} +; PREGFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done vm{{$}} +; GFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]]{{$}} +; GFX11: {{exp|export}} mrt0, [[SRC0]], [[SRC1]], [[SRC2]], [[SRC3]] done{{$}} define amdgpu_kernel void @test_export_vm_i32() #0 { call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 false, i1 true) call void @llvm.amdgcn.exp.i32(i32 0, i32 15, i32 1, i32 2, i32 5, i32 4, i1 true, i1 true) @@ -555,15 +555,15 @@ end: ; GFX8-DAG: v_mov_b32_e32 [[Y:v[0-9]+]], s0 ; GFX8-DAG: v_add_f32_e{{32|64}} [[Z0:v[0-9]+]] ; GFX8-DAG: v_sub_f32_e{{32|64}} [[Z1:v[0-9]+]] -; GFX8: {{exp|export}} param0 [[Y]], [[X]], [[Z0]], [[W0]]{{$}} -; GFX8-NEXT: {{exp|export}} param1 [[Y]], [[X]], [[Z1]], [[W1]] done{{$}} +; GFX8: {{exp|export}} param0, [[Y]], [[X]], [[Z0]], [[W0]]{{$}} +; GFX8-NEXT: {{exp|export}} param1, [[Y]], [[X]], [[Z1]], [[W1]] done{{$}} ; GFX10-DAG: v_mov_b32_e32 [[X:v[0-9]+]], s0 ; GFX10-DAG: v_mov_b32_e32 [[Y:v[0-9]+]], s1 ; GFX10-DAG: v_add_f32_e{{32|64}} [[Z0:v[0-9]+]] ; GFX10-DAG: v_sub_f32_e{{32|64}} [[Z1:v[0-9]+]] -; GFX10: {{exp|export}} param0 [[X]], [[Y]], [[Z0]], [[W0]]{{$}} -; GFX10-NEXT: {{exp|export}} param1 [[X]], [[Y]], [[Z1]], [[W1]] done{{$}} +; GFX10: {{exp|export}} param0, [[X]], [[Y]], [[Z0]], [[W0]]{{$}} +; GFX10-NEXT: {{exp|export}} param1, [[X]], [[Y]], [[Z1]], [[W1]] done{{$}} define amdgpu_kernel void @test_export_clustering(float %x, float %y) #0 { %z0 = fadd float %x, %y call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %x, float %y, float %z0, float 0.0, i1 false, i1 false) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll index a08dca816afc..ff8cadea80e2 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.prim.ll @@ -6,8 +6,8 @@ declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1 ; GCN-LABEL: {{^}}test_export_prim_i32: -; NOPRIM: exp invalid_target_20 v0, off, off, off done{{$}} -; PRIM: {{exp|export}} prim v0, off, off, off done{{$}} +; NOPRIM: exp invalid_target_20, v0, off, off, off done{{$}} +; PRIM: {{exp|export}} prim, v0, off, off, off done{{$}} define amdgpu_gs void @test_export_prim_i32(i32 inreg %a) #0 { call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 poison, i32 poison, i32 poison, i1 true, i1 false) ret void diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll index af73475e14a8..0451f7de5bf7 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.exp.row.ll @@ -12,15 +12,15 @@ define amdgpu_kernel void @undef_i32() #0 { ; GFX11-LABEL: undef_i32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_mov_b32 m0, 0 -; GFX11-NEXT: exp pos0 off, off, off, off row_en -; GFX11-NEXT: exp pos1 off, off, off, off done row_en +; GFX11-NEXT: exp pos0, off, off, off, off row_en +; GFX11-NEXT: exp pos1, off, off, off, off done row_en ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: undef_i32: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_mov_b32 m0, 0 -; GFX12-NEXT: export pos0 off, off, off, off row_en -; GFX12-NEXT: export pos1 off, off, off, off done row_en +; GFX12-NEXT: export pos0, off, off, off, off row_en +; GFX12-NEXT: export pos1, off, off, off, off done row_en ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.exp.row.i32(i32 12, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 false, i32 0) call void @llvm.amdgcn.exp.row.i32(i32 13, i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i1 true, i32 0) @@ -31,15 +31,15 @@ define amdgpu_kernel void @undef_f32() #0 { ; GFX11-LABEL: undef_f32: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_mov_b32 m0, 0 -; GFX11-NEXT: exp pos0 off, off, off, off row_en -; GFX11-NEXT: exp pos1 off, off, off, off done row_en +; GFX11-NEXT: exp pos0, off, off, off, off row_en +; GFX11-NEXT: exp pos1, off, off, off, off done row_en ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: undef_f32: ; GFX12: ; %bb.0: ; GFX12-NEXT: s_mov_b32 m0, 0 -; GFX12-NEXT: export pos0 off, off, off, off row_en -; GFX12-NEXT: export pos1 off, off, off, off done row_en +; GFX12-NEXT: export pos0, off, off, off, off row_en +; GFX12-NEXT: export pos1, off, off, off, off done row_en ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.exp.row.f32(i32 12, i32 0, float poison, float poison, float poison, float poison, i1 false, i32 0) call void @llvm.amdgcn.exp.row.f32(i32 13, i32 0, float poison, float poison, float poison, float poison, i1 true, i32 0) @@ -51,16 +51,16 @@ define amdgpu_kernel void @zero_i32() #0 { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-NEXT: s_mov_b32 m0, 0 -; GFX11-NEXT: exp pos0 v0, v0, v0, off row_en -; GFX11-NEXT: exp pos1 v0, v0, v0, off done row_en +; GFX11-NEXT: exp pos0, v0, v0, v0, off row_en +; GFX11-NEXT: exp pos1, v0, v0, v0, off done row_en ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: zero_i32: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-NEXT: s_mov_b32 m0, 0 -; GFX12-NEXT: export pos0 v0, v0, v0, off row_en -; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en +; GFX12-NEXT: export pos0, v0, v0, v0, off row_en +; GFX12-NEXT: export pos1, v0, v0, v0, off done row_en ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.exp.row.i32(i32 12, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 false, i32 0) call void @llvm.amdgcn.exp.row.i32(i32 13, i32 7, i32 0, i32 0, i32 0, i32 poison, i1 true, i32 0) @@ -72,16 +72,16 @@ define amdgpu_kernel void @one_f32() #0 { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX11-NEXT: s_mov_b32 m0, 0 -; GFX11-NEXT: exp pos0 v0, v0, v0, off row_en -; GFX11-NEXT: exp pos1 v0, v0, v0, off done row_en +; GFX11-NEXT: exp pos0, v0, v0, v0, off row_en +; GFX11-NEXT: exp pos1, v0, v0, v0, off done row_en ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: one_f32: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 1.0 ; GFX12-NEXT: s_mov_b32 m0, 0 -; GFX12-NEXT: export pos0 v0, v0, v0, off row_en -; GFX12-NEXT: export pos1 v0, v0, v0, off done row_en +; GFX12-NEXT: export pos0, v0, v0, v0, off row_en +; GFX12-NEXT: export pos1, v0, v0, v0, off done row_en ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.exp.row.f32(i32 12, i32 7, float 1.0, float 1.0, float 1.0, float poison, i1 false, i32 0) call void @llvm.amdgcn.exp.row.f32(i32 13, i32 7, float 1.0, float 1.0, float 1.0, float poison, i1 true, i32 0) @@ -93,14 +93,14 @@ define amdgpu_kernel void @id_i32() #0 { ; GFX11: ; %bb.0: ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX11-NEXT: s_mov_b32 m0, 0 -; GFX11-NEXT: exp pos0 v0, off, off, off done row_en +; GFX11-NEXT: exp pos0, v0, off, off, off done row_en ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: id_i32: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX12-NEXT: s_mov_b32 m0, 0 -; GFX12-NEXT: export pos0 v0, off, off, off done row_en +; GFX12-NEXT: export pos0, v0, off, off, off done row_en ; GFX12-NEXT: s_endpgm %id = call i32 @llvm.amdgcn.workitem.id.x() call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 0) @@ -114,7 +114,7 @@ define amdgpu_kernel void @id_arg_i32(i32 %row) #0 { ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_mov_b32 m0, s0 -; GFX11-NEXT: exp pos0 v0, off, off, off done row_en +; GFX11-NEXT: exp pos0, v0, off, off, off done row_en ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: id_arg_i32: @@ -123,7 +123,7 @@ define amdgpu_kernel void @id_arg_i32(i32 %row) #0 { ; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: s_mov_b32 m0, s0 -; GFX12-NEXT: export pos0 v0, off, off, off done row_en +; GFX12-NEXT: export pos0, v0, off, off, off done row_en ; GFX12-NEXT: s_endpgm %id = call i32 @llvm.amdgcn.workitem.id.x() call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 %id, i32 poison, i32 poison, i32 poison, i1 true, i32 %row) @@ -132,43 +132,25 @@ define amdgpu_kernel void @id_arg_i32(i32 %row) #0 { ; Divergent row number just causes a readfirstlane for now. define amdgpu_kernel void @id_row_i32() #0 { -; GFX11-SDAG-LABEL: id_row_i32: -; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-SDAG-NEXT: v_readfirstlane_b32 s0, v0 -; GFX11-SDAG-NEXT: v_mov_b32_e32 v0, 0x63 -; GFX11-SDAG-NEXT: s_mov_b32 m0, s0 -; GFX11-SDAG-NEXT: exp pos0 v0, off, off, off done row_en -; GFX11-SDAG-NEXT: s_endpgm +; GFX11-LABEL: id_row_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0x63 +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: exp pos0, v0, off, off, off done row_en +; GFX11-NEXT: s_endpgm ; -; GFX11-GISEL-LABEL: id_row_i32: -; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0x63 -; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-GISEL-NEXT: v_readfirstlane_b32 m0, v0 -; GFX11-GISEL-NEXT: exp pos0 v1, off, off, off done row_en -; GFX11-GISEL-NEXT: s_endpgm -; -; GFX12-SDAG-LABEL: id_row_i32: -; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-SDAG-NEXT: v_readfirstlane_b32 s0, v0 -; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0x63 -; GFX12-SDAG-NEXT: s_mov_b32 m0, s0 -; GFX12-SDAG-NEXT: export pos0 v0, off, off, off done row_en -; GFX12-SDAG-NEXT: s_endpgm -; -; GFX12-GISEL-LABEL: id_row_i32: -; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0x63 -; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX12-GISEL-NEXT: v_readfirstlane_b32 m0, v0 -; GFX12-GISEL-NEXT: export pos0 v1, off, off, off done row_en -; GFX12-GISEL-NEXT: s_endpgm +; GFX12-LABEL: id_row_i32: +; GFX12: ; %bb.0: +; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX12-NEXT: v_readfirstlane_b32 s0, v0 +; GFX12-NEXT: v_mov_b32_e32 v0, 0x63 +; GFX12-NEXT: s_mov_b32 m0, s0 +; GFX12-NEXT: export pos0, v0, off, off, off done row_en +; GFX12-NEXT: s_endpgm %id = call i32 @llvm.amdgcn.workitem.id.x() call void @llvm.amdgcn.exp.row.i32(i32 12, i32 1, i32 99, i32 poison, i32 poison, i32 poison, i1 true, i32 %id) ret void diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll index d9226df0010f..ad7d37b6719f 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll @@ -21,7 +21,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m ; GFX11-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7 -; GFX11-NEXT: exp mrt0 v3, v2, v5, v4 done +; GFX11-NEXT: exp mrt0, v3, v2, v5, v4 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: v_interp_f32: @@ -40,7 +40,7 @@ define amdgpu_ps void @v_interp_f32(float inreg %i, float inreg %j, i32 inreg %m ; GFX12-NEXT: v_interp_p2_f32 v5, v0, v4, v3 wait_exp:7 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_interp_p2_f32 v4, v1, v4, v5 wait_exp:7 -; GFX12-NEXT: export mrt0 v3, v2, v5, v4 done +; GFX12-NEXT: export mrt0, v3, v2, v5, v4 done ; GFX12-NEXT: s_endpgm main_body: %p0 = call float @llvm.amdgcn.lds.param.load(i32 1, i32 0, i32 %m0) @@ -76,7 +76,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr ; GFX11-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX11-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7 -; GFX11-NEXT: exp mrt0 v6, v7, v8, v4 done +; GFX11-NEXT: exp mrt0, v6, v7, v8, v4 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: v_interp_f32_many: @@ -101,7 +101,7 @@ define amdgpu_ps void @v_interp_f32_many(float inreg %i, float inreg %j, i32 inr ; GFX12-NEXT: v_interp_p2_f32 v8, v2, v5, v8 wait_exp:7 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-NEXT: v_interp_p2_f32 v4, v3, v5, v4 wait_exp:7 -; GFX12-NEXT: export mrt0 v6, v7, v8, v4 done +; GFX12-NEXT: export mrt0, v6, v7, v8, v4 done ; GFX12-NEXT: s_endpgm main_body: %p0 = call float @llvm.amdgcn.lds.param.load(i32 0, i32 0, i32 %m0) @@ -143,7 +143,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7 ; GFX11-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7 -; GFX11-NEXT: exp mrt0 v6, v7, v8, v0 done +; GFX11-NEXT: exp mrt0, v6, v7, v8, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: v_interp_f32_many_vm: @@ -168,7 +168,7 @@ define amdgpu_ps void @v_interp_f32_many_vm(ptr addrspace(1) %ptr, i32 inreg %m0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-NEXT: v_interp_p2_f32 v8, v4, v1, v8 wait_exp:7 ; GFX12-NEXT: v_interp_p2_f32 v0, v5, v1, v0 wait_exp:7 -; GFX12-NEXT: export mrt0 v6, v7, v8, v0 done +; GFX12-NEXT: export mrt0, v6, v7, v8, v0 done ; GFX12-NEXT: s_endpgm main_body: %i.ptr = getelementptr float, ptr addrspace(1) %ptr, i32 1 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll index d37a6c931989..af81d9597345 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kill.ll @@ -63,14 +63,14 @@ define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) { ; SI-NEXT: ; %bb.1: ; SI-NEXT: s_andn2_b64 exec, exec, vcc ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1] -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_mov_b32 m0, 0 ; SI-NEXT: s_nop 0 ; SI-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB1_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-LABEL: vcc_implicit_def: @@ -84,11 +84,11 @@ define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) { ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1] ; GFX10-NEXT: s_mov_b32 m0, 0 ; GFX10-NEXT: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) -; GFX10-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB1_2: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: vcc_implicit_def: @@ -102,11 +102,11 @@ define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) { ; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, s[0:1] ; GFX11-NEXT: s_mov_b32 m0, 0 ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: exp mrt1 v0, v0, v0, v0 done +; GFX11-NEXT: exp mrt1, v0, v0, v0, v0 done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB1_2: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: vcc_implicit_def: @@ -122,11 +122,11 @@ define amdgpu_ps void @vcc_implicit_def(float %arg13, float %arg14) { ; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc ; GFX12-NEXT: s_mov_b32 m0, 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX12-NEXT: export mrt1 v0, v0, v0, v0 done +; GFX12-NEXT: export mrt1, v0, v0, v0, v0 done ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB1_2: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm %tmp0 = fcmp olt float %arg13, 0.000000e+00 %c1 = fcmp oge float %arg14, 0.0 @@ -1164,7 +1164,7 @@ define amdgpu_ps void @fcmp_x2(float %a) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB21_1: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-LABEL: fcmp_x2: @@ -1177,7 +1177,7 @@ define amdgpu_ps void @fcmp_x2(float %a) #0 { ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB21_1: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: fcmp_x2: @@ -1191,7 +1191,7 @@ define amdgpu_ps void @fcmp_x2(float %a) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB21_1: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: fcmp_x2: @@ -1205,7 +1205,7 @@ define amdgpu_ps void @fcmp_x2(float %a) #0 { ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB21_1: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm %ogt = fcmp nsz ogt float %a, 2.500000e-01 %k = select i1 %ogt, float -1.000000e+00, float 0.000000e+00 @@ -1230,7 +1230,7 @@ define amdgpu_ps float @wqm(float %a) { ; SI-NEXT: s_branch .LBB22_3 ; SI-NEXT: .LBB22_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB22_3: ; @@ -1248,7 +1248,7 @@ define amdgpu_ps float @wqm(float %a) { ; GFX10-NEXT: s_branch .LBB22_3 ; GFX10-NEXT: .LBB22_2: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB22_3: ; @@ -1266,7 +1266,7 @@ define amdgpu_ps float @wqm(float %a) { ; GFX11-NEXT: s_branch .LBB22_3 ; GFX11-NEXT: .LBB22_2: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB22_3: ; @@ -1284,7 +1284,7 @@ define amdgpu_ps float @wqm(float %a) { ; GFX12-NEXT: s_branch .LBB22_3 ; GFX12-NEXT: .LBB22_2: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB22_3: %c1 = fcmp une float %a, 0.0 @@ -1303,7 +1303,7 @@ define amdgpu_ps void @test_sgpr(float inreg %a) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB23_1: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-LABEL: test_sgpr: @@ -1314,7 +1314,7 @@ define amdgpu_ps void @test_sgpr(float inreg %a) #0 { ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB23_1: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: test_sgpr: @@ -1325,7 +1325,7 @@ define amdgpu_ps void @test_sgpr(float inreg %a) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB23_1: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: test_sgpr: @@ -1338,7 +1338,7 @@ define amdgpu_ps void @test_sgpr(float inreg %a) #0 { ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB23_1: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm %c = fcmp ole float %a, 1.000000e+00 call void @llvm.amdgcn.kill(i1 %c) #1 @@ -1356,7 +1356,7 @@ define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB24_1: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-LABEL: test_non_inline_imm_sgpr: @@ -1368,7 +1368,7 @@ define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB24_1: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: test_non_inline_imm_sgpr: @@ -1380,7 +1380,7 @@ define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB24_1: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: test_non_inline_imm_sgpr: @@ -1393,7 +1393,7 @@ define amdgpu_ps void @test_non_inline_imm_sgpr(float inreg %a) #0 { ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB24_1: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm %c = fcmp ole float %a, 1.500000e+00 call void @llvm.amdgcn.kill(i1 %c) #1 @@ -1423,7 +1423,7 @@ define amdgpu_ps void @test_scc_liveness() #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB25_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-LABEL: test_scc_liveness: @@ -1448,7 +1448,7 @@ define amdgpu_ps void @test_scc_liveness() #0 { ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB25_4: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: test_scc_liveness: @@ -1473,7 +1473,7 @@ define amdgpu_ps void @test_scc_liveness() #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB25_4: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: test_scc_liveness: @@ -1498,7 +1498,7 @@ define amdgpu_ps void @test_scc_liveness() #0 { ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB25_4: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm main_body: br label %loop3 @@ -1543,11 +1543,11 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, ; SI-NEXT: ; %bb.4: ; %bb33 ; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: .LBB26_5: ; %bb35 -; SI-NEXT: exp mrt0 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt0, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB26_6: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-LABEL: kill_with_loop_exit: @@ -1575,11 +1575,11 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, ; GFX10-NEXT: ; %bb.4: ; %bb33 ; GFX10-NEXT: s_mov_b64 exec, 0 ; GFX10-NEXT: .LBB26_5: ; %bb35 -; GFX10-NEXT: exp mrt0 v0, v0, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v0, v0, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; GFX10-NEXT: .LBB26_6: ; GFX10-NEXT: s_mov_b64 exec, 0 -; GFX10-NEXT: exp null off, off, off, off done vm +; GFX10-NEXT: exp null, off, off, off, off done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: kill_with_loop_exit: @@ -1608,11 +1608,11 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, ; GFX11-NEXT: ; %bb.4: ; %bb33 ; GFX11-NEXT: s_mov_b64 exec, 0 ; GFX11-NEXT: .LBB26_5: ; %bb35 -; GFX11-NEXT: exp mrt0 v0, v0, v0, v0 done +; GFX11-NEXT: exp mrt0, v0, v0, v0, v0 done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB26_6: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: kill_with_loop_exit: @@ -1644,11 +1644,11 @@ define amdgpu_ps void @kill_with_loop_exit(float inreg %inp0, float inreg %inp1, ; GFX12-NEXT: s_mov_b64 exec, 0 ; GFX12-NEXT: .LBB26_5: ; %bb35 ; GFX12-NEXT: v_mov_b32_e32 v0, s4 -; GFX12-NEXT: export mrt0 v0, v0, v0, v0 done +; GFX12-NEXT: export mrt0, v0, v0, v0, v0 done ; GFX12-NEXT: s_endpgm ; GFX12-NEXT: .LBB26_6: ; GFX12-NEXT: s_mov_b64 exec, 0 -; GFX12-NEXT: export mrt0 off, off, off, off done +; GFX12-NEXT: export mrt0, off, off, off, off done ; GFX12-NEXT: s_endpgm .entry: %tmp24 = fcmp olt float %inp0, 1.280000e+02 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll index e6a59f43ad69..8fa5aa47eec6 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll @@ -505,9 +505,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i3 ; PREGFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; PREGFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offen_merged_and: @@ -516,9 +516,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i3 ; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; GFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offen_merged_and: @@ -527,9 +527,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i3 ; GFX11-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], 0 offen offset:4 ; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done +; GFX11-NEXT: exp mrt0, v5, v6, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: buffer_load_x1_offen_merged_and: @@ -538,9 +538,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(<4 x i32> inreg %rsrc, i3 ; GFX12-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], null offen offset:4 ; GFX12-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], null offen offset:28 ; GFX12-NEXT: s_wait_loadcnt 0x1 -; GFX12-NEXT: export mrt0 v1, v2, v3, v4 done +; GFX12-NEXT: export mrt0, v1, v2, v3, v4 done ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v5, v6, v0, v0 done +; GFX12-NEXT: export mrt0, v5, v6, v0, v0 done ; GFX12-NEXT: s_endpgm main_body: %a1 = add i32 %a, 4 @@ -567,9 +567,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v4, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], v4, s[0:3], 0 offen offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offen_merged_or: @@ -579,9 +579,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v6, s[0:3], 0 offen offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], v6, s[0:3], 0 offen offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offen_merged_or: @@ -591,9 +591,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX11-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], v4, s[0:3], 0 offen offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-SDAG-LABEL: buffer_load_x1_offen_merged_or: @@ -603,9 +603,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX12-SDAG-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], null offen offset:4 ; GFX12-SDAG-NEXT: buffer_load_b64 v[4:5], v4, s[0:3], null offen offset:28 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x1 -; GFX12-SDAG-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-SDAG-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 -; GFX12-SDAG-NEXT: export mrt0 v4, v5, v0, v0 done +; GFX12-SDAG-NEXT: export mrt0, v4, v5, v0, v0 done ; GFX12-SDAG-NEXT: s_endpgm ; ; GFX12-GISEL-LABEL: buffer_load_x1_offen_merged_or: @@ -625,9 +625,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX12-GISEL-NEXT: buffer_load_b32 v5, v5, s[0:3], null offen ; GFX12-GISEL-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x2 -; GFX12-GISEL-NEXT: export mrt0 v1, v2, v3, v4 done +; GFX12-GISEL-NEXT: export mrt0, v1, v2, v3, v4 done ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 -; GFX12-GISEL-NEXT: export mrt0 v5, v0, v0, v0 done +; GFX12-GISEL-NEXT: export mrt0, v5, v0, v0, v0 done ; GFX12-GISEL-NEXT: s_endpgm main_body: %a = shl i32 %inp, 6 @@ -655,9 +655,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc ; PREGFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc ; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; PREGFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offen_merged_glc_slc: @@ -667,9 +667,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc ; GFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc ; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; GFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offen_merged_glc_slc: @@ -679,9 +679,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc ; GFX11-NEXT: buffer_load_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc ; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done +; GFX11-NEXT: exp mrt0, v5, v6, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: buffer_load_x1_offen_merged_glc_slc: @@ -691,9 +691,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(<4 x i32> inreg %rsrc ; GFX12-NEXT: buffer_load_b64 v[3:4], v0, s[0:3], null offen offset:12 th:TH_LOAD_NT ; GFX12-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], null offen offset:28 th:TH_LOAD_LU ; GFX12-NEXT: s_wait_loadcnt 0x1 -; GFX12-NEXT: export mrt0 v1, v2, v3, v4 done +; GFX12-NEXT: export mrt0, v1, v2, v3, v4 done ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v5, v6, v0, v0 done +; GFX12-NEXT: export mrt0, v5, v6, v0, v0 done ; GFX12-NEXT: s_endpgm main_body: %a1 = add i32 %a, 4 @@ -718,28 +718,28 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_and(<4 x i32> inreg %rsrc, i3 ; PREGFX10: ; %bb.0: ; %main_body ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x2_offen_merged_and: ; GFX10: ; %bb.0: ; %main_body ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x2_offen_merged_and: ; GFX11: ; %bb.0: ; %main_body ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: buffer_load_x2_offen_merged_and: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen offset:4 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_endpgm main_body: %a1 = add i32 %a, 4 @@ -760,7 +760,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; PREGFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x2_offen_merged_or: @@ -768,7 +768,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x2_offen_merged_or: @@ -776,7 +776,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: buffer_load_x2_offen_merged_or: @@ -784,7 +784,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(<4 x i32> inreg %rsrc, i32 ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX12-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], null offen offset:4 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_endpgm main_body: %a = shl i32 %inp, 4 @@ -806,9 +806,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offset_merged: @@ -817,9 +817,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offset_merged: @@ -828,9 +828,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: buffer_load_x1_offset_merged: @@ -839,9 +839,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4 ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null offset:28 ; GFX12-NEXT: s_wait_loadcnt 0x1 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done +; GFX12-NEXT: export mrt0, v4, v5, v0, v0 done ; GFX12-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) @@ -860,28 +860,28 @@ define amdgpu_ps void @buffer_load_x2_offset_merged(<4 x i32> inreg %rsrc) { ; PREGFX10: ; %bb.0: ; %main_body ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x2_offset_merged: ; GFX10: ; %bb.0: ; %main_body ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x2_offset_merged: ; GFX11: ; %bb.0: ; %main_body ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: buffer_load_x2_offset_merged: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_endpgm main_body: %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) @@ -1263,9 +1263,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: raw_buffer_load_x1_offset_merged: @@ -1274,9 +1274,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: raw_buffer_load_x1_offset_merged: @@ -1285,9 +1285,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: raw_buffer_load_x1_offset_merged: @@ -1296,9 +1296,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_merged(<4 x i32> inreg %rsrc) { ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4 ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null offset:28 ; GFX12-NEXT: s_wait_loadcnt 0x1 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done +; GFX12-NEXT: export mrt0, v4, v5, v0, v0 done ; GFX12-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0) @@ -1322,9 +1322,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12(<4 ; PREGFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32 ; PREGFX10-NEXT: s_waitcnt vmcnt(2) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12: @@ -1337,9 +1337,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12(<4 ; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28 ; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32 ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12: @@ -1352,9 +1352,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12(<4 ; GFX11-NEXT: buffer_load_b32 v4, off, s[0:3], 0 offset:28 ; GFX11-NEXT: buffer_load_b32 v5, off, s[0:3], 0 offset:32 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12: @@ -1363,9 +1363,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged_pregfx12(<4 ; GFX12-NEXT: buffer_load_b128 v[0:3], off, s[0:3], null offset:4 scope:SCOPE_SE ; GFX12-NEXT: buffer_load_b64 v[4:5], off, s[0:3], null offset:28 scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x1 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done +; GFX12-NEXT: export mrt0, v4, v5, v0, v0 done ; GFX12-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 8) @@ -1385,9 +1385,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> i ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged: @@ -1396,9 +1396,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> i ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged: @@ -1407,9 +1407,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> i ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: raw_buffer_load_x1_offset_swizzled_not_merged: @@ -1422,9 +1422,9 @@ define amdgpu_ps void @raw_buffer_load_x1_offset_swizzled_not_merged(<4 x i32> i ; GFX12-NEXT: buffer_load_b32 v4, off, s[0:3], null offset:28 ; GFX12-NEXT: buffer_load_b32 v5, off, s[0:3], null offset:32 ; GFX12-NEXT: s_wait_loadcnt 0x2 -; GFX12-NEXT: export mrt0 v0, v1, v2, v3 done +; GFX12-NEXT: export mrt0, v0, v1, v2, v3 done ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: export mrt0 v4, v5, v0, v0 done +; GFX12-NEXT: export mrt0, v4, v5, v0, v0 done ; GFX12-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.buffer.load.f32(<4 x i32> %rsrc, i32 4, i32 0, i32 64) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll index a9799993f5cd..543b619f3074 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll @@ -440,9 +440,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(ptr addrspace(8) inreg %r ; PREGFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; PREGFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offen_merged_and: @@ -451,9 +451,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(ptr addrspace(8) inreg %r ; GFX10-NEXT: buffer_load_dwordx4 v[1:4], v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; GFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offen_merged_and: @@ -462,9 +462,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_and(ptr addrspace(8) inreg %r ; GFX11-NEXT: buffer_load_b128 v[1:4], v0, s[0:3], 0 offen offset:4 ; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done +; GFX11-NEXT: exp mrt0, v5, v6, v0, v0 done ; GFX11-NEXT: s_endpgm main_body: %a1 = add i32 %a, 4 @@ -491,9 +491,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(ptr addrspace(8) inreg %rs ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v4, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], v4, s[0:3], 0 offen offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offen_merged_or: @@ -503,9 +503,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(ptr addrspace(8) inreg %rs ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v6, s[0:3], 0 offen offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], v6, s[0:3], 0 offen offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offen_merged_or: @@ -515,9 +515,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_or(ptr addrspace(8) inreg %rs ; GFX11-NEXT: buffer_load_b128 v[0:3], v4, s[0:3], 0 offen offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], v4, s[0:3], 0 offen offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm main_body: %a = shl i32 %inp, 6 @@ -545,9 +545,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(ptr addrspace(8) inre ; PREGFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc ; PREGFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; PREGFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offen_merged_glc_slc: @@ -557,9 +557,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(ptr addrspace(8) inre ; GFX10-NEXT: buffer_load_dwordx2 v[3:4], v0, s[0:3], 0 offen offset:12 glc ; GFX10-NEXT: buffer_load_dwordx2 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v1, v2, v3, v4 done vm +; GFX10-NEXT: exp mrt0, v1, v2, v3, v4 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v5, v6, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v5, v6, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offen_merged_glc_slc: @@ -569,9 +569,9 @@ define amdgpu_ps void @buffer_load_x1_offen_merged_glc_slc(ptr addrspace(8) inre ; GFX11-NEXT: buffer_load_b64 v[3:4], v0, s[0:3], 0 offen offset:12 glc ; GFX11-NEXT: buffer_load_b64 v[5:6], v0, s[0:3], 0 offen offset:28 glc slc ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v1, v2, v3, v4 done +; GFX11-NEXT: exp mrt0, v1, v2, v3, v4 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v5, v6, v0, v0 done +; GFX11-NEXT: exp mrt0, v5, v6, v0, v0 done ; GFX11-NEXT: s_endpgm main_body: %a1 = add i32 %a, 4 @@ -596,21 +596,21 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_and(ptr addrspace(8) inreg %r ; PREGFX10: ; %bb.0: ; %main_body ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x2_offen_merged_and: ; GFX10: ; %bb.0: ; %main_body ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x2_offen_merged_and: ; GFX11: ; %bb.0: ; %main_body ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_endpgm main_body: %a1 = add i32 %a, 4 @@ -631,7 +631,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(ptr addrspace(8) inreg %rs ; PREGFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x2_offen_merged_or: @@ -639,7 +639,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(ptr addrspace(8) inreg %rs ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x2_offen_merged_or: @@ -647,7 +647,7 @@ define amdgpu_ps void @buffer_load_x2_offen_merged_or(ptr addrspace(8) inreg %rs ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX11-NEXT: buffer_load_b128 v[0:3], v0, s[0:3], 0 offen offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_endpgm main_body: %a = shl i32 %inp, 4 @@ -669,9 +669,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(ptr addrspace(8) inreg %rsrc ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x1_offset_merged: @@ -680,9 +680,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(ptr addrspace(8) inreg %rsrc ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x1_offset_merged: @@ -691,9 +691,9 @@ define amdgpu_ps void @buffer_load_x1_offset_merged(ptr addrspace(8) inreg %rsrc ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 0) @@ -712,21 +712,21 @@ define amdgpu_ps void @buffer_load_x2_offset_merged(ptr addrspace(8) inreg %rsrc ; PREGFX10: ; %bb.0: ; %main_body ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: buffer_load_x2_offset_merged: ; GFX10: ; %bb.0: ; %main_body ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: buffer_load_x2_offset_merged: ; GFX11: ; %bb.0: ; %main_body ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_endpgm main_body: %vr1 = call <2 x float> @llvm.amdgcn.raw.ptr.buffer.load.v2f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 0) @@ -1086,9 +1086,9 @@ define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_merged(ptr addrspace(8) inr ; PREGFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; PREGFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: s_waitcnt vmcnt(1) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: raw_ptr_buffer_load_x1_offset_merged: @@ -1097,9 +1097,9 @@ define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_merged(ptr addrspace(8) inr ; GFX10-NEXT: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:4 ; GFX10-NEXT: buffer_load_dwordx2 v[4:5], off, s[0:3], 0 offset:28 ; GFX10-NEXT: s_waitcnt vmcnt(1) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: raw_ptr_buffer_load_x1_offset_merged: @@ -1108,9 +1108,9 @@ define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_merged(ptr addrspace(8) inr ; GFX11-NEXT: buffer_load_b128 v[0:3], off, s[0:3], 0 offset:4 ; GFX11-NEXT: buffer_load_b64 v[4:5], off, s[0:3], 0 offset:28 ; GFX11-NEXT: s_waitcnt vmcnt(1) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 0) @@ -1134,9 +1134,9 @@ define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_swizzled_not_merged(ptr add ; PREGFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28 ; PREGFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32 ; PREGFX10-NEXT: s_waitcnt vmcnt(2) -; PREGFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; PREGFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; PREGFX10-NEXT: s_waitcnt vmcnt(0) -; PREGFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; PREGFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; PREGFX10-NEXT: s_endpgm ; ; GFX10-LABEL: raw_ptr_buffer_load_x1_offset_swizzled_not_merged: @@ -1149,9 +1149,9 @@ define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_swizzled_not_merged(ptr add ; GFX10-NEXT: buffer_load_dword v4, off, s[0:3], 0 offset:28 ; GFX10-NEXT: buffer_load_dword v5, off, s[0:3], 0 offset:32 ; GFX10-NEXT: s_waitcnt vmcnt(2) -; GFX10-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: exp mrt0 v4, v5, v0, v0 done vm +; GFX10-NEXT: exp mrt0, v4, v5, v0, v0 done vm ; GFX10-NEXT: s_endpgm ; ; GFX11-LABEL: raw_ptr_buffer_load_x1_offset_swizzled_not_merged: @@ -1164,9 +1164,9 @@ define amdgpu_ps void @raw_ptr_buffer_load_x1_offset_swizzled_not_merged(ptr add ; GFX11-NEXT: buffer_load_b32 v4, off, s[0:3], 0 offset:28 ; GFX11-NEXT: buffer_load_b32 v5, off, s[0:3], 0 offset:32 ; GFX11-NEXT: s_waitcnt vmcnt(2) -; GFX11-NEXT: exp mrt0 v0, v1, v2, v3 done +; GFX11-NEXT: exp mrt0, v0, v1, v2, v3 done ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: exp mrt0 v4, v5, v0, v0 done +; GFX11-NEXT: exp mrt0, v4, v5, v0, v0 done ; GFX11-NEXT: s_endpgm main_body: %r1 = call float @llvm.amdgcn.raw.ptr.buffer.load.f32(ptr addrspace(8) %rsrc, i32 4, i32 0, i32 8) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll index c98feeb96232..3fb6910d283e 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.demote.ll @@ -13,11 +13,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: s_mov_b64 exec, 0 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB0_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: static_exact: @@ -28,11 +28,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: s_mov_b64 exec, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB0_2: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: static_exact: @@ -43,11 +43,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB0_2: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: static_exact: @@ -58,11 +58,11 @@ define amdgpu_ps void @static_exact(float %arg0, float %arg1) { ; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: s_mov_b64 exec, 0 ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB0_2: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %c0 = fcmp olt float %arg0, 0.000000e+00 @@ -85,11 +85,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; SI-NEXT: ; %bb.1: ; %.entry ; SI-NEXT: s_and_b64 exec, exec, s[2:3] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB1_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: dynamic_exact: @@ -103,11 +103,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; GFX9-NEXT: ; %bb.1: ; %.entry ; GFX9-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB1_2: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: dynamic_exact: @@ -121,11 +121,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; GFX10-32-NEXT: ; %bb.1: ; %.entry ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB1_2: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: dynamic_exact: @@ -139,11 +139,11 @@ define amdgpu_ps void @dynamic_exact(float %arg0, float %arg1) { ; GFX10-64-NEXT: ; %bb.1: ; %.entry ; GFX10-64-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB1_2: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %c0 = fcmp olt float %arg0, 0.000000e+00 @@ -175,11 +175,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; SI-NEXT: .LBB2_3: ; %.continue ; SI-NEXT: s_or_b64 exec, exec, s[0:1] ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB2_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: branch: @@ -202,11 +202,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; GFX9-NEXT: .LBB2_3: ; %.continue ; GFX9-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB2_4: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: branch: @@ -229,11 +229,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; GFX10-32-NEXT: .LBB2_3: ; %.continue ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB2_4: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: branch: @@ -256,11 +256,11 @@ define amdgpu_ps void @branch(float %arg0, float %arg1) { ; GFX10-64-NEXT: .LBB2_3: ; %.continue ; GFX10-64-NEXT: s_or_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB2_4: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %i0 = fptosi float %arg0 to i32 @@ -307,7 +307,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; SI-NEXT: s_branch .LBB3_5 ; SI-NEXT: .LBB3_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB3_5: ; @@ -336,7 +336,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX9-NEXT: s_branch .LBB3_5 ; GFX9-NEXT: .LBB3_4: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB3_5: ; @@ -365,7 +365,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-32-NEXT: s_branch .LBB3_5 ; GFX10-32-NEXT: .LBB3_4: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB3_5: ; @@ -394,7 +394,7 @@ define amdgpu_ps <4 x float> @wqm_demote_1(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-64-NEXT: s_branch .LBB3_5 ; GFX10-64-NEXT: .LBB3_4: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB3_5: .entry: @@ -441,7 +441,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; SI-NEXT: s_branch .LBB4_5 ; SI-NEXT: .LBB4_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB4_5: ; @@ -470,7 +470,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX9-NEXT: s_branch .LBB4_5 ; GFX9-NEXT: .LBB4_4: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB4_5: ; @@ -499,7 +499,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-32-NEXT: s_branch .LBB4_5 ; GFX10-32-NEXT: .LBB4_4: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB4_5: ; @@ -528,7 +528,7 @@ define amdgpu_ps <4 x float> @wqm_demote_2(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10-64-NEXT: s_branch .LBB4_5 ; GFX10-64-NEXT: .LBB4_4: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB4_5: .entry: @@ -570,7 +570,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; SI-NEXT: s_branch .LBB5_3 ; SI-NEXT: .LBB5_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB5_3: ; @@ -594,7 +594,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; GFX9-NEXT: s_branch .LBB5_3 ; GFX9-NEXT: .LBB5_2: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB5_3: ; @@ -618,7 +618,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10-32-NEXT: s_branch .LBB5_3 ; GFX10-32-NEXT: .LBB5_2: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB5_3: ; @@ -642,7 +642,7 @@ define amdgpu_ps <4 x float> @wqm_demote_dynamic(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10-64-NEXT: s_branch .LBB5_3 ; GFX10-64-NEXT: .LBB5_2: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB5_3: .entry: @@ -700,11 +700,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: v_bfrev_b32_e32 v0, 60 ; SI-NEXT: v_mov_b32_e32 v1, 0x3c00 -; SI-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; SI-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB6_7: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: wqm_deriv: @@ -748,11 +748,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX9-NEXT: v_bfrev_b32_e32 v0, 60 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x3c00 -; GFX9-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; GFX9-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB6_7: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: wqm_deriv: @@ -794,11 +794,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; GFX10-32-NEXT: s_or_b32 exec_lo, exec_lo, s1 ; GFX10-32-NEXT: v_bfrev_b32_e32 v0, 60 ; GFX10-32-NEXT: v_mov_b32_e32 v1, 0x3c00 -; GFX10-32-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; GFX10-32-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB6_7: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: wqm_deriv: @@ -840,11 +840,11 @@ define amdgpu_ps void @wqm_deriv(<2 x float> %input, float %arg, i32 %index) { ; GFX10-64-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX10-64-NEXT: v_bfrev_b32_e32 v0, 60 ; GFX10-64-NEXT: v_mov_b32_e32 v1, 0x3c00 -; GFX10-64-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; GFX10-64-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB6_7: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %p0 = extractelement <2 x float> %input, i32 0 @@ -941,11 +941,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; SI-NEXT: s_and_b64 exec, exec, s[0:1] ; SI-NEXT: v_bfrev_b32_e32 v0, 60 ; SI-NEXT: v_mov_b32_e32 v1, 0x3c00 -; SI-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; SI-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB7_9: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: wqm_deriv_loop: @@ -1007,11 +1007,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; GFX9-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-NEXT: v_bfrev_b32_e32 v0, 60 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x3c00 -; GFX9-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; GFX9-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB7_9: ; GFX9-NEXT: s_mov_b64 exec, 0 -; GFX9-NEXT: exp null off, off, off, off done vm +; GFX9-NEXT: exp null, off, off, off, off done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: wqm_deriv_loop: @@ -1070,11 +1070,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; GFX10-32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-32-NEXT: v_bfrev_b32_e32 v0, 60 ; GFX10-32-NEXT: v_mov_b32_e32 v1, 0x3c00 -; GFX10-32-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; GFX10-32-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; GFX10-32-NEXT: s_endpgm ; GFX10-32-NEXT: .LBB7_9: ; GFX10-32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-32-NEXT: exp null off, off, off, off done vm +; GFX10-32-NEXT: exp null, off, off, off, off done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: wqm_deriv_loop: @@ -1133,11 +1133,11 @@ define amdgpu_ps void @wqm_deriv_loop(<2 x float> %input, float %arg, i32 %index ; GFX10-64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX10-64-NEXT: v_bfrev_b32_e32 v0, 60 ; GFX10-64-NEXT: v_mov_b32_e32 v1, 0x3c00 -; GFX10-64-NEXT: exp mrt0 v1, v1, v0, v0 done compr vm +; GFX10-64-NEXT: exp mrt0, v1, v1, v0, v0 done compr vm ; GFX10-64-NEXT: s_endpgm ; GFX10-64-NEXT: .LBB7_9: ; GFX10-64-NEXT: s_mov_b64 exec, 0 -; GFX10-64-NEXT: exp null off, off, off, off done vm +; GFX10-64-NEXT: exp null, off, off, off, off done vm ; GFX10-64-NEXT: s_endpgm .entry: %p0 = extractelement <2 x float> %input, i32 0 @@ -1185,28 +1185,28 @@ define amdgpu_ps void @static_exact_nop(float %arg0, float %arg1) { ; SI: ; %bb.0: ; %.entry ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; SI-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; SI-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; SI-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; SI-NEXT: s_endpgm ; ; GFX9-LABEL: static_exact_nop: ; GFX9: ; %bb.0: ; %.entry ; GFX9-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX9-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX9-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX9-NEXT: s_endpgm ; ; GFX10-32-LABEL: static_exact_nop: ; GFX10-32: ; %bb.0: ; %.entry ; GFX10-32-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0 ; GFX10-32-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo -; GFX10-32-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-32-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-32-NEXT: s_endpgm ; ; GFX10-64-LABEL: static_exact_nop: ; GFX10-64: ; %bb.0: ; %.entry ; GFX10-64-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0 ; GFX10-64-NEXT: v_cndmask_b32_e64 v0, 0, 1.0, vcc -; GFX10-64-NEXT: exp mrt1 v0, v0, v0, v0 done vm +; GFX10-64-NEXT: exp mrt1, v0, v0, v0, v0 done vm ; GFX10-64-NEXT: s_endpgm .entry: %c0 = fcmp olt float %arg0, 0.000000e+00 diff --git a/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll b/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll index c9615f478e5b..157b4fbe6803 100644 --- a/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll +++ b/llvm/test/CodeGen/AMDGPU/load-local-redundant-copies.ll @@ -16,7 +16,7 @@ define amdgpu_vs void @test(ptr addrspace(8) inreg %arg1, ptr addrspace(3) %arg2 ; CHECK-NEXT: ds_read_b32 v1, v4 ; CHECK-NEXT: ds_read_b32 v0, v0 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: exp mrt0 off, off, off, off +; CHECK-NEXT: exp mrt0, off, off, off, off ; CHECK-NEXT: v_mov_b32_e32 v4, 0 ; CHECK-NEXT: tbuffer_store_format_xyzw v[0:3], v4, s[0:3], 0 format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] idxen ; CHECK-NEXT: s_endpgm @@ -95,7 +95,7 @@ define amdgpu_vs void @test_3(i32 inreg %arg1, i32 inreg %arg2, ptr addrspace(8) ; CHECK-NEXT: ds_read_b32 v0, v9 ; CHECK-NEXT: ds_read_b32 v2, v2 ; CHECK-NEXT: s_waitcnt lgkmcnt(1) -; CHECK-NEXT: exp mrt0 off, off, off, off +; CHECK-NEXT: exp mrt0, off, off, off, off ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: tbuffer_store_format_xyzw v[2:5], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_32_32_32,BUF_NUM_FORMAT_UINT] idxen offset:240 glc slc ; CHECK-NEXT: tbuffer_store_format_xy v[0:1], v10, s[4:7], s1 format:[BUF_DATA_FORMAT_INVALID,BUF_NUM_FORMAT_UINT] idxen offset:256 glc slc diff --git a/llvm/test/CodeGen/AMDGPU/memory_clause.ll b/llvm/test/CodeGen/AMDGPU/memory_clause.ll index e6fd6aba92cf..4d3920a9459d 100644 --- a/llvm/test/CodeGen/AMDGPU/memory_clause.ll +++ b/llvm/test/CodeGen/AMDGPU/memory_clause.ll @@ -404,7 +404,7 @@ define amdgpu_kernel void @flat_scratch_load(float %a, float %b, <8 x i32> %desc ; GCN-NEXT: image_sample v0, v[0:1], s[8:15], s[0:3] dmask:0x1 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_add_f32_e32 v0, v2, v0 -; GCN-NEXT: exp mrt0 v0, off, off, off done vm +; GCN-NEXT: exp mrt0, v0, off, off, off done vm ; GCN-NEXT: s_endpgm ; ; GCN-SCRATCH-LABEL: flat_scratch_load: @@ -432,7 +432,7 @@ define amdgpu_kernel void @flat_scratch_load(float %a, float %b, <8 x i32> %desc ; GCN-SCRATCH-NEXT: image_sample v0, v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GCN-SCRATCH-NEXT: v_add_f32_e32 v0, v2, v0 -; GCN-SCRATCH-NEXT: exp mrt0 v0, off, off, off done vm +; GCN-SCRATCH-NEXT: exp mrt0, v0, off, off, off done vm ; GCN-SCRATCH-NEXT: s_endpgm .entry: %alloca = alloca float, align 4, addrspace(5) @@ -469,7 +469,7 @@ define amdgpu_kernel void @flat_scratch_load_clause(float %a, float %b, <8 x i32 ; GCN-NEXT: buffer_load_dword v1, off, s[12:15], 0 offset:4 ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-NEXT: exp mrt0 v0, off, off, off done vm +; GCN-NEXT: exp mrt0, v0, off, off, off done vm ; GCN-NEXT: s_endpgm ; ; GCN-SCRATCH-LABEL: flat_scratch_load_clause: @@ -491,7 +491,7 @@ define amdgpu_kernel void @flat_scratch_load_clause(float %a, float %b, <8 x i32 ; GCN-SCRATCH-NEXT: scratch_load_dword v1, off, off offset:4 ; GCN-SCRATCH-NEXT: s_waitcnt vmcnt(0) ; GCN-SCRATCH-NEXT: v_add_f32_e32 v0, v0, v1 -; GCN-SCRATCH-NEXT: exp mrt0 v0, off, off, off done vm +; GCN-SCRATCH-NEXT: exp mrt0, v0, off, off, off done vm ; GCN-SCRATCH-NEXT: s_endpgm .entry: %alloca = alloca float, align 4, addrspace(5) diff --git a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll index 4aa1ddee2efe..962cd28693b9 100644 --- a/llvm/test/CodeGen/AMDGPU/required-export-priority.ll +++ b/llvm/test/CodeGen/AMDGPU/required-export-priority.ll @@ -6,8 +6,8 @@ define amdgpu_ps void @test_export_zeroes_f32() #0 { ; GCN: ; %bb.0: ; GCN-NEXT: s_setprio 2 ; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: exp mrt0 off, off, off, off -; GCN-NEXT: exp mrt0 off, off, off, off done +; GCN-NEXT: exp mrt0, off, off, off, off +; GCN-NEXT: exp mrt0, off, off, off, off done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 @@ -25,7 +25,7 @@ define amdgpu_ps void @test_export_en_src0_f32() #0 { ; GCN-NEXT: v_mov_b32_e32 v1, 0.5 ; GCN-NEXT: v_mov_b32_e32 v2, 2.0 ; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0 v3, off, off, off done +; GCN-NEXT: exp mrt0, v3, off, off, off done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 @@ -42,7 +42,7 @@ define amdgpu_gs void @test_export_gs() #0 { ; GCN-NEXT: v_mov_b32_e32 v1, 0.5 ; GCN-NEXT: v_mov_b32_e32 v2, 2.0 ; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0 off, v2, off, off done +; GCN-NEXT: exp mrt0, off, v2, off, off done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 @@ -59,7 +59,7 @@ define amdgpu_hs void @test_export_hs() #0 { ; GCN-NEXT: v_mov_b32_e32 v1, 0.5 ; GCN-NEXT: v_mov_b32_e32 v2, 2.0 ; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0 off, v2, off, off done +; GCN-NEXT: exp mrt0, off, v2, off, off done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 @@ -75,7 +75,7 @@ define amdgpu_gfx void @test_export_gfx(float %v) #0 { ; GCN-NEXT: v_mov_b32_e32 v1, 4.0 ; GCN-NEXT: v_mov_b32_e32 v2, 0.5 ; GCN-NEXT: v_mov_b32_e32 v3, 2.0 -; GCN-NEXT: exp mrt0 off, v3, off, off done +; GCN-NEXT: exp mrt0, off, v3, off, off done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_waitcnt_expcnt null, 0x0 ; GCN-NEXT: s_nop 0 @@ -94,7 +94,7 @@ define amdgpu_cs void @test_export_cs() #0 { ; GCN-NEXT: v_mov_b32_e32 v1, 0.5 ; GCN-NEXT: v_mov_b32_e32 v2, 2.0 ; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0 off, v2, off, off done +; GCN-NEXT: exp mrt0, off, v2, off, off done ; GCN-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -107,7 +107,7 @@ define amdgpu_kernel void @test_export_kernel() #0 { ; GCN-NEXT: v_mov_b32_e32 v1, 0.5 ; GCN-NEXT: v_mov_b32_e32 v2, 2.0 ; GCN-NEXT: v_mov_b32_e32 v3, 1.0 -; GCN-NEXT: exp mrt0 off, v2, off, off done +; GCN-NEXT: exp mrt0, off, v2, off, off done ; GCN-NEXT: s_endpgm call void @llvm.amdgcn.exp.f32(i32 0, i32 2, float 1.0, float 2.0, float 0.5, float 4.0, i1 true, i1 false) ret void @@ -136,7 +136,7 @@ define amdgpu_ps void @test_if_export_f32(i32 %flag, float %x, float %y, float % ; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GCN-NEXT: s_cbranch_execz .LBB9_2 ; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0 v1, v2, v3, v4 +; GCN-NEXT: exp mrt0, v1, v2, v3, v4 ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_waitcnt_expcnt null, 0x0 ; GCN-NEXT: s_nop 0 @@ -163,7 +163,7 @@ define amdgpu_ps void @test_if_export_vm_f32(i32 %flag, float %x, float %y, floa ; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GCN-NEXT: s_cbranch_execz .LBB10_2 ; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0 v1, v2, v3, v4 +; GCN-NEXT: exp mrt0, v1, v2, v3, v4 ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_waitcnt_expcnt null, 0x0 ; GCN-NEXT: s_nop 0 @@ -190,7 +190,7 @@ define amdgpu_ps void @test_if_export_done_f32(i32 %flag, float %x, float %y, fl ; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GCN-NEXT: s_cbranch_execz .LBB11_2 ; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0 v1, v2, v3, v4 done +; GCN-NEXT: exp mrt0, v1, v2, v3, v4 done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_waitcnt_expcnt null, 0x0 ; GCN-NEXT: s_nop 0 @@ -217,7 +217,7 @@ define amdgpu_ps void @test_if_export_vm_done_f32(i32 %flag, float %x, float %y, ; GCN-NEXT: v_cmpx_ne_u32_e32 0, v0 ; GCN-NEXT: s_cbranch_execz .LBB12_2 ; GCN-NEXT: ; %bb.1: ; %exp -; GCN-NEXT: exp mrt0 v1, v2, v3, v4 done +; GCN-NEXT: exp mrt0, v1, v2, v3, v4 done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_waitcnt_expcnt null, 0x0 ; GCN-NEXT: s_nop 0 @@ -245,9 +245,9 @@ define amdgpu_ps void @test_export_pos_before_param_across_load(i32 %idx) #0 { ; GCN-NEXT: v_mov_b32_e32 v2, 1.0 ; GCN-NEXT: v_mov_b32_e32 v3, 0.5 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: exp pos0 v1, v1, v1, v0 done -; GCN-NEXT: exp invalid_target_32 v2, v2, v2, v2 -; GCN-NEXT: exp invalid_target_33 v2, v2, v2, v3 +; GCN-NEXT: exp pos0, v1, v1, v1, v0 done +; GCN-NEXT: exp invalid_target_32, v2, v2, v2, v2 +; GCN-NEXT: exp invalid_target_33, v2, v2, v2, v3 ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 @@ -271,15 +271,15 @@ define amdgpu_ps void @test_export_across_store_load(i32 %idx, float %v) #0 { ; GCN-NEXT: scratch_store_b32 v0, v1, off ; GCN-NEXT: scratch_load_b32 v0, off, off ; GCN-NEXT: v_mov_b32_e32 v1, 1.0 -; GCN-NEXT: exp pos0 v2, v2, v2, v1 done +; GCN-NEXT: exp pos0, v2, v2, v2, v1 done ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_waitcnt_expcnt null, 0x0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_setprio 2 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: exp invalid_target_32 v0, v2, v1, v2 -; GCN-NEXT: exp invalid_target_33 v0, v2, v1, v2 +; GCN-NEXT: exp invalid_target_32, v0, v2, v1, v2 +; GCN-NEXT: exp invalid_target_33, v0, v2, v1, v2 ; GCN-NEXT: s_setprio 0 ; GCN-NEXT: s_nop 0 ; GCN-NEXT: s_nop 0 diff --git a/llvm/test/CodeGen/AMDGPU/ret.ll b/llvm/test/CodeGen/AMDGPU/ret.ll index 43f5c22669be..059fa6b69207 100644 --- a/llvm/test/CodeGen/AMDGPU/ret.ll +++ b/llvm/test/CodeGen/AMDGPU/ret.ll @@ -5,7 +5,7 @@ ; GCN-LABEL: {{^}}vgpr: ; GCN-DAG: v_mov_b32_e32 v1, v0 -; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm +; GCN-DAG: exp mrt0, v0, v0, v0, v0 done vm ; GCN: s_waitcnt expcnt(0) ; GCN: v_add_f32_e32 v0, 1.0, v1 ; GCN-NOT: s_endpgm @@ -19,7 +19,7 @@ bb: } ; GCN-LABEL: {{^}}vgpr_literal: -; GCN: exp mrt0 v0, v0, v0, v0 done vm +; GCN: exp mrt0, v0, v0, v0, v0 done vm ; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0 @@ -205,7 +205,7 @@ bb: } ; GCN-LABEL: {{^}}both: -; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm +; GCN-DAG: exp mrt0, v0, v0, v0, v0 done vm ; GCN-DAG: v_mov_b32_e32 v1, v0 ; GCN-DAG: s_mov_b32 s1, s2 ; GCN-DAG: s_waitcnt expcnt(0) @@ -227,7 +227,7 @@ bb: } ; GCN-LABEL: {{^}}structure_literal: -; GCN: exp mrt0 v0, v0, v0, v0 done vm +; GCN: exp mrt0, v0, v0, v0, v0 done vm ; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: s_mov_b32 s0, 2 diff --git a/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll b/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll index cac1fe9605a1..333f2527dcc9 100644 --- a/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll +++ b/llvm/test/CodeGen/AMDGPU/scheduler-rp-calc-one-successor-two-predecessors-bug.ll @@ -52,11 +52,11 @@ define amdgpu_ps void @_amdgpu_ps_main(float %arg) { ; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: v_cvt_pkrtz_f16_f32 v1, 0, v1 ; GFX900-NEXT: v_cvt_pkrtz_f16_f32 v0, v2, v0 -; GFX900-NEXT: exp mrt0 off, off, off, off compr +; GFX900-NEXT: exp mrt0, off, off, off, off compr ; GFX900-NEXT: s_endpgm ; GFX900-NEXT: .LBB0_6: ; GFX900-NEXT: s_mov_b64 exec, 0 -; GFX900-NEXT: exp null off, off, off, off done vm +; GFX900-NEXT: exp null, off, off, off, off done vm ; GFX900-NEXT: s_endpgm bb: %i = fcmp olt float %arg, 0.000000e+00 diff --git a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll index 8efa58d1e6f1..2c8cd46b84a8 100644 --- a/llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll +++ b/llvm/test/CodeGen/AMDGPU/si-annotate-cf-kill.ll @@ -41,7 +41,7 @@ define amdgpu_ps float @uniform_kill(float %a, i32 %b, float %c) { ; SI-NEXT: s_branch .LBB0_7 ; SI-NEXT: .LBB0_6: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB0_7: ; @@ -83,7 +83,7 @@ define amdgpu_ps float @uniform_kill(float %a, i32 %b, float %c) { ; FLAT-NEXT: s_branch .LBB0_7 ; FLAT-NEXT: .LBB0_6: ; FLAT-NEXT: s_mov_b64 exec, 0 -; FLAT-NEXT: exp null off, off, off, off done vm +; FLAT-NEXT: exp null, off, off, off, off done vm ; FLAT-NEXT: s_endpgm ; FLAT-NEXT: .LBB0_7: entry: diff --git a/llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll b/llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll index ac271ff6a258..9d0fd4541ba8 100644 --- a/llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll +++ b/llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll @@ -12,7 +12,7 @@ define amdgpu_gs void @_amdgpu_gs_main() { ; CHECK-NEXT: v_mov_b32_e32 v2, v0 ; CHECK-NEXT: v_mov_b32_e32 v3, v0 ; CHECK-NEXT: s_mov_b32 s3, s0 -; CHECK-NEXT: exp mrt0 off, off, off, off +; CHECK-NEXT: exp mrt0, off, off, off, off ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], v0, s[0:3], 0 idxen ; CHECK-NEXT: s_endpgm entry: diff --git a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll index 4b4fe73826e0..08cc6f9b6fff 100644 --- a/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll +++ b/llvm/test/CodeGen/AMDGPU/skip-if-dead.ll @@ -20,7 +20,7 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { ; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: .LBB1_1: ; WAVE64-NEXT: s_mov_b64 exec, 0 -; WAVE64-NEXT: exp null off, off, off, off done vm +; WAVE64-NEXT: exp null, off, off, off, off done vm ; WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg: @@ -30,7 +30,7 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB1_1: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_depth_0_imm_neg: @@ -40,7 +40,7 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB1_1: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm call void @llvm.amdgcn.kill(i1 false) ret void @@ -60,7 +60,7 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { ; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: .LBB2_2: ; WAVE64-NEXT: s_mov_b64 exec, 0 -; WAVE64-NEXT: exp null off, off, off, off done vm +; WAVE64-NEXT: exp null, off, off, off, off done vm ; WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_depth_0_imm_neg_x2: @@ -75,7 +75,7 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB2_2: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_depth_0_imm_neg_x2: @@ -92,7 +92,7 @@ define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB2_2: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm call void @llvm.amdgcn.kill(i1 false) call void @llvm.amdgcn.kill(i1 false) @@ -108,7 +108,7 @@ define amdgpu_ps void @test_kill_depth_var(float %x) #0 { ; WAVE64-NEXT: s_endpgm ; WAVE64-NEXT: .LBB3_1: ; WAVE64-NEXT: s_mov_b64 exec, 0 -; WAVE64-NEXT: exp null off, off, off, off done vm +; WAVE64-NEXT: exp null, off, off, off, off done vm ; WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_depth_var: @@ -119,7 +119,7 @@ define amdgpu_ps void @test_kill_depth_var(float %x) #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB3_1: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_depth_var: @@ -130,7 +130,7 @@ define amdgpu_ps void @test_kill_depth_var(float %x) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB3_1: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm %cmp = fcmp olt float %x, 0.0 call void @llvm.amdgcn.kill(i1 %cmp) @@ -153,7 +153,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB4_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_same: @@ -170,7 +170,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB4_2: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_same: @@ -187,7 +187,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB4_2: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_depth_var_x2_same: @@ -205,7 +205,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB4_2: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm %cmp = fcmp olt float %x, 0.0 call void @llvm.amdgcn.kill(i1 %cmp) @@ -229,7 +229,7 @@ define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB5_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: test_kill_depth_var_x2: @@ -246,7 +246,7 @@ define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB5_2: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_depth_var_x2: @@ -263,7 +263,7 @@ define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB5_2: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_depth_var_x2: @@ -281,7 +281,7 @@ define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB5_2: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm %cmp.x = fcmp olt float %x, 0.0 call void @llvm.amdgcn.kill(i1 %cmp.x) @@ -308,7 +308,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB6_2: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: test_kill_depth_var_x2_instructions: @@ -328,7 +328,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB6_2: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_depth_var_x2_instructions: @@ -348,7 +348,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB6_2: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_depth_var_x2_instructions: @@ -369,7 +369,7 @@ define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB6_2: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm %cmp.x = fcmp olt float %x, 0.0 call void @llvm.amdgcn.kill(i1 %cmp.x) @@ -412,7 +412,7 @@ define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 { ; SI-NEXT: s_branch .LBB7_5 ; SI-NEXT: .LBB7_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB7_5: ; @@ -447,7 +447,7 @@ define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 { ; GFX10-WAVE64-NEXT: s_branch .LBB7_5 ; GFX10-WAVE64-NEXT: .LBB7_4: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB7_5: ; @@ -482,7 +482,7 @@ define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 { ; GFX10-WAVE32-NEXT: s_branch .LBB7_5 ; GFX10-WAVE32-NEXT: .LBB7_4: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB7_5: ; @@ -518,7 +518,7 @@ define amdgpu_ps float @test_kill_control_flow(i32 inreg %arg) #0 { ; GFX11-NEXT: s_branch .LBB7_5 ; GFX11-NEXT: .LBB7_4: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB7_5: entry: @@ -590,7 +590,7 @@ define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB8_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: test_kill_control_flow_remainder: @@ -634,7 +634,7 @@ define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB8_4: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_control_flow_remainder: @@ -678,7 +678,7 @@ define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB8_4: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_control_flow_remainder: @@ -722,7 +722,7 @@ define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB8_4: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm entry: %cmp = icmp eq i32 %arg, 0 @@ -789,7 +789,7 @@ define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 { ; SI-NEXT: s_branch .LBB9_5 ; SI-NEXT: .LBB9_4: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB9_5: ; @@ -826,7 +826,7 @@ define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 { ; GFX10-WAVE64-NEXT: s_branch .LBB9_5 ; GFX10-WAVE64-NEXT: .LBB9_4: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB9_5: ; @@ -863,7 +863,7 @@ define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 { ; GFX10-WAVE32-NEXT: s_branch .LBB9_5 ; GFX10-WAVE32-NEXT: .LBB9_4: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB9_5: ; @@ -901,7 +901,7 @@ define amdgpu_ps float @test_kill_control_flow_return(i32 inreg %arg) #0 { ; GFX11-NEXT: s_branch .LBB9_5 ; GFX11-NEXT: .LBB9_4: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB9_5: entry: @@ -975,7 +975,7 @@ define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB10_5: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: test_kill_divergent_loop: @@ -1018,7 +1018,7 @@ define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB10_4: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: test_kill_divergent_loop: @@ -1061,7 +1061,7 @@ define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB10_4: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: test_kill_divergent_loop: @@ -1104,7 +1104,7 @@ define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB10_4: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm entry: %cmp = icmp eq i32 %arg, 0 @@ -1167,7 +1167,7 @@ define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i32 inreg %y) #0 ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB11_6: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: phi_use_def_before_kill: @@ -1198,7 +1198,7 @@ define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i32 inreg %y) #0 ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB11_6: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: phi_use_def_before_kill: @@ -1229,7 +1229,7 @@ define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i32 inreg %y) #0 ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB11_6: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: phi_use_def_before_kill: @@ -1262,7 +1262,7 @@ define amdgpu_ps void @phi_use_def_before_kill(float inreg %x, i32 inreg %y) #0 ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB11_6: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm bb: %tmp = fadd float %x, 1.000000e+00 @@ -1309,7 +1309,7 @@ define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1 ; SI-NEXT: ; %bb.4: ; %bb5 ; SI-NEXT: .LBB12_5: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: no_skip_no_successors: @@ -1329,7 +1329,7 @@ define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1 ; GFX10-WAVE64-NEXT: ; %bb.4: ; %bb5 ; GFX10-WAVE64-NEXT: .LBB12_5: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: no_skip_no_successors: @@ -1349,7 +1349,7 @@ define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1 ; GFX10-WAVE32-NEXT: ; %bb.4: ; %bb5 ; GFX10-WAVE32-NEXT: .LBB12_5: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: no_skip_no_successors: @@ -1370,7 +1370,7 @@ define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1 ; GFX11-NEXT: ; %bb.4: ; %bb5 ; GFX11-NEXT: .LBB12_5: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm bb: %tmp = fcmp ult float %arg1, 0.000000e+00 @@ -1426,7 +1426,7 @@ define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB13_6: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: if_after_kill_block: @@ -1458,7 +1458,7 @@ define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB13_6: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: if_after_kill_block: @@ -1490,7 +1490,7 @@ define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB13_6: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: if_after_kill_block: @@ -1524,7 +1524,7 @@ define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, float %arg2, ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB13_6: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm bb: %tmp = fcmp ult float %arg1, 0.000000e+00 @@ -1577,11 +1577,11 @@ define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) { ; SI-NEXT: v_mul_f32_e32 v2, v0, v1 ; SI-NEXT: ; %bb.5: ; %export ; SI-NEXT: s_or_b64 exec, exec, s[0:1] -; SI-NEXT: exp mrt0 v2, v2, v2, v2 done vm +; SI-NEXT: exp mrt0, v2, v2, v2, v2 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB14_6: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: cbranch_kill: @@ -1609,11 +1609,11 @@ define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) { ; GFX10-WAVE64-NEXT: v_mul_f32_e32 v2, v0, v1 ; GFX10-WAVE64-NEXT: ; %bb.5: ; %export ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v2, v2 done vm +; GFX10-WAVE64-NEXT: exp mrt0, v2, v2, v2, v2 done vm ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB14_6: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: cbranch_kill: @@ -1641,11 +1641,11 @@ define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) { ; GFX10-WAVE32-NEXT: v_mul_f32_e32 v2, v0, v1 ; GFX10-WAVE32-NEXT: ; %bb.5: ; %export ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s0 -; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v2, v2 done vm +; GFX10-WAVE32-NEXT: exp mrt0, v2, v2, v2, v2 done vm ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB14_6: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: cbranch_kill: @@ -1674,11 +1674,11 @@ define amdgpu_ps void @cbranch_kill(i32 inreg %0, float %val0, float %val1) { ; GFX11-NEXT: v_mul_f32_e32 v2, v0, v1 ; GFX11-NEXT: ; %bb.5: ; %export ; GFX11-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX11-NEXT: exp mrt0 v2, v2, v2, v2 done +; GFX11-NEXT: exp mrt0, v2, v2, v2, v2 done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB14_6: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm .entry: %sample = call float @llvm.amdgcn.image.sample.l.2darray.f32.f32(i32 1, float %val1, float %val1, float %val1, float 0.000000e+00, <8 x i32> poison, <4 x i32> poison, i1 false, i32 0, i32 0) @@ -1735,15 +1735,15 @@ define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) { ; SI-NEXT: s_branch .LBB15_2 ; SI-NEXT: .LBB15_6: ; %Flow ; SI-NEXT: s_or_b64 exec, exec, s[0:1] -; SI-NEXT: exp mrt0 v2, v2, v0, v0 done vm +; SI-NEXT: exp mrt0, v2, v2, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB15_7: ; SI-NEXT: v_mov_b32_e32 v2, -1 -; SI-NEXT: exp mrt0 v2, v2, v0, v0 done vm +; SI-NEXT: exp mrt0, v2, v2, v0, v0 done vm ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB15_8: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: complex_loop: @@ -1780,15 +1780,15 @@ define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) { ; GFX10-WAVE64-NEXT: s_branch .LBB15_2 ; GFX10-WAVE64-NEXT: .LBB15_6: ; %Flow ; GFX10-WAVE64-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v0, v0 done vm +; GFX10-WAVE64-NEXT: exp mrt0, v2, v2, v0, v0 done vm ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB15_7: ; GFX10-WAVE64-NEXT: v_mov_b32_e32 v2, -1 -; GFX10-WAVE64-NEXT: exp mrt0 v2, v2, v0, v0 done vm +; GFX10-WAVE64-NEXT: exp mrt0, v2, v2, v0, v0 done vm ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB15_8: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: complex_loop: @@ -1825,15 +1825,15 @@ define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) { ; GFX10-WAVE32-NEXT: s_branch .LBB15_2 ; GFX10-WAVE32-NEXT: .LBB15_6: ; %Flow ; GFX10-WAVE32-NEXT: s_or_b32 exec_lo, exec_lo, s0 -; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v0, v0 done vm +; GFX10-WAVE32-NEXT: exp mrt0, v2, v2, v0, v0 done vm ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB15_7: ; GFX10-WAVE32-NEXT: v_mov_b32_e32 v2, -1 -; GFX10-WAVE32-NEXT: exp mrt0 v2, v2, v0, v0 done vm +; GFX10-WAVE32-NEXT: exp mrt0, v2, v2, v0, v0 done vm ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB15_8: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: complex_loop: @@ -1871,15 +1871,15 @@ define amdgpu_ps void @complex_loop(i32 inreg %cmpa, i32 %cmpb, i32 %cmpc) { ; GFX11-NEXT: s_branch .LBB15_2 ; GFX11-NEXT: .LBB15_6: ; %Flow ; GFX11-NEXT: s_or_b64 exec, exec, s[0:1] -; GFX11-NEXT: exp mrt0 v2, v2, v0, v0 done +; GFX11-NEXT: exp mrt0, v2, v2, v0, v0 done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB15_7: ; GFX11-NEXT: v_mov_b32_e32 v2, -1 -; GFX11-NEXT: exp mrt0 v2, v2, v0, v0 done +; GFX11-NEXT: exp mrt0, v2, v2, v0, v0 done ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB15_8: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm .entry: %flaga = icmp sgt i32 %cmpa, 0 @@ -1991,7 +1991,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0 ; SI-NEXT: s_endpgm ; SI-NEXT: .LBB17_6: ; SI-NEXT: s_mov_b64 exec, 0 -; SI-NEXT: exp null off, off, off, off done vm +; SI-NEXT: exp null, off, off, off, off done vm ; SI-NEXT: s_endpgm ; ; GFX10-WAVE64-LABEL: scc_use_after_kill_inst: @@ -2023,7 +2023,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0 ; GFX10-WAVE64-NEXT: s_endpgm ; GFX10-WAVE64-NEXT: .LBB17_6: ; GFX10-WAVE64-NEXT: s_mov_b64 exec, 0 -; GFX10-WAVE64-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE64-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE64-NEXT: s_endpgm ; ; GFX10-WAVE32-LABEL: scc_use_after_kill_inst: @@ -2055,7 +2055,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0 ; GFX10-WAVE32-NEXT: s_endpgm ; GFX10-WAVE32-NEXT: .LBB17_6: ; GFX10-WAVE32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-WAVE32-NEXT: exp null off, off, off, off done vm +; GFX10-WAVE32-NEXT: exp null, off, off, off, off done vm ; GFX10-WAVE32-NEXT: s_endpgm ; ; GFX11-LABEL: scc_use_after_kill_inst: @@ -2089,7 +2089,7 @@ define amdgpu_ps void @scc_use_after_kill_inst(float inreg %x, i32 inreg %y) #0 ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB17_6: ; GFX11-NEXT: s_mov_b64 exec, 0 -; GFX11-NEXT: exp mrt0 off, off, off, off done +; GFX11-NEXT: exp mrt0, off, off, off, off done ; GFX11-NEXT: s_endpgm bb: %tmp = fadd float %x, 1.000000e+00 diff --git a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll index 199ab49fa19d..66a29b09ff0f 100644 --- a/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll +++ b/llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll @@ -68,7 +68,7 @@ define amdgpu_ps void @foo() #0 { ; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: v_mul_f32_e32 v0, 0x41280000, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x41380000, v1 -; GCN-NEXT: exp mrt0 v1, v0, v0, v0 done vm +; GCN-NEXT: exp mrt0, v1, v0, v0, v0 done vm ; GCN-NEXT: s_endpgm bb: %undef0 = freeze i1 poison diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 8e7dc4072c01..ab3c4f43b2b6 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -80,7 +80,7 @@ define amdgpu_ps void @test_vopc_vcmp(float %x) { ; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: .LBB2_1: ; GFX1032-NEXT: s_mov_b32 exec_lo, 0 -; GFX1032-NEXT: exp null off, off, off, off done vm +; GFX1032-NEXT: exp null, off, off, off, off done vm ; GFX1032-NEXT: s_endpgm ; ; GFX1064-LABEL: test_vopc_vcmp: @@ -91,7 +91,7 @@ define amdgpu_ps void @test_vopc_vcmp(float %x) { ; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: .LBB2_1: ; GFX1064-NEXT: s_mov_b64 exec, 0 -; GFX1064-NEXT: exp null off, off, off, off done vm +; GFX1064-NEXT: exp null, off, off, off, off done vm ; GFX1064-NEXT: s_endpgm %cmp = fcmp oge float %x, 0.0 call void @llvm.amdgcn.kill(i1 %cmp) @@ -1726,7 +1726,7 @@ define amdgpu_ps void @test_kill_i1_terminator_float() #0 { ; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: .LBB31_1: ; GFX1032-NEXT: s_mov_b32 exec_lo, 0 -; GFX1032-NEXT: exp null off, off, off, off done vm +; GFX1032-NEXT: exp null, off, off, off, off done vm ; GFX1032-NEXT: s_endpgm ; ; GFX1064-LABEL: test_kill_i1_terminator_float: @@ -1736,7 +1736,7 @@ define amdgpu_ps void @test_kill_i1_terminator_float() #0 { ; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: .LBB31_1: ; GFX1064-NEXT: s_mov_b64 exec, 0 -; GFX1064-NEXT: exp null off, off, off, off done vm +; GFX1064-NEXT: exp null, off, off, off, off done vm ; GFX1064-NEXT: s_endpgm call void @llvm.amdgcn.kill(i1 false) ret void @@ -1753,7 +1753,7 @@ define amdgpu_gs void @test_kill_i1_terminator_i1(i32 %a, i32 %b, i32 %c, i32 %d ; GFX1032-NEXT: s_andn2_b32 s1, s1, s0 ; GFX1032-NEXT: s_and_b32 exec_lo, exec_lo, s1 ; GFX1032-NEXT: v_mov_b32_e32 v0, 0 -; GFX1032-NEXT: exp mrt0 off, off, off, off +; GFX1032-NEXT: exp mrt0, off, off, off, off ; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: s_mov_b32 exec_lo, 0 @@ -1769,7 +1769,7 @@ define amdgpu_gs void @test_kill_i1_terminator_i1(i32 %a, i32 %b, i32 %c, i32 %d ; GFX1064-NEXT: s_andn2_b64 s[2:3], s[2:3], s[0:1] ; GFX1064-NEXT: s_and_b64 exec, exec, s[2:3] ; GFX1064-NEXT: v_mov_b32_e32 v0, 0 -; GFX1064-NEXT: exp mrt0 off, off, off, off +; GFX1064-NEXT: exp mrt0, off, off, off, off ; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: s_mov_b64 exec, 0 @@ -2243,11 +2243,11 @@ define amdgpu_ps void @test_wqm_vote(float %a) { ; GFX1032-NEXT: s_cbranch_scc0 .LBB44_2 ; GFX1032-NEXT: ; %bb.1: ; GFX1032-NEXT: s_and_b32 exec_lo, exec_lo, s0 -; GFX1032-NEXT: exp mrt0 off, off, off, off +; GFX1032-NEXT: exp mrt0, off, off, off, off ; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: .LBB44_2: ; GFX1032-NEXT: s_mov_b32 exec_lo, 0 -; GFX1032-NEXT: exp null off, off, off, off done vm +; GFX1032-NEXT: exp null, off, off, off, off done vm ; GFX1032-NEXT: s_endpgm ; ; GFX1064-LABEL: test_wqm_vote: @@ -2261,11 +2261,11 @@ define amdgpu_ps void @test_wqm_vote(float %a) { ; GFX1064-NEXT: s_cbranch_scc0 .LBB44_2 ; GFX1064-NEXT: ; %bb.1: ; GFX1064-NEXT: s_and_b64 exec, exec, s[0:1] -; GFX1064-NEXT: exp mrt0 off, off, off, off +; GFX1064-NEXT: exp mrt0, off, off, off, off ; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: .LBB44_2: ; GFX1064-NEXT: s_mov_b64 exec, 0 -; GFX1064-NEXT: exp null off, off, off, off done vm +; GFX1064-NEXT: exp null, off, off, off, off done vm ; GFX1064-NEXT: s_endpgm %c1 = fcmp une float %a, 0.0 %c2 = call i1 @llvm.amdgcn.wqm.vote(i1 %c1) diff --git a/llvm/test/CodeGen/AMDGPU/wqm.ll b/llvm/test/CodeGen/AMDGPU/wqm.ll index aa68ee0e7793..aad5ef0251d3 100644 --- a/llvm/test/CodeGen/AMDGPU/wqm.ll +++ b/llvm/test/CodeGen/AMDGPU/wqm.ll @@ -145,7 +145,7 @@ define amdgpu_ps void @test3x(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <8 ; GFX9-W64-NEXT: s_and_b64 exec, exec, s[0:1] ; GFX9-W64-NEXT: image_sample v[0:3], v[2:3], s[4:11], s[12:15] dmask:0xf ; GFX9-W64-NEXT: s_waitcnt vmcnt(0) -; GFX9-W64-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX9-W64-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX9-W64-NEXT: s_endpgm ; ; GFX10-W32-LABEL: test3x: @@ -160,7 +160,7 @@ define amdgpu_ps void @test3x(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <8 ; GFX10-W32-NEXT: s_and_b32 exec_lo, exec_lo, s0 ; GFX10-W32-NEXT: image_sample v[0:3], v[2:3], s[4:11], s[12:15] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX10-W32-NEXT: s_waitcnt vmcnt(0) -; GFX10-W32-NEXT: exp mrt0 v0, v1, v2, v3 done vm +; GFX10-W32-NEXT: exp mrt0, v0, v1, v2, v3 done vm ; GFX10-W32-NEXT: s_endpgm main_body: %inst23 = extractelement <2 x float> %pos, i32 0 @@ -1782,7 +1782,7 @@ define amdgpu_ps <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg ; GFX9-W64-NEXT: s_branch .LBB32_3 ; GFX9-W64-NEXT: .LBB32_2: ; GFX9-W64-NEXT: s_mov_b64 exec, 0 -; GFX9-W64-NEXT: exp null off, off, off, off done vm +; GFX9-W64-NEXT: exp null, off, off, off, off done vm ; GFX9-W64-NEXT: s_endpgm ; GFX9-W64-NEXT: .LBB32_3: ; @@ -1814,7 +1814,7 @@ define amdgpu_ps <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg ; GFX10-W32-NEXT: s_branch .LBB32_3 ; GFX10-W32-NEXT: .LBB32_2: ; GFX10-W32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-W32-NEXT: exp null off, off, off, off done vm +; GFX10-W32-NEXT: exp null, off, off, off, off done vm ; GFX10-W32-NEXT: s_endpgm ; GFX10-W32-NEXT: .LBB32_3: main_body: @@ -1859,7 +1859,7 @@ define amdgpu_ps <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg ; GFX9-W64-NEXT: s_branch .LBB33_3 ; GFX9-W64-NEXT: .LBB33_2: ; GFX9-W64-NEXT: s_mov_b64 exec, 0 -; GFX9-W64-NEXT: exp null off, off, off, off done vm +; GFX9-W64-NEXT: exp null, off, off, off, off done vm ; GFX9-W64-NEXT: s_endpgm ; GFX9-W64-NEXT: .LBB33_3: ; @@ -1883,7 +1883,7 @@ define amdgpu_ps <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg ; GFX10-W32-NEXT: s_branch .LBB33_3 ; GFX10-W32-NEXT: .LBB33_2: ; GFX10-W32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-W32-NEXT: exp null off, off, off, off done vm +; GFX10-W32-NEXT: exp null, off, off, off, off done vm ; GFX10-W32-NEXT: s_endpgm ; GFX10-W32-NEXT: .LBB33_3: main_body: @@ -2957,7 +2957,7 @@ define amdgpu_ps float @test_strict_wqm_within_wqm_with_kill(<8 x i32> inreg %rs ; GFX9-W64-NEXT: s_branch .LBB51_3 ; GFX9-W64-NEXT: .LBB51_2: ; GFX9-W64-NEXT: s_mov_b64 exec, 0 -; GFX9-W64-NEXT: exp null off, off, off, off done vm +; GFX9-W64-NEXT: exp null, off, off, off, off done vm ; GFX9-W64-NEXT: s_endpgm ; GFX9-W64-NEXT: .LBB51_3: ; @@ -2992,7 +2992,7 @@ define amdgpu_ps float @test_strict_wqm_within_wqm_with_kill(<8 x i32> inreg %rs ; GFX10-W32-NEXT: s_branch .LBB51_3 ; GFX10-W32-NEXT: .LBB51_2: ; GFX10-W32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-W32-NEXT: exp null off, off, off, off done vm +; GFX10-W32-NEXT: exp null, off, off, off, off done vm ; GFX10-W32-NEXT: s_endpgm ; GFX10-W32-NEXT: .LBB51_3: main_body: @@ -3366,7 +3366,7 @@ define amdgpu_ps void @test_for_deactivating_lanes_in_wave32(ptr addrspace(6) in ; GFX9-W64-NEXT: s_endpgm ; GFX9-W64-NEXT: .LBB55_1: ; GFX9-W64-NEXT: s_mov_b64 exec, 0 -; GFX9-W64-NEXT: exp null off, off, off, off done vm +; GFX9-W64-NEXT: exp null, off, off, off, off done vm ; GFX9-W64-NEXT: s_endpgm ; ; GFX10-W32-LABEL: test_for_deactivating_lanes_in_wave32: @@ -3382,7 +3382,7 @@ define amdgpu_ps void @test_for_deactivating_lanes_in_wave32(ptr addrspace(6) in ; GFX10-W32-NEXT: s_endpgm ; GFX10-W32-NEXT: .LBB55_1: ; GFX10-W32-NEXT: s_mov_b32 exec_lo, 0 -; GFX10-W32-NEXT: exp null off, off, off, off done vm +; GFX10-W32-NEXT: exp null, off, off, off, off done vm ; GFX10-W32-NEXT: s_endpgm main_body: %1 = ptrtoint ptr addrspace(6) %0 to i32 @@ -3481,7 +3481,7 @@ define amdgpu_gs void @wqm_init_exec_wwm() { ; GFX9-W64-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-W64-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s[0:1] -; GFX9-W64-NEXT: exp mrt0 off, off, off, off +; GFX9-W64-NEXT: exp mrt0, off, off, off, off ; GFX9-W64-NEXT: s_endpgm ; ; GFX10-W32-LABEL: wqm_init_exec_wwm: @@ -3493,7 +3493,7 @@ define amdgpu_gs void @wqm_init_exec_wwm() { ; GFX10-W32-NEXT: s_cmp_eq_u64 s[0:1], 0 ; GFX10-W32-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-W32-NEXT: v_cndmask_b32_e64 v1, 0, 1.0, s0 -; GFX10-W32-NEXT: exp mrt0 off, off, off, off +; GFX10-W32-NEXT: exp mrt0, off, off, off, off ; GFX10-W32-NEXT: s_endpgm call void @llvm.amdgcn.init.exec(i64 0) %i = call i64 @llvm.amdgcn.ballot.i64(i1 true) diff --git a/llvm/test/MC/AMDGPU/exp-gfx10.s b/llvm/test/MC/AMDGPU/exp-gfx10.s index 6597f0af0926..bc881ad1f79c 100644 --- a/llvm/test/MC/AMDGPU/exp-gfx10.s +++ b/llvm/test/MC/AMDGPU/exp-gfx10.s @@ -5,16 +5,16 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 %s exp pos4 v4, v3, v2, v1 -// GFX10: exp pos4 v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX11: exp pos4 v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp pos4, v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX11: exp pos4, v4, v3, v2, v1 ; encoding: [0x0f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] // SIVI: :[[@LINE-3]]:5: error: exp target is not supported on this GPU exp prim v1, off, off, off -// GFX10: exp prim v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00] -// GFX11: exp prim v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00] +// GFX10: exp prim, v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00] +// GFX11: exp prim, v1, off, off, off ; encoding: [0x41,0x01,0x00,0xf8,0x01,0x00,0x00,0x00] // SIVI: :[[@LINE-3]]:5: error: exp target is not supported on this GPU exp prim v2, v3, off, off -// GFX10: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] -// GFX11: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +// GFX10: exp prim, v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +// GFX11: exp prim, v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] // SIVI: :[[@LINE-3]]:5: error: exp target is not supported on this GPU diff --git a/llvm/test/MC/AMDGPU/exp-gfx11.s b/llvm/test/MC/AMDGPU/exp-gfx11.s index 57aaa5e6f5e7..7c16b2be85d0 100644 --- a/llvm/test/MC/AMDGPU/exp-gfx11.s +++ b/llvm/test/MC/AMDGPU/exp-gfx11.s @@ -4,17 +4,17 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX11 --implicit-check-not=error: %s exp dual_src_blend0 v4, v3, v2, v1 -// GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX11: exp dual_src_blend0, v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] // PREGFX11: :[[@LINE-2]]:5: error: exp target is not supported on this GPU exp dual_src_blend1 v2, v3, off, off -// GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +// GFX11: exp dual_src_blend1, v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] // PREGFX11: :[[@LINE-2]]:5: error: exp target is not supported on this GPU exp mrtz v4, v3, off, off done row_en -// GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] +// GFX11: exp mrtz, v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] // PREGFX11: :[[@LINE-2]]:32: error: invalid operand for instruction exp mrtz v4, v3, v2, v1 row_en -// GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX11: exp mrtz, v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] // PREGFX11: :[[@LINE-2]]:25: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/exp-pregfx11.s b/llvm/test/MC/AMDGPU/exp-pregfx11.s index b4464d060411..3663e01a4086 100644 --- a/llvm/test/MC/AMDGPU/exp-pregfx11.s +++ b/llvm/test/MC/AMDGPU/exp-pregfx11.s @@ -4,57 +4,71 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX89 %s // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck -check-prefix=GFX10 %s +// Check format without comma between target export and first data exp mrt0 v4, v3, v2, v1 done vm -// GFX10: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp mrt0 v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp mrt0, v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrt0, v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrt0, v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01] exp mrt0 v4, v3, v2, v1 vm -// GFX10: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp mrt0 v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp mrt0, v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrt0, v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrt0, v4, v3, v2, v1 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x04,0x03,0x02,0x01] +// Check format with comma between target export and first data +exp mrt0, v4, v3, v2, v1 done vm +// GFX10: exp mrt0, v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrt0, v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrt0, v4, v3, v2, v1 done vm ; encoding: [0x0f,0x18,0x00,0xf8,0x04,0x03,0x02,0x01] + +// Check format without comma between target export and first data +exp mrtz off, off, v7, v7 compr +// GFX10: exp mrtz, off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00] +// GFX89: exp mrtz, off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00] +// SI: exp mrtz, off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00] + +// Check format with comma between target export and first data exp mrtz, off, off, v7, v7 compr -// GFX10: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00] -// GFX89: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00] -// SI: exp mrtz off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00] +// GFX10: exp mrtz, off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00] +// GFX89: exp mrtz, off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xc4,0x00,0x07,0x00,0x00] +// SI: exp mrtz, off, off, v7, v7 compr ; encoding: [0x8c,0x04,0x00,0xf8,0x00,0x07,0x00,0x00] exp mrtz, v3, v3, off, off compr -// GFX10: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00] -// GFX89: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xc4,0x03,0x00,0x00,0x00] -// SI: exp mrtz v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00] +// GFX10: exp mrtz, v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00] +// GFX89: exp mrtz, v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xc4,0x03,0x00,0x00,0x00] +// SI: exp mrtz, v3, v3, off, off compr ; encoding: [0x83,0x04,0x00,0xf8,0x03,0x00,0x00,0x00] exp mrtz, v3, v3, v7, v7 compr -// GFX10: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00] -// GFX89: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x03,0x07,0x00,0x00] -// SI: exp mrtz v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00] +// GFX10: exp mrtz, v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00] +// GFX89: exp mrtz, v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x03,0x07,0x00,0x00] +// SI: exp mrtz, v3, v3, v7, v7 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x03,0x07,0x00,0x00] exp null v4, v3, v2, v1 -// GFX10: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp null v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp null, v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp null, v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp null, v4, v3, v2, v1 ; encoding: [0x9f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] exp null v4, v3, v2, v1 done -// GFX10: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp null v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp null, v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp null, v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp null, v4, v3, v2, v1 done ; encoding: [0x9f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] exp param0 v4, v3, v2, v1 -// GFX10: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp param0 v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp param0, v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp param0, v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp param0, v4, v3, v2, v1 ; encoding: [0x0f,0x02,0x00,0xf8,0x04,0x03,0x02,0x01] exp param0 v4, v3, v2, v1 done -// GFX10: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp param0 v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp param0, v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp param0, v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp param0, v4, v3, v2, v1 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x04,0x03,0x02,0x01] exp param31 v4, v3, v2, v1 -// GFX10: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp param31 v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp param31, v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp param31, v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp param31, v4, v3, v2, v1 ; encoding: [0xff,0x03,0x00,0xf8,0x04,0x03,0x02,0x01] exp param31 v4, v3, v2, v1 done -// GFX10: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp param31 v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp param31, v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp param31, v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp param31, v4, v3, v2, v1 done ; encoding: [0xff,0x0b,0x00,0xf8,0x04,0x03,0x02,0x01] diff --git a/llvm/test/MC/AMDGPU/exp.s b/llvm/test/MC/AMDGPU/exp.s index c63fb44cbd81..a04642929239 100644 --- a/llvm/test/MC/AMDGPU/exp.s +++ b/llvm/test/MC/AMDGPU/exp.s @@ -6,122 +6,130 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck -check-prefix=GFX10 %s // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX12 %s +// Check format without comma between target export and first data exp mrt0 off, off, off, off -// GFX10: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] -// GFX12: export mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] -// GFX89: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] -// SI: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX10: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX89: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// SI: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, off, off, off done -// GFX10: exp mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] -// GFX12: export mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] -// GFX89: exp mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] -// SI: exp mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX10: exp mrt0, off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export mrt0, off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX89: exp mrt0, off, off, off, off done ; encoding: [0x00,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] +// SI: exp mrt0, off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, off, off, v1 done -// GFX10: exp mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] -// GFX12: export mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] -// GFX89: exp mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xc4,0x00,0x00,0x00,0x01] -// SI: exp mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] +// GFX10: exp mrt0, off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] +// GFX12: export mrt0, off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] +// GFX89: exp mrt0, off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xc4,0x00,0x00,0x00,0x01] +// SI: exp mrt0, off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] exp mrt0 off, off, v2, off done -// GFX10: exp mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] -// GFX12: export mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] -// GFX89: exp mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xc4,0x00,0x00,0x02,0x00] -// SI: exp mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] +// GFX10: exp mrt0, off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] +// GFX12: export mrt0, off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] +// GFX89: exp mrt0, off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xc4,0x00,0x00,0x02,0x00] +// SI: exp mrt0, off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] exp mrt0 off, v3, off, off done -// GFX10: exp mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] -// GFX12: export mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] -// GFX89: exp mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xc4,0x00,0x03,0x00,0x00] -// SI: exp mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] +// GFX10: exp mrt0, off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] +// GFX12: export mrt0, off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] +// GFX89: exp mrt0, off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xc4,0x00,0x03,0x00,0x00] +// SI: exp mrt0, off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] exp mrt0 v4, off, off, off done -// GFX10: exp mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] -// GFX12: export mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] -// GFX89: exp mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xc4,0x04,0x00,0x00,0x00] -// SI: exp mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] +// GFX10: exp mrt0, v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] +// GFX12: export mrt0, v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] +// GFX89: exp mrt0, v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xc4,0x04,0x00,0x00,0x00] +// SI: exp mrt0, v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] exp mrt0 v4, off, off, v1 -// GFX10: exp mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] -// GFX12: export mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] -// GFX89: exp mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xc4,0x04,0x00,0x00,0x01] -// SI: exp mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] +// GFX10: exp mrt0, v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] +// GFX12: export mrt0, v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] +// GFX89: exp mrt0, v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xc4,0x04,0x00,0x00,0x01] +// SI: exp mrt0, v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] exp mrt0 v4, off, off, v1 done -// GFX10: exp mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] -// GFX12: export mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] -// GFX89: exp mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xc4,0x04,0x00,0x00,0x01] -// SI: exp mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] +// GFX10: exp mrt0, v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] +// GFX12: export mrt0, v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] +// GFX89: exp mrt0, v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xc4,0x04,0x00,0x00,0x01] +// SI: exp mrt0, v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] exp mrt0 v4, off, v2, off done -// GFX10: exp mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] -// GFX12: export mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] -// GFX89: exp mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xc4,0x04,0x00,0x02,0x00] -// SI: exp mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] +// GFX10: exp mrt0, v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] +// GFX12: export mrt0, v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] +// GFX89: exp mrt0, v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xc4,0x04,0x00,0x02,0x00] +// SI: exp mrt0, v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] exp mrt0 v4, v3, off, off done -// GFX10: exp mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] -// GFX12: export mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] -// GFX89: exp mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xc4,0x04,0x03,0x00,0x00] -// SI: exp mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] +// GFX10: exp mrt0, v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] +// GFX12: export mrt0, v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] +// GFX89: exp mrt0, v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xc4,0x04,0x03,0x00,0x00] +// SI: exp mrt0, v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] exp mrt0 v4, v3, v2, v1 -// GFX10: exp mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp mrt0, v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export mrt0, v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrt0, v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrt0, v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] exp mrt0 v4, v3, v2, v1 done -// GFX10: exp mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp mrt0, v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export mrt0, v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrt0, v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrt0, v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] + +// Check format with comma between target export and first data +exp mrt0, off, off, off, off +// GFX10: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX89: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// SI: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt7 v1, v1, v1, v1 -// GFX10: exp mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] -// GFX12: export mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] -// GFX89: exp mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xc4,0x01,0x01,0x01,0x01] -// SI: exp mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] +// GFX10: exp mrt7, v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] +// GFX12: export mrt7, v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] +// GFX89: exp mrt7, v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xc4,0x01,0x01,0x01,0x01] +// SI: exp mrt7, v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] exp mrt7 v1, v1, v1, v1 done -// GFX10: exp mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] -// GFX12: export mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] -// GFX89: exp mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xc4,0x01,0x01,0x01,0x01] -// SI: exp mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] +// GFX10: exp mrt7, v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] +// GFX12: export mrt7, v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] +// GFX89: exp mrt7, v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xc4,0x01,0x01,0x01,0x01] +// SI: exp mrt7, v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] exp mrtz v4, v3, v2, v1 -// GFX10: exp mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp mrtz, v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export mrtz, v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrtz, v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrtz, v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] exp mrtz v4, v3, v2, v1 done -// GFX10: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp mrtz, v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export mrtz, v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp mrtz, v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp mrtz, v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] exp pos0 v4, v3, v2, v1 -// GFX10: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp pos0, v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export pos0, v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp pos0, v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp pos0, v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] exp pos0 v4, v3, v2, v1 done -// GFX10: exp pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp pos0, v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export pos0, v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp pos0, v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp pos0, v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] exp pos3 v4, v3, v2, v1 -// GFX10: exp pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp pos3, v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export pos3, v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp pos3, v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp pos3, v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] exp pos3 v4, v3, v2, v1 done -// GFX10: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX12: export pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] -// GFX89: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] -// SI: exp pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX10: exp pos3, v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX12: export pos3, v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] +// GFX89: exp pos3, v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xc4,0x04,0x03,0x02,0x01] +// SI: exp pos3, v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] diff --git a/llvm/test/MC/AMDGPU/gfx10_asm_exp.s b/llvm/test/MC/AMDGPU/gfx10_asm_exp.s index b7e45d18e705..050418df9244 100644 --- a/llvm/test/MC/AMDGPU/gfx10_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx10_asm_exp.s @@ -1,145 +1,146 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -show-encoding %s | FileCheck %s exp mrt0 v0, v0, v0, v0 -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 done -// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 done -// CHECK: exp mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 done -// CHECK: exp null v0, v0, v0, v0 done ; encoding: [0x9f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 done ; encoding: [0x9f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 done -// CHECK: exp pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 done -// CHECK: exp param0 v0, v0, v0, v0 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 done ; encoding: [0x0f,0x0a,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 done -// CHECK: exp prim v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nodone -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 nodone -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 nodone -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 nodone -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 nodone -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 nodone -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 compr -// CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 compr -// CHECK: exp mrtz v0, v0, v0, v0 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 compr ; encoding: [0x8f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 compr -// CHECK: exp null v0, v0, v0, v0 compr ; encoding: [0x9f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 compr ; encoding: [0x9f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 compr -// CHECK: exp pos0 v0, v0, v0, v0 compr ; encoding: [0xcf,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 compr ; encoding: [0xcf,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 compr -// CHECK: exp param0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x06,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x06,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 compr -// CHECK: exp prim v0, v0, v0, v0 compr ; encoding: [0x4f,0x05,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 compr ; encoding: [0x4f,0x05,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nocompr -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 nocompr -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 nocompr -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 nocompr -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 nocompr -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 nocompr -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 vm -// CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 vm -// CHECK: exp mrtz v0, v0, v0, v0 vm ; encoding: [0x8f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 vm ; encoding: [0x8f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 vm -// CHECK: exp null v0, v0, v0, v0 vm ; encoding: [0x9f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 vm ; encoding: [0x9f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 vm -// CHECK: exp pos0 v0, v0, v0, v0 vm ; encoding: [0xcf,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 vm ; encoding: [0xcf,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 vm -// CHECK: exp param0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x12,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x12,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 vm -// CHECK: exp prim v0, v0, v0, v0 vm ; encoding: [0x4f,0x11,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 vm ; encoding: [0x4f,0x11,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 novm -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 novm -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 novm -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 novm -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 novm -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 novm -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s index fcdac8aed13a..a375d4c224ab 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_exp.s @@ -1,79 +1,80 @@ +// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s exp mrt0 v0, v0, v0, v0 done -// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 done -// CHECK: exp mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 done -// CHECK: exp prim v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 done -// CHECK: exp pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp dual_src_blend0 v0, v0, v0, v0 done -// CHECK: exp dual_src_blend0 v0, v0, v0, v0 done ; encoding: [0x5f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp dual_src_blend0, v0, v0, v0, v0 done ; encoding: [0x5f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nodone -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 nodone -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 nodone -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 nodone -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp dual_src_blend0 v0, v0, v0, v0 nodone -// CHECK: exp dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp dual_src_blend0, v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 row_en -// CHECK: exp mrt0 v0, v0, v0, v0 row_en ; encoding: [0x0f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 row_en ; encoding: [0x0f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 row_en -// CHECK: exp mrtz v0, v0, v0, v0 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 row_en -// CHECK: exp prim v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 row_en -// CHECK: exp pos0 v0, v0, v0, v0 row_en ; encoding: [0xcf,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 row_en ; encoding: [0xcf,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] exp dual_src_blend0 v0, v0, v0, v0 row_en -// CHECK: exp dual_src_blend0 v0, v0, v0, v0 row_en ; encoding: [0x5f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp dual_src_blend0, v0, v0, v0, v0 row_en ; encoding: [0x5f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 norow_en -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 norow_en -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 norow_en -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 norow_en -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp dual_src_blend0 v0, v0, v0, v0 norow_en -// CHECK: exp dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp dual_src_blend0, v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nodone norow_en -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 nodone norow_en -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp prim v0, v0, v0, v0 nodone norow_en -// CHECK: exp prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 nodone norow_en -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp dual_src_blend0 v0, v0, v0, v0 nodone norow_en -// CHECK: exp dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp dual_src_blend0, v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_exp.s b/llvm/test/MC/AMDGPU/gfx12_asm_exp.s index 7f3a78ecbef1..e9adc2bfdf0f 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_exp.s @@ -1,142 +1,147 @@ // NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --sort --version 6 // RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck -check-prefix=GFX12 %s -export mrt0 off, off, off, off -// GFX12: export mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrt0 off, off, off, off done -// GFX12: export mrt0 off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrt0 off, off, off, v1 done -// GFX12: export mrt0 off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] - -export mrt0 off, off, v2, off done -// GFX12: export mrt0 off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] - -export mrt0 off, v3, off, off done -// GFX12: export mrt0 off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] - -export mrt0 v4, off, off, off done -// GFX12: export mrt0 v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] - -export mrt0 v4, off, off, v1 -// GFX12: export mrt0 v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] - -export mrt0 v4, off, off, v1 done -// GFX12: export mrt0 v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] - -export mrt0 v4, off, v2, off done -// GFX12: export mrt0 v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] - -export mrt0 v4, v3, off, off done -// GFX12: export mrt0 v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] - -export mrt0 v4, v3, v2, v1 -// GFX12: export mrt0 v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] - -export mrt0 v4, v3, v2, v1 done -// GFX12: export mrt0 v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] - -export mrt7 v1, v1, v1, v1 -// GFX12: export mrt7 v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] - -export mrt7 v1, v1, v1, v1 done -// GFX12: export mrt7 v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] - -export mrtz v4, v3, v2, v1 -// GFX12: export mrtz v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] - -export mrtz v4, v3, v2, v1 done -// GFX12: export mrtz v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] - -export pos0 v4, v3, v2, v1 -// GFX12: export pos0 v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] - -export pos0 v4, v3, v2, v1 done -// GFX12: export pos0 v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] - -export pos3 v4, v3, v2, v1 -// GFX12: export pos3 v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] - -export pos3 v4, v3, v2, v1 done -// GFX12: export pos3 v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] - // Optional operands: done and row_en -export mrt0 v0, v0, v0, v0 done -// GFX12: export mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrtz v0, v0, v0, v0 done -// GFX12: export mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] - -export prim v0, v0, v0, v0 done -// GFX12: export prim v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] - -export pos0 v0, v0, v0, v0 done -// GFX12: export pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] - export dual_src_blend0 v0, v0, v0, v0 done -// GFX12: export dual_src_blend0 v0, v0, v0, v0 done ; encoding: [0x5f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export dual_src_blend0, v0, v0, v0, v0 done ; encoding: [0x5f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 nodone +// GFX12: export dual_src_blend0, v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 nodone norow_en +// GFX12: export dual_src_blend0, v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 norow_en +// GFX12: export dual_src_blend0, v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export dual_src_blend0 v0, v0, v0, v0 row_en +// GFX12: export dual_src_blend0, v0, v0, v0, v0 row_en ; encoding: [0x5f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrt0 off, off, off, off +// GFX12: export mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrt0 off, off, off, off done +// GFX12: export mrt0, off, off, off, off done ; encoding: [0x00,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrt0 off, off, off, v1 done +// GFX12: export mrt0, off, off, off, v1 done ; encoding: [0x08,0x08,0x00,0xf8,0x00,0x00,0x00,0x01] + +export mrt0 off, off, v2, off done +// GFX12: export mrt0, off, off, v2, off done ; encoding: [0x04,0x08,0x00,0xf8,0x00,0x00,0x02,0x00] + +export mrt0 off, v3, off, off done +// GFX12: export mrt0, off, v3, off, off done ; encoding: [0x02,0x08,0x00,0xf8,0x00,0x03,0x00,0x00] + +export mrt0 v0, v0, v0, v0 done +// GFX12: export mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] export mrt0 v0, v0, v0, v0 nodone -// GFX12: export mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrtz v0, v0, v0, v0 nodone -// GFX12: export mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export prim v0, v0, v0, v0 nodone -// GFX12: export prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] - -export pos0 v0, v0, v0, v0 nodone -// GFX12: export pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export dual_src_blend0 v0, v0, v0, v0 nodone -// GFX12: export dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] - - -export mrt0 v0, v0, v0, v0 row_en -// GFX12: export mrt0 v0, v0, v0, v0 row_en ; encoding: [0x0f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrtz v0, v0, v0, v0 row_en -// GFX12: export mrtz v0, v0, v0, v0 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] - -export prim v0, v0, v0, v0 row_en -// GFX12: export prim v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] - -export pos0 v0, v0, v0, v0 row_en -// GFX12: export pos0 v0, v0, v0, v0 row_en ; encoding: [0xcf,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] - -export dual_src_blend0 v0, v0, v0, v0 row_en -// GFX12: export dual_src_blend0 v0, v0, v0, v0 row_en ; encoding: [0x5f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrt0 v0, v0, v0, v0 norow_en -// GFX12: export mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export mrtz v0, v0, v0, v0 norow_en -// GFX12: export mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export prim v0, v0, v0, v0 norow_en -// GFX12: export prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] - -export pos0 v0, v0, v0, v0 norow_en -// GFX12: export pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] - -export dual_src_blend0 v0, v0, v0, v0 norow_en -// GFX12: export dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] export mrt0 v0, v0, v0, v0 nodone norow_en -// GFX12: export mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrt0 v0, v0, v0, v0 norow_en +// GFX12: export mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + + +export mrt0 v0, v0, v0, v0 row_en +// GFX12: export mrt0, v0, v0, v0, v0 row_en ; encoding: [0x0f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrt0 v4, off, off, off done +// GFX12: export mrt0, v4, off, off, off done ; encoding: [0x01,0x08,0x00,0xf8,0x04,0x00,0x00,0x00] + +export mrt0 v4, off, off, v1 +// GFX12: export mrt0, v4, off, off, v1 ; encoding: [0x09,0x00,0x00,0xf8,0x04,0x00,0x00,0x01] + +export mrt0 v4, off, off, v1 done +// GFX12: export mrt0, v4, off, off, v1 done ; encoding: [0x09,0x08,0x00,0xf8,0x04,0x00,0x00,0x01] + +export mrt0 v4, off, v2, off done +// GFX12: export mrt0, v4, off, v2, off done ; encoding: [0x05,0x08,0x00,0xf8,0x04,0x00,0x02,0x00] + +export mrt0 v4, v3, off, off done +// GFX12: export mrt0, v4, v3, off, off done ; encoding: [0x03,0x08,0x00,0xf8,0x04,0x03,0x00,0x00] + +export mrt0 v4, v3, v2, v1 +// GFX12: export mrt0, v4, v3, v2, v1 ; encoding: [0x0f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] + +export mrt0 v4, v3, v2, v1 done +// GFX12: export mrt0, v4, v3, v2, v1 done ; encoding: [0x0f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] + +export mrt7 v1, v1, v1, v1 +// GFX12: export mrt7, v1, v1, v1, v1 ; encoding: [0x7f,0x00,0x00,0xf8,0x01,0x01,0x01,0x01] + +export mrt7 v1, v1, v1, v1 done +// GFX12: export mrt7, v1, v1, v1, v1 done ; encoding: [0x7f,0x08,0x00,0xf8,0x01,0x01,0x01,0x01] + +export mrtz v0, v0, v0, v0 done +// GFX12: export mrtz, v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 nodone +// GFX12: export mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] export mrtz v0, v0, v0, v0 nodone norow_en -// GFX12: export mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] -export prim v0, v0, v0, v0 nodone norow_en -// GFX12: export prim v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +export mrtz v0, v0, v0, v0 norow_en +// GFX12: export mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v0, v0, v0, v0 row_en +// GFX12: export mrtz, v0, v0, v0, v0 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +export mrtz v4, v3, v2, v1 +// GFX12: export mrtz, v4, v3, v2, v1 ; encoding: [0x8f,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] + +export mrtz v4, v3, v2, v1 done +// GFX12: export mrtz, v4, v3, v2, v1 done ; encoding: [0x8f,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] + +export pos0 v0, v0, v0, v0 done +// GFX12: export pos0, v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 nodone +// GFX12: export pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] export pos0 v0, v0, v0, v0 nodone norow_en -// GFX12: export pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// GFX12: export pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] -export dual_src_blend0 v0, v0, v0, v0 nodone norow_en -// GFX12: export dual_src_blend0 v0, v0, v0, v0 ; encoding: [0x5f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] +export pos0 v0, v0, v0, v0 norow_en +// GFX12: export pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v0, v0, v0, v0 row_en +// GFX12: export pos0, v0, v0, v0, v0 row_en ; encoding: [0xcf,0x20,0x00,0xf8,0x00,0x00,0x00,0x00] + +export pos0 v4, v3, v2, v1 +// GFX12: export pos0, v4, v3, v2, v1 ; encoding: [0xcf,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] + +export pos0 v4, v3, v2, v1 done +// GFX12: export pos0, v4, v3, v2, v1 done ; encoding: [0xcf,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] + +export pos3 v4, v3, v2, v1 +// GFX12: export pos3, v4, v3, v2, v1 ; encoding: [0xff,0x00,0x00,0xf8,0x04,0x03,0x02,0x01] + +export pos3 v4, v3, v2, v1 done +// GFX12: export pos3, v4, v3, v2, v1 done ; encoding: [0xff,0x08,0x00,0xf8,0x04,0x03,0x02,0x01] + +export prim v0, v0, v0, v0 done +// GFX12: export prim, v0, v0, v0, v0 done ; encoding: [0x4f,0x09,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 nodone +// GFX12: export prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 nodone norow_en +// GFX12: export prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +export prim v0, v0, v0, v0 norow_en +// GFX12: export prim, v0, v0, v0, v0 ; encoding: [0x4f,0x01,0x00,0xf8,0x00,0x00,0x00,0x00] + +// Check format without comma between target export and first data +export prim v0, v0, v0, v0 row_en +// GFX12: export prim, v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] + +// Check format with comma between target export and first data +export prim, v0, v0, v0, v0 row_en +// GFX12: export prim, v0, v0, v0, v0 row_en ; encoding: [0x4f,0x21,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx7_asm_exp.s b/llvm/test/MC/AMDGPU/gfx7_asm_exp.s index c8edcd7f5e9d..cfb6d3a35177 100644 --- a/llvm/test/MC/AMDGPU/gfx7_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx7_asm_exp.s @@ -2,82 +2,82 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s exp mrt0 off, off, off, off -// CHECK: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, off, off, v0 -// CHECK: exp mrt0 off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, off, v0, off -// CHECK: exp mrt0 off, off, v0, off ; encoding: [0x04,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, v0, off ; encoding: [0x04,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, off, v0, v0 -// CHECK: exp mrt0 off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, v0, off, off -// CHECK: exp mrt0 off, v0, off, off ; encoding: [0x02,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, off, off ; encoding: [0x02,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, v0, off, v0 -// CHECK: exp mrt0 off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, v0, v0, off -// CHECK: exp mrt0 off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 off, v0, v0, v0 -// CHECK: exp mrt0 off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, off, off, off -// CHECK: exp mrt0 v0, off, off, off ; encoding: [0x01,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, off, off ; encoding: [0x01,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, off, off, v0 -// CHECK: exp mrt0 v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, off, v0, off -// CHECK: exp mrt0 v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, off, v0, v0 -// CHECK: exp mrt0 v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, off, off -// CHECK: exp mrt0 v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, off, v0 -// CHECK: exp mrt0 v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, off -// CHECK: exp mrt0 v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 compr -// CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 done -// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 vm -// CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v255 -// CHECK: exp mrt0 v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0xff] +// CHECK: exp mrt0, v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0x00,0xff] exp mrt0 v0, v0, v255, v0 -// CHECK: exp mrt0 v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0xff,0x00] +// CHECK: exp mrt0, v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0x00,0xff,0x00] exp mrt0 v0, v255, v0, v0 -// CHECK: exp mrt0 v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0xff,0x00,0x00] +// CHECK: exp mrt0, v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0x00,0xff,0x00,0x00] exp mrt0 v255, v0, v0, v0 -// CHECK: exp mrt0 v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0xff,0x00,0x00,0x00] +// CHECK: exp mrt0, v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xf8,0xff,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xf8,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xf8,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx8_asm_exp.s b/llvm/test/MC/AMDGPU/gfx8_asm_exp.s index a146e312c3cc..7e5e1aed9203 100644 --- a/llvm/test/MC/AMDGPU/gfx8_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx8_asm_exp.s @@ -2,82 +2,82 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s exp mrt0 off, off, off, off -// CHECK: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, off, off, v0 -// CHECK: exp mrt0 off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, off, v0, off -// CHECK: exp mrt0 off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, off, v0, v0 -// CHECK: exp mrt0 off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, off, off -// CHECK: exp mrt0 off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, off, v0 -// CHECK: exp mrt0 off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, v0, off -// CHECK: exp mrt0 off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, v0, v0 -// CHECK: exp mrt0 off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, off, off -// CHECK: exp mrt0 v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, off, v0 -// CHECK: exp mrt0 v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, v0, off -// CHECK: exp mrt0 v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, v0, v0 -// CHECK: exp mrt0 v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, off, off -// CHECK: exp mrt0 v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, off, v0 -// CHECK: exp mrt0 v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, off -// CHECK: exp mrt0 v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 compr -// CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 done -// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 vm -// CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v255 -// CHECK: exp mrt0 v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] +// CHECK: exp mrt0, v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] exp mrt0 v0, v0, v255, v0 -// CHECK: exp mrt0 v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] +// CHECK: exp mrt0, v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] exp mrt0 v0, v255, v0, v0 -// CHECK: exp mrt0 v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] +// CHECK: exp mrt0, v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] exp mrt0 v255, v0, v0, v0 -// CHECK: exp mrt0 v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] +// CHECK: exp mrt0, v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] exp pos0 v0, v0, v0, v0 -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s index a8a961bd7fae..3f8bf3e13f7b 100644 --- a/llvm/test/MC/AMDGPU/gfx9_asm_exp.s +++ b/llvm/test/MC/AMDGPU/gfx9_asm_exp.s @@ -2,184 +2,184 @@ // RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s exp mrt0 off, off, off, off -// CHECK: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, off, off, v0 -// CHECK: exp mrt0 off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, off, v0, off -// CHECK: exp mrt0 off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, off, v0, v0 -// CHECK: exp mrt0 off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, off, off -// CHECK: exp mrt0 off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, off, v0 -// CHECK: exp mrt0 off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, v0, off -// CHECK: exp mrt0 off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 off, v0, v0, v0 -// CHECK: exp mrt0 off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, off, off -// CHECK: exp mrt0 v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, off, v0 -// CHECK: exp mrt0 v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, v0, off -// CHECK: exp mrt0 v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, off, v0, v0 -// CHECK: exp mrt0 v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, off, off -// CHECK: exp mrt0 v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, off, v0 -// CHECK: exp mrt0 v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, off -// CHECK: exp mrt0 v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 compr -// CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 done -// CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] -exp mrt0 v0, v0, v0, v0 vm -// CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrt0 v0, v0, v0, v255 -// CHECK: exp mrt0 v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] - -exp mrt0 v0, v0, v255, v0 -// CHECK: exp mrt0 v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] - -exp mrt0 v0, v255, v0, v0 -// CHECK: exp mrt0 v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] - -exp mrt0 v255, v0, v0, v0 -// CHECK: exp mrt0 v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] - -exp mrtz v0, v0, v0, v0 -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp null v0, v0, v0, v0 -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp param0 v0, v0, v0, v0 -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp pos0 v0, v0, v0, v0 -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +exp mrt0 v0, v0, v0, v0 nocompr +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nodone -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrt0 v0, v0, v0, v0 nocompr -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrt0 v0, v0, v0, v0 novm -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - - -exp mrtz v0, v0, v0, v0 done -// CHECK: exp mrtz v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrtz v0, v0, v0, v0 nodone -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrtz v0, v0, v0, v0 compr -// CHECK: exp mrtz v0, v0, v0, v0 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrtz v0, v0, v0, v0 nocompr -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrtz v0, v0, v0, v0 vm -// CHECK: exp mrtz v0, v0, v0, v0 vm ; encoding: [0x8f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp mrtz v0, v0, v0, v0 novm -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - - -exp null v0, v0, v0, v0 done -// CHECK: exp null v0, v0, v0, v0 done ; encoding: [0x9f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp null v0, v0, v0, v0 nodone -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp null v0, v0, v0, v0 compr -// CHECK: exp null v0, v0, v0, v0 compr ; encoding: [0x9f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp null v0, v0, v0, v0 nocompr -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp null v0, v0, v0, v0 vm -// CHECK: exp null v0, v0, v0, v0 vm ; encoding: [0x9f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp null v0, v0, v0, v0 novm -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - - -exp pos0 v0, v0, v0, v0 done -// CHECK: exp pos0 v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp pos0 v0, v0, v0, v0 nodone -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp pos0 v0, v0, v0, v0 compr -// CHECK: exp pos0 v0, v0, v0, v0 compr ; encoding: [0xcf,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp pos0 v0, v0, v0, v0 nocompr -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp pos0 v0, v0, v0, v0 vm -// CHECK: exp pos0 v0, v0, v0, v0 vm ; encoding: [0xcf,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp pos0 v0, v0, v0, v0 novm -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] - - -exp param0 v0, v0, v0, v0 done -// CHECK: exp param0 v0, v0, v0, v0 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp param0 v0, v0, v0, v0 nodone -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp param0 v0, v0, v0, v0 compr -// CHECK: exp param0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x06,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp param0 v0, v0, v0, v0 nocompr -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp param0 v0, v0, v0, v0 vm -// CHECK: exp param0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x12,0x00,0xc4,0x00,0x00,0x00,0x00] - -exp param0 v0, v0, v0, v0 novm -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrt0 v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 novm +// CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v0 vm +// CHECK: exp mrt0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrt0 v0, v0, v0, v255 +// CHECK: exp mrt0, v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] + +exp mrt0 v0, v0, v255, v0 +// CHECK: exp mrt0, v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] + +exp mrt0 v0, v255, v0, v0 +// CHECK: exp mrt0, v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] + +exp mrt0 v255, v0, v0, v0 +// CHECK: exp mrt0, v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 compr +// CHECK: exp mrtz, v0, v0, v0, v0 compr ; encoding: [0x8f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp mrtz v0, v0, v0, v0 done +// CHECK: exp mrtz, v0, v0, v0, v0 done ; encoding: [0x8f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nocompr +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 nodone +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp mrtz v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 novm +// CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp mrtz v0, v0, v0, v0 vm +// CHECK: exp mrtz, v0, v0, v0, v0 vm ; encoding: [0x8f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 compr +// CHECK: exp null, v0, v0, v0, v0 compr ; encoding: [0x9f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp null v0, v0, v0, v0 done +// CHECK: exp null, v0, v0, v0, v0 done ; encoding: [0x9f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nocompr +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 nodone +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] exp null v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] -exp pos0 v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +exp null v0, v0, v0, v0 novm +// CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp null v0, v0, v0, v0 vm +// CHECK: exp null, v0, v0, v0, v0 vm ; encoding: [0x9f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 compr +// CHECK: exp param0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x06,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp param0 v0, v0, v0, v0 done +// CHECK: exp param0, v0, v0, v0, v0 done ; encoding: [0x0f,0x0a,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nocompr +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 nodone +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] exp param0 v0, v0, v0, v0 nodone nocompr novm -// CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 novm +// CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp param0 v0, v0, v0, v0 vm +// CHECK: exp param0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x12,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 compr +// CHECK: exp pos0, v0, v0, v0, v0 compr ; encoding: [0xcf,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] + + +exp pos0 v0, v0, v0, v0 done +// CHECK: exp pos0, v0, v0, v0, v0 done ; encoding: [0xcf,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nocompr +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 nodone nocompr novm +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 novm +// CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] + +exp pos0 v0, v0, v0, v0 vm +// CHECK: exp pos0, v0, v0, v0, v0 vm ; encoding: [0xcf,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt index 42d696f83053..04f8558a72a6 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_exp.txt @@ -2,49 +2,49 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX10 0x0c,0x00,0x00,0xf8,0x00,0x00,0x01,0x02 -# GFX10: exp mrt0 off, off, v1, v2 ; encoding: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x01,0x02] +# GFX10: exp mrt0, off, off, v1, v2 ; encoding: [0x0c,0x00,0x00,0xf8,0x00,0x00,0x01,0x02] 0x0c,0x0c,0x00,0xf8,0x00,0x08,0x00,0x00 -# GFX10: exp mrt0 off, off, v8, v8 done compr ; encoding: [0x0c,0x0c,0x00,0xf8,0x00,0x08,0x00,0x00] +# GFX10: exp mrt0, off, off, v8, v8 done compr ; encoding: [0x0c,0x0c,0x00,0xf8,0x00,0x08,0x00,0x00] 0x03,0x04,0x00,0xf8,0x01,0x00,0x00,0x00 -# GFX10: exp mrt0 v1, v1, off, off compr ; encoding: [0x03,0x04,0x00,0xf8,0x01,0x00,0x00,0x00] +# GFX10: exp mrt0, v1, v1, off, off compr ; encoding: [0x03,0x04,0x00,0xf8,0x01,0x00,0x00,0x00] 0x0f,0x04,0x00,0xf8,0x01,0x03,0x00,0x00 -# GFX10: exp mrt0 v1, v1, v3, v3 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x01,0x03,0x00,0x00] +# GFX10: exp mrt0, v1, v1, v3, v3 compr ; encoding: [0x0f,0x04,0x00,0xf8,0x01,0x03,0x00,0x00] 0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04 -# GFX10: exp mrt0 v1, v2, v3, v4 ; encoding: [0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04] +# GFX10: exp mrt0, v1, v2, v3, v4 ; encoding: [0x0f,0x00,0x00,0xf8,0x01,0x02,0x03,0x04] 0x0f,0x08,0x00,0xf8,0x01,0x02,0x03,0x04 -# GFX10: exp mrt0 v1, v2, v3, v4 done ; encoding: [0x0f,0x08,0x00,0xf8,0x01,0x02,0x03,0x04] +# GFX10: exp mrt0, v1, v2, v3, v4 done ; encoding: [0x0f,0x08,0x00,0xf8,0x01,0x02,0x03,0x04] 0x0f,0x10,0x00,0xf8,0x01,0x02,0x03,0x04 -# GFX10: exp mrt0 v1, v2, v3, v4 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x01,0x02,0x03,0x04] +# GFX10: exp mrt0, v1, v2, v3, v4 vm ; encoding: [0x0f,0x10,0x00,0xf8,0x01,0x02,0x03,0x04] 0x0f,0x1c,0x00,0xf8,0x02,0x04,0x00,0x00 -# GFX10: exp mrt0 v2, v2, v4, v4 done compr vm ; encoding: [0x0f,0x1c,0x00,0xf8,0x02,0x04,0x00,0x00] +# GFX10: exp mrt0, v2, v2, v4, v4 done compr vm ; encoding: [0x0f,0x1c,0x00,0xf8,0x02,0x04,0x00,0x00] 0x01,0x10,0x00,0xf8,0x07,0x00,0x00,0x00 -# GFX10: exp mrt0 v7, off, off, off vm ; encoding: [0x01,0x10,0x00,0xf8,0x07,0x00,0x00,0x00] +# GFX10: exp mrt0, v7, off, off, off vm ; encoding: [0x01,0x10,0x00,0xf8,0x07,0x00,0x00,0x00] 0x81,0x18,0x00,0xf8,0x00,0x00,0x00,0x00 -# GFX10: exp mrtz v0, off, off, off done vm ; encoding: [0x81,0x18,0x00,0xf8,0x00,0x00,0x00,0x00] +# GFX10: exp mrtz, v0, off, off, off done vm ; encoding: [0x81,0x18,0x00,0xf8,0x00,0x00,0x00,0x00] 0x9f,0x00,0x00,0xf8,0xff,0x00,0xff,0x00 -# GFX10: exp null v255, v0, v255, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0xff,0x00,0xff,0x00] +# GFX10: exp null, v255, v0, v255, v0 ; encoding: [0x9f,0x00,0x00,0xf8,0xff,0x00,0xff,0x00] 0x00,0x06,0x00,0xf8,0x00,0x00,0x00,0x00 -# GFX10: exp param0 off, off, off, off compr ; encoding: [0x00,0x06,0x00,0xf8,0x00,0x00,0x00,0x00] +# GFX10: exp param0, off, off, off, off compr ; encoding: [0x00,0x06,0x00,0xf8,0x00,0x00,0x00,0x00] 0xc1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00 -# GFX10: exp pos0 v1, off, off, off ; encoding: [0xc1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00] +# GFX10: exp pos0, v1, off, off, off ; encoding: [0xc1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00] 0xf1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00 -# GFX10: exp pos3 v1, off, off, off ; encoding: [0xf1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00] +# GFX10: exp pos3, v1, off, off, off ; encoding: [0xf1,0x00,0x00,0xf8,0x01,0x00,0x00,0x00] 0x01,0x01,0x00,0xf8,0x01,0x00,0x00,0x00 -# GFX10: exp pos4 v1, off, off, off ; encoding: [0x01,0x01,0x00,0xf8,0x01,0x00,0x00,0x00] +# GFX10: exp pos4, v1, off, off, off ; encoding: [0x01,0x01,0x00,0xf8,0x01,0x00,0x00,0x00] 0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00 -# GFX10: exp prim v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +# GFX10: exp prim, v2, v3, off, off ; encoding: [0x43,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt index 84ee181bd402..4cd61dc6fffe 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_exp.txt @@ -2,13 +2,13 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s -check-prefix=GFX11 0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01 -# GFX11: exp dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] +# GFX11: exp dual_src_blend0, v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] 0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00 -# GFX11: exp dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +# GFX11: exp dual_src_blend1, v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] 0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00 -# GFX11: exp mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] +# GFX11: exp mrtz, v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] 0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01 -# GFX11: exp mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] +# GFX11: exp mrtz, v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_exp.txt index eb8ec6a9310d..c4e74f807e2c 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_exp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_exp.txt @@ -2,13 +2,13 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX12 0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01 -# GFX12: export dual_src_blend0 v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] +# GFX12: export dual_src_blend0, v4, v3, v2, v1 ; encoding: [0x5f,0x01,0x00,0xf8,0x04,0x03,0x02,0x01] 0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00 -# GFX12: export dual_src_blend1 v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] +# GFX12: export dual_src_blend1, v2, v3, off, off ; encoding: [0x63,0x01,0x00,0xf8,0x02,0x03,0x00,0x00] 0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00 -# GFX12: export mrtz v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] +# GFX12: export mrtz, v4, v3, off, off done row_en ; encoding: [0x83,0x28,0x00,0xf8,0x04,0x03,0x00,0x00] 0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01 -# GFX12: export mrtz v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] +# GFX12: export mrtz, v4, v3, v2, v1 row_en ; encoding: [0x8f,0x20,0x00,0xf8,0x04,0x03,0x02,0x01] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt index d2f93f28ecfa..7ea3b185bbd2 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx8_exp.txt @@ -2,82 +2,82 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s 0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff -# CHECK: exp mrt0 v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] +# CHECK: exp mrt0, v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] 0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00 -# CHECK: exp mrt0 v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] +# CHECK: exp mrt0, v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] 0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00 -# CHECK: exp mrt0 v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] +# CHECK: exp mrt0, v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] 0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00 -# CHECK: exp mrt0 v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] +# CHECK: exp mrt0, v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] 0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] 0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt index 2935be865fbd..3b6633e303c8 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_exp.txt @@ -2,82 +2,82 @@ # RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck -strict-whitespace %s 0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, off, off ; encoding: [0x00,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, off, v0 ; encoding: [0x08,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, v0, off ; encoding: [0x04,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, off, v0, v0 ; encoding: [0x0c,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, off, off ; encoding: [0x02,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, off, v0 ; encoding: [0x0a,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, v0, off ; encoding: [0x06,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, off, v0, v0, v0 ; encoding: [0x0e,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, off, off ; encoding: [0x01,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, off, v0 ; encoding: [0x09,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, v0, off ; encoding: [0x05,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, off, v0, v0 ; encoding: [0x0d,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, off, off ; encoding: [0x03,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, off, v0 ; encoding: [0x0b,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, off ; encoding: [0x07,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 compr ; encoding: [0x0f,0x04,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 done ; encoding: [0x0f,0x08,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrt0 v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrt0, v0, v0, v0, v0 vm ; encoding: [0x0f,0x10,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff -# CHECK: exp mrt0 v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] +# CHECK: exp mrt0, v0, v0, v0, v255 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0x00,0xff] 0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00 -# CHECK: exp mrt0 v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] +# CHECK: exp mrt0, v0, v0, v255, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0x00,0xff,0x00] 0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00 -# CHECK: exp mrt0 v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] +# CHECK: exp mrt0, v0, v255, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0x00,0xff,0x00,0x00] 0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00 -# CHECK: exp mrt0 v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] +# CHECK: exp mrt0, v255, v0, v0, v0 ; encoding: [0x0f,0x00,0x00,0xc4,0xff,0x00,0x00,0x00] 0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp mrtz v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp mrtz, v0, v0, v0, v0 ; encoding: [0x8f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp null v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp null, v0, v0, v0, v0 ; encoding: [0x9f,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] 0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp param0 v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp param0, v0, v0, v0, v0 ; encoding: [0x0f,0x02,0x00,0xc4,0x00,0x00,0x00,0x00] 0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00 -# CHECK: exp pos0 v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00] +# CHECK: exp pos0, v0, v0, v0, v0 ; encoding: [0xcf,0x00,0x00,0xc4,0x00,0x00,0x00,0x00]