AtomicExpand: Refactor atomic instruction handling (#102914)
Move the processing of an instruction into a helper function. Also avoid redundant checking for all types of atomic instructions. Including the assert, it was effectively performing the same check 3 times.
This commit is contained in:
Matt Arsenault
GitHub
parent
55323ca6c8
commit
2d7a2c1212
@ -119,6 +119,8 @@ private:
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llvm::expandAtomicRMWToCmpXchg(AtomicRMWInst *AI,
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CreateCmpXchgInstFun CreateCmpXchg);
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bool processAtomicInstr(Instruction *I);
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public:
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bool run(Function &F, const TargetMachine *TM);
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};
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@ -203,6 +205,143 @@ static bool atomicSizeSupported(const TargetLowering *TLI, Inst *I) {
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Size <= TLI->getMaxAtomicSizeInBitsSupported() / 8;
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}
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bool AtomicExpandImpl::processAtomicInstr(Instruction *I) {
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auto *LI = dyn_cast<LoadInst>(I);
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auto *SI = dyn_cast<StoreInst>(I);
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auto *RMWI = dyn_cast<AtomicRMWInst>(I);
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auto *CASI = dyn_cast<AtomicCmpXchgInst>(I);
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bool MadeChange = false;
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// If the Size/Alignment is not supported, replace with a libcall.
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if (LI) {
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if (!LI->isAtomic())
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return false;
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if (!atomicSizeSupported(TLI, LI)) {
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expandAtomicLoadToLibcall(LI);
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return true;
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}
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if (TLI->shouldCastAtomicLoadInIR(LI) ==
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TargetLoweringBase::AtomicExpansionKind::CastToInteger) {
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I = LI = convertAtomicLoadToIntegerType(LI);
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MadeChange = true;
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}
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} else if (SI) {
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if (!SI->isAtomic())
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return false;
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if (!atomicSizeSupported(TLI, SI)) {
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expandAtomicStoreToLibcall(SI);
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return true;
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}
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if (TLI->shouldCastAtomicStoreInIR(SI) ==
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TargetLoweringBase::AtomicExpansionKind::CastToInteger) {
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I = SI = convertAtomicStoreToIntegerType(SI);
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MadeChange = true;
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}
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} else if (RMWI) {
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if (!atomicSizeSupported(TLI, RMWI)) {
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expandAtomicRMWToLibcall(RMWI);
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return true;
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}
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if (TLI->shouldCastAtomicRMWIInIR(RMWI) ==
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TargetLoweringBase::AtomicExpansionKind::CastToInteger) {
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I = RMWI = convertAtomicXchgToIntegerType(RMWI);
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MadeChange = true;
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}
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} else if (CASI) {
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if (!atomicSizeSupported(TLI, CASI)) {
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expandAtomicCASToLibcall(CASI);
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return true;
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}
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// TODO: when we're ready to make the change at the IR level, we can
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// extend convertCmpXchgToInteger for floating point too.
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if (CASI->getCompareOperand()->getType()->isPointerTy()) {
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// TODO: add a TLI hook to control this so that each target can
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// convert to lowering the original type one at a time.
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I = CASI = convertCmpXchgToIntegerType(CASI);
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MadeChange = true;
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}
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} else
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return false;
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if (TLI->shouldInsertFencesForAtomic(I)) {
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auto FenceOrdering = AtomicOrdering::Monotonic;
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if (LI && isAcquireOrStronger(LI->getOrdering())) {
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FenceOrdering = LI->getOrdering();
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LI->setOrdering(AtomicOrdering::Monotonic);
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} else if (SI && isReleaseOrStronger(SI->getOrdering())) {
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FenceOrdering = SI->getOrdering();
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SI->setOrdering(AtomicOrdering::Monotonic);
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} else if (RMWI && (isReleaseOrStronger(RMWI->getOrdering()) ||
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isAcquireOrStronger(RMWI->getOrdering()))) {
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FenceOrdering = RMWI->getOrdering();
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RMWI->setOrdering(AtomicOrdering::Monotonic);
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} else if (CASI &&
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TLI->shouldExpandAtomicCmpXchgInIR(CASI) ==
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TargetLoweringBase::AtomicExpansionKind::None &&
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(isReleaseOrStronger(CASI->getSuccessOrdering()) ||
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isAcquireOrStronger(CASI->getSuccessOrdering()) ||
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isAcquireOrStronger(CASI->getFailureOrdering()))) {
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// If a compare and swap is lowered to LL/SC, we can do smarter fence
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// insertion, with a stronger one on the success path than on the
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// failure path. As a result, fence insertion is directly done by
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// expandAtomicCmpXchg in that case.
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FenceOrdering = CASI->getMergedOrdering();
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CASI->setSuccessOrdering(AtomicOrdering::Monotonic);
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CASI->setFailureOrdering(AtomicOrdering::Monotonic);
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}
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if (FenceOrdering != AtomicOrdering::Monotonic) {
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MadeChange |= bracketInstWithFences(I, FenceOrdering);
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}
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} else if (I->hasAtomicStore() &&
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TLI->shouldInsertTrailingFenceForAtomicStore(I)) {
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auto FenceOrdering = AtomicOrdering::Monotonic;
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if (SI)
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FenceOrdering = SI->getOrdering();
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else if (RMWI)
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FenceOrdering = RMWI->getOrdering();
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else if (CASI && TLI->shouldExpandAtomicCmpXchgInIR(CASI) !=
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TargetLoweringBase::AtomicExpansionKind::LLSC)
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// LLSC is handled in expandAtomicCmpXchg().
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FenceOrdering = CASI->getSuccessOrdering();
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IRBuilder Builder(I);
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if (auto TrailingFence =
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TLI->emitTrailingFence(Builder, I, FenceOrdering)) {
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TrailingFence->moveAfter(I);
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MadeChange = true;
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}
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}
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if (LI)
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MadeChange |= tryExpandAtomicLoad(LI);
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else if (SI)
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MadeChange |= tryExpandAtomicStore(SI);
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else if (RMWI) {
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// There are two different ways of expanding RMW instructions:
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// - into a load if it is idempotent
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// - into a Cmpxchg/LL-SC loop otherwise
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// we try them in that order.
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if (isIdempotentRMW(RMWI) && simplifyIdempotentRMW(RMWI)) {
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MadeChange = true;
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} else {
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MadeChange |= tryExpandAtomicRMW(RMWI);
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}
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} else if (CASI)
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MadeChange |= tryExpandAtomicCmpXchg(CASI);
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return MadeChange;
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}
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bool AtomicExpandImpl::run(Function &F, const TargetMachine *TM) {
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const auto *Subtarget = TM->getSubtargetImpl(F);
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if (!Subtarget->enableAtomicExpand())
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@ -210,6 +349,8 @@ bool AtomicExpandImpl::run(Function &F, const TargetMachine *TM) {
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TLI = Subtarget->getTargetLowering();
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DL = &F.getDataLayout();
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bool MadeChange = false;
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SmallVector<Instruction *, 1> AtomicInsts;
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// Changing control-flow while iterating through it is a bad idea, so gather a
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@ -218,134 +359,11 @@ bool AtomicExpandImpl::run(Function &F, const TargetMachine *TM) {
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if (I.isAtomic() && !isa<FenceInst>(&I))
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AtomicInsts.push_back(&I);
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bool MadeChange = false;
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for (auto *I : AtomicInsts) {
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auto LI = dyn_cast<LoadInst>(I);
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auto SI = dyn_cast<StoreInst>(I);
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auto RMWI = dyn_cast<AtomicRMWInst>(I);
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auto CASI = dyn_cast<AtomicCmpXchgInst>(I);
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assert((LI || SI || RMWI || CASI) && "Unknown atomic instruction");
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// If the Size/Alignment is not supported, replace with a libcall.
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if (LI) {
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if (!atomicSizeSupported(TLI, LI)) {
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expandAtomicLoadToLibcall(LI);
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MadeChange = true;
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continue;
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}
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} else if (SI) {
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if (!atomicSizeSupported(TLI, SI)) {
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expandAtomicStoreToLibcall(SI);
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MadeChange = true;
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continue;
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}
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} else if (RMWI) {
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if (!atomicSizeSupported(TLI, RMWI)) {
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expandAtomicRMWToLibcall(RMWI);
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MadeChange = true;
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continue;
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}
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} else if (CASI) {
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if (!atomicSizeSupported(TLI, CASI)) {
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expandAtomicCASToLibcall(CASI);
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MadeChange = true;
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continue;
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}
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}
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if (LI && TLI->shouldCastAtomicLoadInIR(LI) ==
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TargetLoweringBase::AtomicExpansionKind::CastToInteger) {
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I = LI = convertAtomicLoadToIntegerType(LI);
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if (processAtomicInstr(I))
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MadeChange = true;
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} else if (SI &&
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TLI->shouldCastAtomicStoreInIR(SI) ==
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TargetLoweringBase::AtomicExpansionKind::CastToInteger) {
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I = SI = convertAtomicStoreToIntegerType(SI);
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MadeChange = true;
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} else if (RMWI &&
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TLI->shouldCastAtomicRMWIInIR(RMWI) ==
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TargetLoweringBase::AtomicExpansionKind::CastToInteger) {
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I = RMWI = convertAtomicXchgToIntegerType(RMWI);
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MadeChange = true;
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} else if (CASI) {
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// TODO: when we're ready to make the change at the IR level, we can
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// extend convertCmpXchgToInteger for floating point too.
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if (CASI->getCompareOperand()->getType()->isPointerTy()) {
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// TODO: add a TLI hook to control this so that each target can
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// convert to lowering the original type one at a time.
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I = CASI = convertCmpXchgToIntegerType(CASI);
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MadeChange = true;
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}
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}
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if (TLI->shouldInsertFencesForAtomic(I)) {
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auto FenceOrdering = AtomicOrdering::Monotonic;
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if (LI && isAcquireOrStronger(LI->getOrdering())) {
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FenceOrdering = LI->getOrdering();
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LI->setOrdering(AtomicOrdering::Monotonic);
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} else if (SI && isReleaseOrStronger(SI->getOrdering())) {
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FenceOrdering = SI->getOrdering();
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SI->setOrdering(AtomicOrdering::Monotonic);
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} else if (RMWI && (isReleaseOrStronger(RMWI->getOrdering()) ||
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isAcquireOrStronger(RMWI->getOrdering()))) {
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FenceOrdering = RMWI->getOrdering();
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RMWI->setOrdering(AtomicOrdering::Monotonic);
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} else if (CASI &&
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TLI->shouldExpandAtomicCmpXchgInIR(CASI) ==
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TargetLoweringBase::AtomicExpansionKind::None &&
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(isReleaseOrStronger(CASI->getSuccessOrdering()) ||
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isAcquireOrStronger(CASI->getSuccessOrdering()) ||
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isAcquireOrStronger(CASI->getFailureOrdering()))) {
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// If a compare and swap is lowered to LL/SC, we can do smarter fence
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// insertion, with a stronger one on the success path than on the
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// failure path. As a result, fence insertion is directly done by
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// expandAtomicCmpXchg in that case.
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FenceOrdering = CASI->getMergedOrdering();
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CASI->setSuccessOrdering(AtomicOrdering::Monotonic);
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CASI->setFailureOrdering(AtomicOrdering::Monotonic);
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}
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if (FenceOrdering != AtomicOrdering::Monotonic) {
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MadeChange |= bracketInstWithFences(I, FenceOrdering);
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}
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} else if (I->hasAtomicStore() &&
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TLI->shouldInsertTrailingFenceForAtomicStore(I)) {
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auto FenceOrdering = AtomicOrdering::Monotonic;
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if (SI)
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FenceOrdering = SI->getOrdering();
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else if (RMWI)
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FenceOrdering = RMWI->getOrdering();
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else if (CASI && TLI->shouldExpandAtomicCmpXchgInIR(CASI) !=
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TargetLoweringBase::AtomicExpansionKind::LLSC)
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// LLSC is handled in expandAtomicCmpXchg().
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FenceOrdering = CASI->getSuccessOrdering();
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IRBuilder Builder(I);
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if (auto TrailingFence =
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TLI->emitTrailingFence(Builder, I, FenceOrdering)) {
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TrailingFence->moveAfter(I);
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MadeChange = true;
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}
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}
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if (LI)
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MadeChange |= tryExpandAtomicLoad(LI);
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else if (SI)
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MadeChange |= tryExpandAtomicStore(SI);
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else if (RMWI) {
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// There are two different ways of expanding RMW instructions:
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// - into a load if it is idempotent
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// - into a Cmpxchg/LL-SC loop otherwise
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// we try them in that order.
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if (isIdempotentRMW(RMWI) && simplifyIdempotentRMW(RMWI)) {
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MadeChange = true;
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} else {
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MadeChange |= tryExpandAtomicRMW(RMWI);
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}
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} else if (CASI)
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MadeChange |= tryExpandAtomicCmpXchg(CASI);
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}
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return MadeChange;
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}
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