From 330fa7d2a4e0cfbb4b078c9f0ec83f176c331afa Mon Sep 17 00:00:00 2001 From: Nick Desaulniers Date: Mon, 25 Sep 2023 08:53:03 -0700 Subject: [PATCH] [TargetLowering] Deduplicate choosing InlineAsm constraint between ISels (#67057) Given a list of constraints for InlineAsm (ex. "imr") I'm looking to modify the order in which they are chosen. Before doing so, I noticed a fair amount of logic is duplicated between SelectionDAGISel and GlobalISel for this. That is because SelectionDAGISel is also trying to lower immediates during selection. If we detangle these concerns into: 1. choose the preferred constraint 2. attempt to lower that constraint Then we can slide down the list of constraints until we find one that can be lowered. That allows the implementation to be shared between instruction selection frameworks. This makes it so that later I might only need to adjust the priority of constraints in one place, and have both selectors behave the same. --- llvm/include/llvm/CodeGen/TargetLowering.h | 11 +- .../CodeGen/GlobalISel/InlineAsmLowering.cpp | 78 ++---------- .../CodeGen/SelectionDAG/TargetLowering.cpp | 111 ++++++++++-------- .../Target/AArch64/AArch64ISelLowering.cpp | 4 +- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 2 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 +- llvm/lib/Target/AMDGPU/SIISelLowering.h | 6 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 +- llvm/lib/Target/ARM/ARMISelLowering.h | 2 +- llvm/lib/Target/AVR/AVRISelLowering.cpp | 4 +- llvm/lib/Target/AVR/AVRISelLowering.h | 2 +- llvm/lib/Target/Lanai/LanaiISelLowering.cpp | 4 +- llvm/lib/Target/Lanai/LanaiISelLowering.h | 2 +- .../LoongArch/LoongArchISelLowering.cpp | 4 +- .../Target/LoongArch/LoongArchISelLowering.h | 2 +- llvm/lib/Target/M68k/M68kISelLowering.cpp | 2 +- llvm/lib/Target/M68k/M68kISelLowering.h | 2 +- llvm/lib/Target/Mips/MipsISelLowering.cpp | 9 +- llvm/lib/Target/Mips/MipsISelLowering.h | 4 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 7 +- llvm/lib/Target/NVPTX/NVPTXISelLowering.h | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 7 +- llvm/lib/Target/PowerPC/PPCISelLowering.h | 3 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 2 +- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 10 +- llvm/lib/Target/Sparc/SparcISelLowering.h | 3 +- .../Target/SystemZ/SystemZISelLowering.cpp | 9 +- llvm/lib/Target/SystemZ/SystemZISelLowering.h | 3 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 7 +- llvm/lib/Target/X86/X86ISelLowering.h | 3 +- 31 files changed, 142 insertions(+), 184 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index c6a7aa17146d..b2a0a8c15cf1 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -4849,6 +4849,15 @@ public: /// Given a constraint, return the type of constraint it is for this target. virtual ConstraintType getConstraintType(StringRef Constraint) const; + using ConstraintPair = std::pair; + using ConstraintGroup = SmallVector; + /// Given an OpInfo with list of constraints codes as strings, return a + /// sorted Vector of pairs of constraint codes and their types in priority of + /// what we'd prefer to lower them as. This may contain immediates that + /// cannot be lowered, but it is meant to be a machine agnostic order of + /// preferences. + ConstraintGroup getConstraintPreferences(AsmOperandInfo &OpInfo) const; + /// Given a physical register constraint (e.g. {edx}), return the register /// number and the register class for the register. /// @@ -4882,7 +4891,7 @@ public: /// Lower the specified operand into the Ops vector. If it is invalid, don't /// add anything to Ops. - virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const; diff --git a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp index 00dba57fcb80..4089a5e941b0 100644 --- a/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp @@ -133,71 +133,6 @@ static void getRegistersForValue(MachineFunction &MF, } } -/// Return an integer indicating how general CT is. -static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { - switch (CT) { - case TargetLowering::C_Immediate: - case TargetLowering::C_Other: - case TargetLowering::C_Unknown: - return 0; - case TargetLowering::C_Register: - return 1; - case TargetLowering::C_RegisterClass: - return 2; - case TargetLowering::C_Memory: - case TargetLowering::C_Address: - return 3; - } - llvm_unreachable("Invalid constraint type"); -} - -static void chooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, - const TargetLowering *TLI) { - assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); - unsigned BestIdx = 0; - TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; - int BestGenerality = -1; - - // Loop over the options, keeping track of the most general one. - for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { - TargetLowering::ConstraintType CType = - TLI->getConstraintType(OpInfo.Codes[i]); - - // Indirect 'other' or 'immediate' constraints are not allowed. - if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory || - CType == TargetLowering::C_Register || - CType == TargetLowering::C_RegisterClass)) - continue; - - // If this is an 'other' or 'immediate' constraint, see if the operand is - // valid for it. For example, on X86 we might have an 'rI' constraint. If - // the operand is an integer in the range [0..31] we want to use I (saving a - // load of a register), otherwise we must use 'r'. - if (CType == TargetLowering::C_Other || - CType == TargetLowering::C_Immediate) { - assert(OpInfo.Codes[i].size() == 1 && - "Unhandled multi-letter 'other' constraint"); - // FIXME: prefer immediate constraints if the target allows it - } - - // Things with matching constraints can only be registers, per gcc - // documentation. This mainly affects "g" constraints. - if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) - continue; - - // This constraint letter is more general than the previous one, use it. - int Generality = getConstraintGenerality(CType); - if (Generality > BestGenerality) { - BestType = CType; - BestIdx = i; - BestGenerality = Generality; - } - } - - OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; - OpInfo.ConstraintType = BestType; -} - static void computeConstraintToUse(const TargetLowering *TLI, TargetLowering::AsmOperandInfo &OpInfo) { assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); @@ -207,7 +142,18 @@ static void computeConstraintToUse(const TargetLowering *TLI, OpInfo.ConstraintCode = OpInfo.Codes[0]; OpInfo.ConstraintType = TLI->getConstraintType(OpInfo.ConstraintCode); } else { - chooseConstraint(OpInfo, TLI); + TargetLowering::ConstraintGroup G = TLI->getConstraintPreferences(OpInfo); + if (G.empty()) + return; + // FIXME: prefer immediate constraints if the target allows it + unsigned BestIdx = 0; + for (const unsigned E = G.size(); + BestIdx < E && (G[BestIdx].second == TargetLowering::C_Other || + G[BestIdx].second == TargetLowering::C_Immediate); + ++BestIdx) + ; + OpInfo.ConstraintCode = G[BestIdx].first; + OpInfo.ConstraintType = G[BestIdx].second; } // 'X' matches anything. diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 39489e0bf142..6aaaa2f68638 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -5379,11 +5379,12 @@ SDValue TargetLowering::LowerAsmOutputForConstraint( /// Lower the specified operand into the Ops vector. /// If it is invalid, don't add anything to Ops. void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { - if (Constraint.length() > 1) return; + if (Constraint.size() > 1) + return; char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { @@ -5702,20 +5703,27 @@ TargetLowering::ParseConstraints(const DataLayout &DL, return ConstraintOperands; } -/// Return an integer indicating how general CT is. -static unsigned getConstraintGenerality(TargetLowering::ConstraintType CT) { +/// Return a number indicating our preference for chosing a type of constraint +/// over another, for the purpose of sorting them. Immediates are almost always +/// preferrable (when they can be emitted). A higher return value means a +/// stronger preference for one constraint type relative to another. +/// FIXME: We should prefer registers over memory but doing so may lead to +/// unrecoverable register exhaustion later. +/// https://github.com/llvm/llvm-project/issues/20571 +static unsigned getConstraintPiority(TargetLowering::ConstraintType CT) { switch (CT) { case TargetLowering::C_Immediate: case TargetLowering::C_Other: - case TargetLowering::C_Unknown: - return 0; - case TargetLowering::C_Register: - return 1; - case TargetLowering::C_RegisterClass: - return 2; + return 4; case TargetLowering::C_Memory: case TargetLowering::C_Address: return 3; + case TargetLowering::C_RegisterClass: + return 2; + case TargetLowering::C_Register: + return 1; + case TargetLowering::C_Unknown: + return 0; } llvm_unreachable("Invalid constraint type"); } @@ -5813,18 +5821,13 @@ TargetLowering::ConstraintWeight /// 2) Otherwise, pick the most general constraint present. This prefers /// 'm' over 'r', for example. /// -static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, - const TargetLowering &TLI, - SDValue Op, SelectionDAG *DAG) { - assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); - unsigned BestIdx = 0; - TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; - int BestGenerality = -1; +TargetLowering::ConstraintGroup TargetLowering::getConstraintPreferences( + TargetLowering::AsmOperandInfo &OpInfo) const { + ConstraintGroup Ret; - // Loop over the options, keeping track of the most general one. - for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { - TargetLowering::ConstraintType CType = - TLI.getConstraintType(OpInfo.Codes[i]); + Ret.reserve(OpInfo.Codes.size()); + for (StringRef Code : OpInfo.Codes) { + TargetLowering::ConstraintType CType = getConstraintType(Code); // Indirect 'other' or 'immediate' constraints are not allowed. if (OpInfo.isIndirect && !(CType == TargetLowering::C_Memory || @@ -5832,40 +5835,37 @@ static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, CType == TargetLowering::C_RegisterClass)) continue; - // If this is an 'other' or 'immediate' constraint, see if the operand is - // valid for it. For example, on X86 we might have an 'rI' constraint. If - // the operand is an integer in the range [0..31] we want to use I (saving a - // load of a register), otherwise we must use 'r'. - if ((CType == TargetLowering::C_Other || - CType == TargetLowering::C_Immediate) && Op.getNode()) { - assert(OpInfo.Codes[i].size() == 1 && - "Unhandled multi-letter 'other' constraint"); - std::vector ResultOps; - TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], - ResultOps, *DAG); - if (!ResultOps.empty()) { - BestType = CType; - BestIdx = i; - break; - } - } - // Things with matching constraints can only be registers, per gcc // documentation. This mainly affects "g" constraints. if (CType == TargetLowering::C_Memory && OpInfo.hasMatchingInput()) continue; - // This constraint letter is more general than the previous one, use it. - int Generality = getConstraintGenerality(CType); - if (Generality > BestGenerality) { - BestType = CType; - BestIdx = i; - BestGenerality = Generality; - } + Ret.emplace_back(Code, CType); } - OpInfo.ConstraintCode = OpInfo.Codes[BestIdx]; - OpInfo.ConstraintType = BestType; + std::sort(Ret.begin(), Ret.end(), [](ConstraintPair a, ConstraintPair b) { + return getConstraintPiority(a.second) > getConstraintPiority(b.second); + }); + + return Ret; +} + +/// If we have an immediate, see if we can lower it. Return true if we can, +/// false otherwise. +static bool lowerImmediateIfPossible(TargetLowering::ConstraintPair &P, + SDValue Op, SelectionDAG *DAG, + const TargetLowering &TLI) { + + assert((P.second == TargetLowering::C_Other || + P.second == TargetLowering::C_Immediate) && + "need immediate or other"); + + if (!Op.getNode()) + return false; + + std::vector ResultOps; + TLI.LowerAsmOperandForConstraint(Op, P.first, ResultOps, *DAG); + return !ResultOps.empty(); } /// Determines the constraint code and constraint type to use for the specific @@ -5880,7 +5880,20 @@ void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, OpInfo.ConstraintCode = OpInfo.Codes[0]; OpInfo.ConstraintType = getConstraintType(OpInfo.ConstraintCode); } else { - ChooseConstraint(OpInfo, *this, Op, DAG); + ConstraintGroup G = getConstraintPreferences(OpInfo); + if (G.empty()) + return; + + unsigned BestIdx = 0; + for (const unsigned E = G.size(); + BestIdx < E && (G[BestIdx].second == TargetLowering::C_Other || + G[BestIdx].second == TargetLowering::C_Immediate); + ++BestIdx) + if (lowerImmediateIfPossible(G[BestIdx], Op, DAG, *this)) + break; + + OpInfo.ConstraintCode = G[BestIdx].first; + OpInfo.ConstraintType = G[BestIdx].second; } // 'X' matches anything. diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index d6e80dd9a7c3..3de6bd1ec94a 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -10310,12 +10310,12 @@ EVT AArch64TargetLowering::getAsmOperandValueType(const DataLayout &DL, /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void AArch64TargetLowering::LowerAsmOperandForConstraint( - SDValue Op, std::string &Constraint, std::vector &Ops, + SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; // Currently only support length 1 constraints. - if (Constraint.length() != 1) + if (Constraint.size() != 1) return; char ConstraintLetter = Constraint[0]; diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index bdde4b5e8e00..cb195d648187 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1168,7 +1168,7 @@ private: const char *LowerXConstraint(EVT ConstraintVT) const override; - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 60b2f9ee49fc..80fd1d2ea72c 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -13872,7 +13872,7 @@ static uint64_t clearUnusedBits(uint64_t Val, unsigned Size) { } void SITargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { if (isImmConstraint(Constraint)) { @@ -13921,8 +13921,7 @@ bool SITargetLowering::getAsmOperandConstVal(SDValue Op, uint64_t &Val) const { return false; } -bool SITargetLowering::checkAsmConstraintVal(SDValue Op, - const std::string &Constraint, +bool SITargetLowering::checkAsmConstraintVal(SDValue Op, StringRef Constraint, uint64_t Val) const { if (Constraint.size() == 1) { switch (Constraint[0]) { diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h index ffe49f651fdb..2cc42b9ac2e1 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.h +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -468,13 +468,11 @@ public: getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; ConstraintType getConstraintType(StringRef Constraint) const override; - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; bool getAsmOperandConstVal(SDValue Op, uint64_t &Val) const; - bool checkAsmConstraintVal(SDValue Op, - const std::string &Constraint, + bool checkAsmConstraintVal(SDValue Op, StringRef Constraint, uint64_t Val) const; bool checkAsmConstraintValA(SDValue Op, uint64_t Val, diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 69ef942df1f6..846094e46e8e 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -111,7 +111,6 @@ #include #include #include -#include #include #include #include @@ -20244,14 +20243,14 @@ bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { return false; InlineAsm *IA = cast(CI->getCalledOperand()); - std::string AsmStr = IA->getAsmString(); + StringRef AsmStr = IA->getAsmString(); SmallVector AsmPieces; SplitString(AsmStr, AsmPieces, ";\n"); switch (AsmPieces.size()) { default: return false; case 1: - AsmStr = std::string(AsmPieces[0]); + AsmStr = AsmPieces[0]; AsmPieces.clear(); SplitString(AsmStr, AsmPieces, " \t,"); @@ -20431,13 +20430,14 @@ RCPair ARMTargetLowering::getRegForInlineAsmConstraint( /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, - std::vector&Ops, + StringRef Constraint, + std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; // Currently only support length 1 constraints. - if (Constraint.length() != 1) return; + if (Constraint.size() != 1) + return; char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index efa823867686..6c2b92de7a1d 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -530,7 +530,7 @@ class VectorType; /// vector. If it is invalid, don't add anything to Ops. If hasMemory is /// true it means one of the asm constraint of the inline asm instruction /// being processed is 'm'. - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp index 4f5a48bd05a4..cd1dcfaea0eb 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.cpp +++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -2722,7 +2722,7 @@ AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, } void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; @@ -2730,7 +2730,7 @@ void AVRTargetLowering::LowerAsmOperandForConstraint(SDValue Op, EVT Ty = Op.getValueType(); // Currently only support length 1 constraints. - if (Constraint.length() != 1) { + if (Constraint.size() != 1) { return; } diff --git a/llvm/lib/Target/AVR/AVRISelLowering.h b/llvm/lib/Target/AVR/AVRISelLowering.h index 6815b519bebf..f60579593453 100644 --- a/llvm/lib/Target/AVR/AVRISelLowering.h +++ b/llvm/lib/Target/AVR/AVRISelLowering.h @@ -136,7 +136,7 @@ public: InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const override; - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp index 157f86027433..cbb5c2b998e2 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -278,12 +278,12 @@ LanaiTargetLowering::getSingleConstraintMatchWeight( // LowerAsmOperandForConstraint - Lower the specified operand into the Ops // vector. If it is invalid, don't add anything to Ops. void LanaiTargetLowering::LowerAsmOperandForConstraint( - SDValue Op, std::string &Constraint, std::vector &Ops, + SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; // Only support length 1 constraints for now. - if (Constraint.length() > 1) + if (Constraint.size() > 1) return; char ConstraintLetter = Constraint[0]; diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.h b/llvm/lib/Target/Lanai/LanaiISelLowering.h index ea1159db9e59..5fa5444b5161 100644 --- a/llvm/lib/Target/Lanai/LanaiISelLowering.h +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.h @@ -103,7 +103,7 @@ public: ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info, const char *Constraint) const override; - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index a4fa79cb0aad..a97523d17c18 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -4371,10 +4371,10 @@ LoongArchTargetLowering::getRegForInlineAsmConstraint( } void LoongArchTargetLowering::LowerAsmOperandForConstraint( - SDValue Op, std::string &Constraint, std::vector &Ops, + SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { // Currently only support length 1 constraints. - if (Constraint.length() == 1) { + if (Constraint.size() == 1) { switch (Constraint[0]) { case 'l': // Validate & create a 16-bit signed immediate operand. diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h index 9d531894a137..49d563a51389 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h @@ -290,7 +290,7 @@ private: getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp index 82f6d7323cf6..d1ed26457fbc 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -2897,7 +2897,7 @@ M68kTargetLowering::getConstraintType(StringRef Constraint) const { } void M68kTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; diff --git a/llvm/lib/Target/M68k/M68kISelLowering.h b/llvm/lib/Target/M68k/M68kISelLowering.h index 37e66695fde9..02427a4e749e 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.h +++ b/llvm/lib/Target/M68k/M68kISelLowering.h @@ -163,7 +163,7 @@ public: StringRef Constraint, MVT VT) const override; // Lower operand with C_Immediate and C_Other constraint type - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 18d7773067f1..6ff829261f5c 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -4198,14 +4198,15 @@ MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, - std::vector&Ops, - SelectionDAG &DAG) const { + StringRef Constraint, + std::vector &Ops, + SelectionDAG &DAG) const { SDLoc DL(Op); SDValue Result; // Only support length 1 constraints for now. - if (Constraint.length() > 1) return; + if (Constraint.size() > 1) + return; char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h index 4b5700b7e28d..81d37ff2f065 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/llvm/lib/Target/Mips/MipsISelLowering.h @@ -33,7 +33,6 @@ #include #include #include -#include #include #include @@ -641,8 +640,7 @@ class TargetRegisterClass; /// vector. If it is invalid, don't add anything to Ops. If hasMemory is /// true it means one of the asm constraint of the inline asm instruction /// being processed is 'm'. - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index e9401d4b93c3..22a72ae24b44 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -3089,12 +3089,11 @@ NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, } void NVPTXTargetLowering::LowerAsmOperandForConstraint( - SDValue Op, std::string &Constraint, std::vector &Ops, + SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { - if (Constraint.length() > 1) + if (Constraint.size() > 1) return; - else - TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } static unsigned getOpcForTextureInstr(unsigned Intrinsic) { diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h index 0b760d06743e..cd1985cc4219 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -520,7 +520,7 @@ public: const SmallVectorImpl &OutVals, const SDLoc &dl, SelectionDAG &DAG) const override; - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index f4e3531980d1..740e5e2ff4b4 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -16718,13 +16718,14 @@ PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, - std::vector&Ops, + StringRef Constraint, + std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; // Only support length 1 constraints. - if (Constraint.length() > 1) return; + if (Constraint.size() > 1) + return; char Letter = Constraint[0]; switch (Letter) { diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h index 7c62e370f153..d8679dcf4018 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.h +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -975,8 +975,7 @@ namespace llvm { /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 08e37ea2a363..686350de2988 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -17739,10 +17739,10 @@ RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const { } void RISCVTargetLowering::LowerAsmOperandForConstraint( - SDValue Op, std::string &Constraint, std::vector &Ops, + SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const { // Currently only support length 1 constraints. - if (Constraint.length() == 1) { + if (Constraint.size() == 1) { switch (Constraint[0]) { case 'I': // Validate & create a 12-bit signed immediate operand. diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h index 815b9be47f56..0b8e6994a876 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -573,7 +573,7 @@ public: getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const override; - void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 0091cb7b8bbe..4d1acc9ad145 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -3428,15 +3428,13 @@ getSingleConstraintMatchWeight(AsmOperandInfo &info, /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. -void SparcTargetLowering:: -LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, - std::vector &Ops, - SelectionDAG &DAG) const { +void SparcTargetLowering::LowerAsmOperandForConstraint( + SDValue Op, StringRef Constraint, std::vector &Ops, + SelectionDAG &DAG) const { SDValue Result; // Only support length 1 constraints for now. - if (Constraint.length() > 1) + if (Constraint.size() > 1) return; char ConstraintLetter = Constraint[0]; diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.h b/llvm/lib/Target/Sparc/SparcISelLowering.h index 5504dcd464fb..b7b48decef3d 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.h +++ b/llvm/lib/Target/Sparc/SparcISelLowering.h @@ -88,8 +88,7 @@ namespace llvm { ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override; - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 6a56869ca20f..886b5e93bffc 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -1289,12 +1289,11 @@ SystemZTargetLowering::getRegisterByName(const char *RegName, LLT VT, report_fatal_error("Invalid register name global variable"); } -void SystemZTargetLowering:: -LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, - std::vector &Ops, - SelectionDAG &DAG) const { +void SystemZTargetLowering::LowerAsmOperandForConstraint( + SDValue Op, StringRef Constraint, std::vector &Ops, + SelectionDAG &DAG) const { // Only support length 1 constraints for now. - if (Constraint.length() == 1) { + if (Constraint.size() == 1) { switch (Constraint[0]) { case 'I': // Unsigned 8-bit constant if (auto *C = dyn_cast(Op)) diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h index 8feeb61abd79..0d4b4873e9d7 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -487,8 +487,7 @@ public: TargetLowering::ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override; - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 81aa998d33c6..71998140325b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -56569,13 +56569,14 @@ SDValue X86TargetLowering::LowerAsmOutputForConstraint( /// Lower the specified operand into the Ops vector. /// If it is invalid, don't add anything to Ops. void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, - std::vector&Ops, + StringRef Constraint, + std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; // Only support length 1 constraints for now. - if (Constraint.length() > 1) return; + if (Constraint.size() > 1) + return; char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h index 1c51a37312bf..8046f4273695 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -1274,8 +1274,7 @@ namespace llvm { /// Lower the specified operand into the Ops vector. If it is invalid, don't /// add anything to Ops. If hasMemory is true it means one of the asm /// constraint of the inline asm instruction being processed is 'm'. - void LowerAsmOperandForConstraint(SDValue Op, - std::string &Constraint, + void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector &Ops, SelectionDAG &DAG) const override;