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Revert "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"

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This reverts commit 657d20dc75252f0c8415ada5214affccc3c98efe.  A correctness problem was reported against the review and the fix warrants re-review.
This commit is contained in:
Philip Reames 2023-05-10 10:49:30 -07:00 committed by Philip Reames
parent 878e590503
commit 33314693f5
21 changed files with 510 additions and 268 deletions
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38
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
View File

@ -85,18 +85,6 @@ static bool isScalarMoveInstr(const MachineInstr &MI) {
}
}
static bool isVSlideInstr(const MachineInstr &MI) {
switch (getRVVMCOpcode(MI.getOpcode())) {
default:
return false;
case RISCV::VSLIDEDOWN_VX:
case RISCV::VSLIDEDOWN_VI:
case RISCV::VSLIDEUP_VX:
case RISCV::VSLIDEUP_VI:
return true;
}
}
/// Get the EEW for a load or store instruction. Return std::nullopt if MI is
/// not a load or store which ignores SEW.
static std::optional<unsigned> getEEWForLoadStore(const MachineInstr &MI) {
@ -830,11 +818,6 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
.addImm(Info.encodeVTYPE());
}
static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) {
auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL);
return Fractional || LMul == 1;
}
/// Return true if a VSETVLI is required to transition from CurInfo to Require
/// before MI.
bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
@ -862,27 +845,6 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI,
}
}
// A slidedown/slideup with a VL of 1 whose destination is an IMPLICIT_DEF
// can use any VL/SEW combination which writes at least the first element.
// Notes:
// * VL=1 is special only because we have existing support for zero vs
// non-zero VL. We could generalize this if we had a VL > C predicate.
// * The LMUL1 restriction is for machines whose latency may depend on VL.
// * As above, this is only legal for IMPLICIT_DEF, not TA.
if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 &&
isLMUL1OrSmaller(CurInfo.getVLMUL())) {
auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg());
if (VRegDef && VRegDef->isImplicitDef() &&
CurInfo.getSEW() >= Require.getSEW()) {
Used.VLAny = false;
Used.VLZeroness = true;
Used.SEW = false;
Used.LMUL = false;
Used.SEWLMULRatio = false;
Used.TailPolicy = false;
}
}
if (CurInfo.isCompatible(Used, Require))
return false;

4
llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
View File

@ -10,6 +10,7 @@ define i1 @extractelt_nxv1i1(<vscale x 1 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -27,6 +28,7 @@ define i1 @extractelt_nxv2i1(<vscale x 2 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -44,6 +46,7 @@ define i1 @extractelt_nxv4i1(<vscale x 4 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -61,6 +64,7 @@ define i1 @extractelt_nxv8i1(<vscale x 8 x i8>* %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret

2
llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
View File

@ -16,7 +16,9 @@ define <2 x i1> @reverse_v2i1(<2 x i1> %a) {
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 1
; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret

2
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll
View File

@ -59,9 +59,9 @@ define void @abs_v6i16(ptr %x) {
; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x i16>, ptr %x

2
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
View File

@ -30,6 +30,7 @@ define i1 @extractelt_v2i1(ptr %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -47,6 +48,7 @@ define i1 @extractelt_v4i1(ptr %x, i64 %idx) nounwind {
; CHECK-NEXT: vmseq.vi v0, v8, 0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret

1
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
View File

@ -248,6 +248,7 @@ define void @extract_v8i1_v64i1_8(ptr %x, ptr %y) {
; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vlm.v v8, (a0)
; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1
; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; LMULMAX1-NEXT: vsm.v v8, (a1)

34
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll
View File

@ -9,6 +9,7 @@ define i8 @extractelt_v16i8(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -22,6 +23,7 @@ define i16 @extractelt_v8i16(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -35,6 +37,7 @@ define i32 @extractelt_v4i32(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -71,6 +74,7 @@ define half @extractelt_v8f16(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@ -84,6 +88,7 @@ define float @extractelt_v4f32(ptr %x) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@ -247,6 +252,7 @@ define i8 @extractelt_v16i8_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -260,6 +266,7 @@ define i16 @extractelt_v8i16_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -274,6 +281,7 @@ define i32 @extractelt_v4i32_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
@ -289,10 +297,10 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret
@ -302,6 +310,7 @@ define i64 @extractelt_v2i64_idx(ptr %x, i32 zeroext %idx) nounwind {
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vx v8, v8, a1
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@ -317,6 +326,7 @@ define half @extractelt_v8f16_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@ -332,6 +342,7 @@ define float @extractelt_v4f32_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@ -347,6 +358,7 @@ define double @extractelt_v2f64_idx(ptr %x, i32 zeroext %idx) nounwind {
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfadd.vv v8, v8, v8
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a1
; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret
@ -517,8 +529,8 @@ define void @store_extractelt_v16i8(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
%a = load <16 x i8>, ptr %x
@ -532,8 +544,8 @@ define void @store_extractelt_v8i16(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 7
; CHECK-NEXT: vse16.v v8, (a1)
; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %x
@ -547,8 +559,8 @@ define void @store_extractelt_v4i32(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret
%a = load <4 x i32>, ptr %x
@ -563,9 +575,9 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vi v8, v8, 1
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: vmv.x.s a2, v8
@ -577,8 +589,8 @@ define void @store_extractelt_v2i64(ptr %x, ptr %p) nounwind {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 1
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: ret
%a = load <2 x i64>, ptr %x
@ -592,8 +604,8 @@ define void @store_extractelt_v2f64(ptr %x, ptr %p) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x
@ -615,6 +627,7 @@ define i32 @extractelt_add_v4i32(<4 x i32> %x) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vadd.vi v8, v8, 13
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@ -637,6 +650,7 @@ define i32 @extractelt_sub_v4i32(<4 x i32> %x) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vrsub.vi v8, v8, 13
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@ -651,6 +665,7 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; RV32NOM-NEXT: li a0, 13
; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32NOM-NEXT: vmul.vx v8, v8, a0
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: ret
@ -669,6 +684,7 @@ define i32 @extractelt_mul_v4i32(<4 x i32> %x) {
; RV64-NEXT: li a0, 13
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@ -696,6 +712,7 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV32NOM-NEXT: vsra.vv v9, v8, v11
; RV32NOM-NEXT: vsrl.vi v8, v8, 31
; RV32NOM-NEXT: vadd.vv v8, v9, v8
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: ret
@ -731,6 +748,7 @@ define i32 @extractelt_sdiv_v4i32(<4 x i32> %x) {
; RV64-NEXT: vsra.vv v8, v8, v11
; RV64-NEXT: vsrl.vi v9, v8, 31
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret
@ -747,6 +765,7 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; RV32NOM-NEXT: lui a0, 322639
; RV32NOM-NEXT: addi a0, a0, -945
; RV32NOM-NEXT: vmulhu.vx v8, v8, a0
; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32NOM-NEXT: vslidedown.vi v8, v8, 2
; RV32NOM-NEXT: vmv.x.s a0, v8
; RV32NOM-NEXT: srli a0, a0, 2
@ -771,6 +790,7 @@ define i32 @extractelt_udiv_v4i32(<4 x i32> %x) {
; RV64-NEXT: addiw a0, a0, -945
; RV64-NEXT: vmulhu.vx v8, v8, a0
; RV64-NEXT: vsrl.vi v8, v8, 2
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret

62
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
View File

@ -47,9 +47,9 @@ define void @fadd_v6f16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -130,9 +130,9 @@ define void @fsub_v6f16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -213,9 +213,9 @@ define void @fmul_v6f16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -296,9 +296,9 @@ define void @fdiv_v6f16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -375,9 +375,9 @@ define void @fneg_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfneg.v v8, v8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -450,9 +450,9 @@ define void @fabs_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfabs.v v8, v8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -532,9 +532,9 @@ define void @copysign_v6f16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -616,9 +616,9 @@ define void @copysign_vf_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfsgnj.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -701,9 +701,9 @@ define void @copysign_neg_v6f16(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vfsgnjn.vv v8, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -776,9 +776,9 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
; LMULMAX1-RV32-NEXT: vle16.v v9, (a0)
; LMULMAX1-RV32-NEXT: vfncvt.f.f.w v10, v8
; LMULMAX1-RV32-NEXT: vfsgnjn.vv v8, v9, v10
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: addi a1, a0, 4
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV32-NEXT: vse16.v v9, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
@ -792,9 +792,9 @@ define void @copysign_neg_trunc_v3f16_v3f32(ptr %x, ptr %y) {
; LMULMAX1-RV64-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV64-NEXT: vfncvt.f.f.w v10, v9
; LMULMAX1-RV64-NEXT: vfsgnjn.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1-RV64-NEXT: addi a1, a0, 4
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1-RV64-NEXT: vse16.v v9, (a1)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
@ -865,9 +865,9 @@ define void @sqrt_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfsqrt.v v8, v8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -951,9 +951,9 @@ define void @fma_v6f16(ptr %x, ptr %y, ptr %z) {
; LMULMAX1-RV64-NEXT: vfmacc.vv v10, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -1047,9 +1047,9 @@ define void @fmsub_v6f16(ptr %x, ptr %y, ptr %z) {
; LMULMAX1-RV64-NEXT: vfmsac.vv v10, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -1878,9 +1878,9 @@ define void @fadd_vf_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfadd.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -1960,9 +1960,9 @@ define void @fadd_fv_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfadd.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2042,9 +2042,9 @@ define void @fsub_vf_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfsub.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2124,9 +2124,9 @@ define void @fsub_fv_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfrsub.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2206,9 +2206,9 @@ define void @fmul_vf_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfmul.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2288,9 +2288,9 @@ define void @fmul_fv_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfmul.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2370,9 +2370,9 @@ define void @fdiv_vf_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfdiv.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2452,9 +2452,9 @@ define void @fdiv_fv_v6f16(ptr %x, half %y) {
; LMULMAX1-RV64-NEXT: vfrdiv.vf v8, v8, fa0
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2538,9 +2538,9 @@ define void @fma_vf_v6f16(ptr %x, ptr %y, half %z) {
; LMULMAX1-RV64-NEXT: vfmacc.vf v9, fa0, v8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2629,9 +2629,9 @@ define void @fma_fv_v6f16(ptr %x, ptr %y, half %z) {
; LMULMAX1-RV64-NEXT: vfmacc.vf v9, fa0, v8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2721,9 +2721,9 @@ define void @fmsub_vf_v6f16(ptr %x, ptr %y, half %z) {
; LMULMAX1-RV64-NEXT: vfmsac.vf v9, fa0, v8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2871,9 +2871,9 @@ define void @trunc_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -2990,9 +2990,9 @@ define void @ceil_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -3113,9 +3113,9 @@ define void @floor_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -3236,9 +3236,9 @@ define void @round_v6f16(ptr %x) {
; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -3478,9 +3478,9 @@ define void @fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
; LMULMAX1-RV64-NEXT: vfmacc.vv v10, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x
@ -3574,9 +3574,9 @@ define void @fmsub_fmuladd_v6f16(ptr %x, ptr %y, ptr %z) {
; LMULMAX1-RV64-NEXT: vfmsac.vv v10, v8, v9
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse64.v v10, (a0)
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2
; LMULMAX1-RV64-NEXT: addi a0, a0, 8
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret
%a = load <6 x half>, ptr %x

6
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll
View File

@ -191,6 +191,7 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vslidedown.vi v9, v8, 1
; RV32-NEXT: vfmv.f.s fa5, v9
; RV32-NEXT: lui a0, %hi(.LCPI10_0)
@ -210,7 +211,7 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV32-NEXT: fmin.d fa5, fa5, fa3
; RV32-NEXT: fcvt.w.d a3, fa5, rtz
; RV32-NEXT: and a2, a2, a3
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV32-NEXT: vslide1down.vx v8, v8, a2
; RV32-NEXT: vslide1down.vx v8, v8, a0
; RV32-NEXT: vse8.v v8, (a1)
@ -220,6 +221,7 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vslidedown.vi v9, v8, 1
; RV64-NEXT: vfmv.f.s fa5, v9
; RV64-NEXT: lui a0, %hi(.LCPI10_0)
@ -239,7 +241,7 @@ define void @fp2si_v2f64_v2i8(ptr %x, ptr %y) {
; RV64-NEXT: fmin.d fa5, fa5, fa3
; RV64-NEXT: fcvt.l.d a3, fa5, rtz
; RV64-NEXT: and a2, a2, a3
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: vslide1down.vx v8, v8, a0
; RV64-NEXT: vse8.v v8, (a1)

24
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
View File

@ -84,9 +84,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@ -97,9 +97,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@ -110,9 +110,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@ -123,9 +123,9 @@ define void @fp2si_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.rtz.x.f.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
@ -142,9 +142,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@ -155,9 +155,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@ -168,9 +168,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@ -181,9 +181,9 @@ define void @fp2ui_v3f32_v3i32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
@ -212,6 +212,7 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV32-NEXT: vmv.x.s a1, v8
; LMULMAX8RV32-NEXT: slli a2, a1, 17
@ -239,6 +240,7 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV64-NEXT: lui a2, 8
; LMULMAX8RV64-NEXT: addiw a2, a2, -1
; LMULMAX8RV64-NEXT: and a1, a1, a2
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: and a2, a3, a2
@ -258,6 +260,7 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1RV32-NEXT: slli a2, a1, 17
@ -285,6 +288,7 @@ define <3 x i15> @fp2si_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV64-NEXT: lui a2, 8
; LMULMAX1RV64-NEXT: addiw a2, a2, -1
; LMULMAX1RV64-NEXT: and a1, a1, a2
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: and a2, a3, a2
@ -309,6 +313,7 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV32: # %bb.0:
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX8RV32-NEXT: vmv.x.s a1, v8
; LMULMAX8RV32-NEXT: slli a2, a1, 17
@ -336,6 +341,7 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX8RV64-NEXT: lui a2, 16
; LMULMAX8RV64-NEXT: addiw a2, a2, -1
; LMULMAX8RV64-NEXT: and a1, a1, a2
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX8RV64-NEXT: vmv.x.s a3, v8
; LMULMAX8RV64-NEXT: and a2, a3, a2
@ -355,6 +361,7 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV32: # %bb.0:
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2
; LMULMAX1RV32-NEXT: vmv.x.s a1, v8
; LMULMAX1RV32-NEXT: slli a2, a1, 17
@ -382,6 +389,7 @@ define <3 x i15> @fp2ui_v3f32_v3i15(<3 x float> %x) {
; LMULMAX1RV64-NEXT: lui a2, 16
; LMULMAX1RV64-NEXT: addiw a2, a2, -1
; LMULMAX1RV64-NEXT: and a1, a1, a2
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1
; LMULMAX1RV64-NEXT: vmv.x.s a3, v8
; LMULMAX1RV64-NEXT: and a2, a3, a2

16
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
View File

@ -90,9 +90,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@ -103,9 +103,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@ -116,9 +116,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@ -129,9 +129,9 @@ define void @si2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.f.x.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)
@ -148,9 +148,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vle32.v v8, (a0)
; LMULMAX8RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV32-NEXT: addi a0, a1, 8
; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v9, (a0)
; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX8RV32-NEXT: vse32.v v8, (a1)
@ -161,9 +161,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vle32.v v8, (a0)
; LMULMAX8RV64-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX8RV64-NEXT: addi a0, a1, 8
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX8RV64-NEXT: vse32.v v9, (a0)
; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX8RV64-NEXT: vse64.v v8, (a1)
@ -174,9 +174,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV32-NEXT: addi a0, a1, 8
; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX1RV32-NEXT: vse32.v v8, (a1)
@ -187,9 +187,9 @@ define void @ui2fp_v3i32_v3f32(ptr %x, ptr %y) {
; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vle32.v v8, (a0)
; LMULMAX1RV64-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2
; LMULMAX1RV64-NEXT: addi a0, a1, 8
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; LMULMAX1RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; LMULMAX1RV64-NEXT: vse64.v v8, (a1)

54
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
View File

@ -61,9 +61,9 @@ define void @add_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -160,9 +160,9 @@ define void @sub_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vsub.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -259,9 +259,9 @@ define void @mul_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vmul.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -358,9 +358,9 @@ define void @and_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vand.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -457,9 +457,9 @@ define void @or_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -556,9 +556,9 @@ define void @xor_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vxor.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -655,9 +655,9 @@ define void @lshr_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vsrl.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -754,9 +754,9 @@ define void @ashr_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vsra.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -853,9 +853,9 @@ define void @shl_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vsll.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -967,9 +967,9 @@ define void @sdiv_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vslideup.vi v8, v10, 4
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -1081,9 +1081,9 @@ define void @srem_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vslideup.vi v8, v10, 4
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -1195,9 +1195,9 @@ define void @udiv_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vslideup.vi v8, v10, 4
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -1309,9 +1309,9 @@ define void @urem_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vslideup.vi v8, v10, 4
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -1536,9 +1536,9 @@ define void @mulhu_v6i16(ptr %x) {
; RV64-NEXT: vslideup.vi v9, v8, 4
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v9, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v9, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -1763,9 +1763,9 @@ define void @mulhs_v6i16(ptr %x) {
; RV64-NEXT: vslideup.vi v8, v9, 4
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -1933,9 +1933,9 @@ define void @smin_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vmin.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2035,9 +2035,9 @@ define void @smin_vx_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vmin.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2119,9 +2119,9 @@ define void @smin_xv_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vmin.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2205,9 +2205,9 @@ define void @smax_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vmax.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2307,9 +2307,9 @@ define void @smax_vx_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vmax.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2391,9 +2391,9 @@ define void @smax_xv_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vmax.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2477,9 +2477,9 @@ define void @umin_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vminu.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2579,9 +2579,9 @@ define void @umin_vx_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vminu.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2663,9 +2663,9 @@ define void @umin_xv_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vminu.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2749,9 +2749,9 @@ define void @umax_v6i16(ptr %x, ptr %y) {
; RV64-NEXT: vmaxu.vv v8, v8, v9
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2851,9 +2851,9 @@ define void @umax_vx_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vmaxu.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x
@ -2935,9 +2935,9 @@ define void @umax_xv_v6i16(ptr %x, i16 %y) {
; RV64-NEXT: vmaxu.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%a = load <6 x i16>, ptr %x

6
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll
View File

@ -33,8 +33,8 @@ define <5 x i8> @load_v5i8_align1(ptr %p) {
; RV32-NEXT: or a1, a3, a1
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vmv.s.x v8, a1
; RV32-NEXT: vslidedown.vi v9, v8, 3
; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vi v9, v8, 3
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vslidedown.vi v9, v8, 2
; RV32-NEXT: vmv.x.s a2, v9
@ -65,8 +65,8 @@ define <5 x i8> @load_v5i8_align1(ptr %p) {
; RV64-NEXT: or a1, a3, a1
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vmv.s.x v8, a1
; RV64-NEXT: vslidedown.vi v9, v8, 3
; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vi v9, v8, 3
; RV64-NEXT: vmv.x.s a1, v9
; RV64-NEXT: vslidedown.vi v9, v8, 2
; RV64-NEXT: vmv.x.s a2, v9
@ -141,9 +141,9 @@ define <6 x half> @load_v6f16(ptr %p) {
; RV64-NEXT: vslide1down.vx v8, v8, a2
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: sd a2, 0(a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
%x = load <6 x half>, ptr %p

255
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
View File

File diff suppressed because it is too large Load Diff

237
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
View File

File diff suppressed because it is too large Load Diff

8
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll
View File

@ -43,9 +43,9 @@ define void @store_v6i8(ptr %p, <6 x i8> %v) {
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: addi a0, a0, 4
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret
store <6 x i8> %v, ptr %p
@ -67,9 +67,9 @@ define void @store_v12i8(ptr %p, <12 x i8> %v) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
store <12 x i8> %v, ptr %p
@ -91,9 +91,9 @@ define void @store_v6i16(ptr %p, <6 x i16> %v) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
store <6 x i16> %v, ptr %p
@ -155,9 +155,9 @@ define void @store_v6f16(ptr %p, <6 x half> %v) {
; RV64-NEXT: vslide1down.vx v8, v8, a1
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 2
; RV64-NEXT: addi a0, a0, 8
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret
store <6 x half> %v, ptr %p

1
llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll
View File

@ -20,6 +20,7 @@ define i32 @test(i32 %call.i) {
; CHECK-V-NEXT: vmslt.vx v0, v8, a0
; CHECK-V-NEXT: vmv.v.i v8, 0
; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
; CHECK-V-NEXT: vmv.x.s a0, v8
; CHECK-V-NEXT: ret

14
llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll
View File

@ -22,7 +22,9 @@ define <4 x i8> @v2i8_2(<2 x i8> %a, <2 x i8> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@ -170,7 +172,9 @@ define <4 x i16> @v2i16_2(<2 x i16> %a, <2 x i16> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@ -317,7 +321,9 @@ define <4 x i32> @v2i32_2(<2 x i32> %a, < 2 x i32> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@ -465,7 +471,9 @@ define <4 x i64> @v2i64_2(<2 x i64> %a, < 2 x i64> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@ -552,7 +560,9 @@ define <4 x half> @v2f16_2(<2 x half> %a, <2 x half> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@ -673,7 +683,9 @@ define <4 x float> @v2f32_2(<2 x float> %a, <2 x float> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2
@ -764,7 +776,9 @@ define <4 x double> @v2f64_2(<2 x double> %a, < 2 x double> %b) {
; CHECK-NEXT: vslidedown.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vslideup.vi v8, v9, 1
; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT: vslideup.vi v8, v10, 2

8
llvm/test/CodeGen/RISCV/rvv/vector-splice.ll
View File

@ -15,7 +15,9 @@ define <vscale x 1 x i1> @splice_nxv1i1_offset_negone(<vscale x 1 x i1> %a, <vsc
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
@ -59,7 +61,9 @@ define <vscale x 2 x i1> @splice_nxv2i1_offset_negone(<vscale x 2 x i1> %a, <vsc
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
@ -103,7 +107,9 @@ define <vscale x 4 x i1> @splice_nxv4i1_offset_negone(<vscale x 4 x i1> %a, <vsc
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1
@ -146,7 +152,9 @@ define <vscale x 8 x i1> @splice_nxv8i1_offset_negone(<vscale x 8 x i1> %a, <vsc
; CHECK-NEXT: vmerge.vim v10, v9, 1, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v10, v10, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v9, 1, v0
; CHECK-NEXT: vslideup.vi v10, v8, 1

2
llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll
View File

@ -198,9 +198,11 @@ define <vscale x 4 x i1> @splat_idx_nxv4i32(<vscale x 4 x i1> %v, i64 %idx) {
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret

2
llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
View File

@ -564,6 +564,7 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV32MV-NEXT: vand.vx v8, v8, a1
; RV32MV-NEXT: vmsltu.vv v0, v12, v8
; RV32MV-NEXT: vmerge.vim v8, v10, -1, v0
; RV32MV-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV32MV-NEXT: vslidedown.vi v9, v8, 2
; RV32MV-NEXT: vmv.x.s a1, v9
; RV32MV-NEXT: slli a2, a1, 21
@ -627,6 +628,7 @@ define void @test_urem_vec(ptr %X) nounwind {
; RV64MV-NEXT: vmerge.vim v8, v10, -1, v0
; RV64MV-NEXT: vmv.x.s a1, v8
; RV64MV-NEXT: andi a1, a1, 2047
; RV64MV-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64MV-NEXT: vslidedown.vi v9, v8, 1
; RV64MV-NEXT: vmv.x.s a2, v9
; RV64MV-NEXT: andi a2, a2, 2047