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AMDGPU: Implememt memsize forms of isLoadFromStackSlot/isStoreToStackSlot (#188264)

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Requested in #182673, though I'm not sure why this needs to be pushed
into targets. The size can be taken from the machine mem operand
generically.
This commit is contained in:
Matt Arsenault 2026-03-25 09:22:04 +01:00 committed by GitHub
parent 19048672ab
commit 34ee487775
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GPG Key ID: B5690EEEBB952194
3 changed files with 41 additions and 19 deletions
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34
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -9748,8 +9748,8 @@ bool SIInstrInfo::isHighLatencyDef(int Opc) const {
(isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc) || isFLAT(Opc));
}
Register SIInstrInfo::isStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
Register SIInstrInfo::isStackAccess(const MachineInstr &MI, int &FrameIndex,
TypeSize &MemBytes) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::vaddr);
if (!Addr || !Addr->isFI())
return Register();
@ -9758,41 +9758,51 @@ Register SIInstrInfo::isStackAccess(const MachineInstr &MI,
(*MI.memoperands_begin())->getAddrSpace() == AMDGPUAS::PRIVATE_ADDRESS);
FrameIndex = Addr->getIndex();
return getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
int VDataIdx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdata);
MemBytes = TypeSize::getFixed(getOpSize(MI.getOpcode(), VDataIdx));
return MI.getOperand(VDataIdx).getReg();
}
Register SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI,
int &FrameIndex) const {
Register SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex,
TypeSize &MemBytes) const {
const MachineOperand *Addr = getNamedOperand(MI, AMDGPU::OpName::addr);
assert(Addr && Addr->isFI());
FrameIndex = Addr->getIndex();
return getNamedOperand(MI, AMDGPU::OpName::data)->getReg();
int DataIdx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::data);
MemBytes = TypeSize::getFixed(getOpSize(MI.getOpcode(), DataIdx));
return MI.getOperand(DataIdx).getReg();
}
Register SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
int &FrameIndex,
TypeSize &MemBytes) const {
if (!MI.mayLoad())
return Register();
if (isMUBUF(MI) || isVGPRSpill(MI))
return isStackAccess(MI, FrameIndex);
return isStackAccess(MI, FrameIndex, MemBytes);
if (isSGPRSpill(MI))
return isSGPRStackAccess(MI, FrameIndex);
return isSGPRStackAccess(MI, FrameIndex, MemBytes);
return Register();
}
Register SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
int &FrameIndex,
TypeSize &MemBytes) const {
if (!MI.mayStore())
return Register();
if (isMUBUF(MI) || isVGPRSpill(MI))
return isStackAccess(MI, FrameIndex);
return isStackAccess(MI, FrameIndex, MemBytes);
if (isSGPRSpill(MI))
return isSGPRStackAccess(MI, FrameIndex);
return isSGPRStackAccess(MI, FrameIndex, MemBytes);
return Register();
}

23
llvm/lib/Target/AMDGPU/SIInstrInfo.h
View File

@ -1556,13 +1556,28 @@ public:
return get(pseudoToMCOpcode(Opcode));
}
Register isStackAccess(const MachineInstr &MI, int &FrameIndex) const;
Register isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const;
Register isStackAccess(const MachineInstr &MI, int &FrameIndex,
TypeSize &MemBytes) const;
Register isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex,
TypeSize &MemBytes) const;
Register isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
int &FrameIndex) const override {
TypeSize MemBytes = TypeSize::getZero();
return isLoadFromStackSlot(MI, FrameIndex, MemBytes);
}
Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex,
TypeSize &MemBytes) const override;
Register isStoreToStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
int &FrameIndex) const override {
TypeSize MemBytes = TypeSize::getZero();
return isStoreToStackSlot(MI, FrameIndex, MemBytes);
}
Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex,
TypeSize &MemBytes) const override;
unsigned getInstBundleSize(const MachineInstr &MI) const;
unsigned getInstSizeInBytes(const MachineInstr &MI) const override;

3
llvm/test/CodeGen/AMDGPU/si-lower-sgpr-spills-vgpr-lanes-usage.mir
View File

@ -42,7 +42,6 @@ body: |
; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit undef $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: $sgpr0 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1, implicit-def $sgpr0_sgpr1
; SGPR_SPILLED-NEXT: $sgpr1 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 2
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr2, 1, [[DEF]], implicit-def $sgpr2_sgpr3, implicit $sgpr2_sgpr3
@ -108,7 +107,6 @@ body: |
; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit undef $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: $sgpr2 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1, implicit-def $sgpr2_sgpr3
; SGPR_SPILLED-NEXT: $sgpr3 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 2
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr2, 1, [[DEF]]
@ -171,7 +169,6 @@ body: |
; SGPR_SPILLED-NEXT: $sgpr5 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 4
; SGPR_SPILLED-NEXT: dead $sgpr30_sgpr31 = SI_CALL killed renamable $sgpr4_sgpr5, 0, csr_amdgpu, implicit undef $vgpr0
; SGPR_SPILLED-NEXT: $sgpr32 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 0
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr32, 0, [[DEF]]
; SGPR_SPILLED-NEXT: $sgpr0 = SI_RESTORE_S32_FROM_VGPR [[DEF]], 1
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr2, 1, [[DEF]], implicit-def $sgpr2_sgpr3, implicit $sgpr2_sgpr3
; SGPR_SPILLED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr3, 2, [[DEF]], implicit $sgpr2_sgpr3