From 34f0a8aaba11bf703ddd2de92eee8ecbb77be5c8 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Thu, 21 Mar 2024 04:13:23 -0700 Subject: [PATCH] [SLP]Fix comparison in bitwidth check. Projected bitwidth should be less than the original, not greater. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 2 +- .../orig-btiwidth-les-projected.ll | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/orig-btiwidth-les-projected.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index a52064e5417b..4853c2006fea 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -13995,7 +13995,7 @@ bool BoUpSLP::collectValuesToDemote( if (MultiNodeScalars.contains(V)) return false; uint32_t OrigBitWidth = DL->getTypeSizeInBits(V->getType()); - if (OrigBitWidth < BitWidth) { + if (OrigBitWidth > BitWidth) { APInt Mask = APInt::getBitsSetFrom(OrigBitWidth, BitWidth); if (MaskedValueIsZero(V, Mask, SimplifyQuery(*DL))) return true; diff --git a/llvm/test/Transforms/SLPVectorizer/orig-btiwidth-les-projected.ll b/llvm/test/Transforms/SLPVectorizer/orig-btiwidth-les-projected.ll new file mode 100644 index 000000000000..531e96405348 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/orig-btiwidth-les-projected.ll @@ -0,0 +1,22 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer < %s | FileCheck %s + +define i32 @test(i4 %0) { +; CHECK-LABEL: define i32 @test( +; CHECK-SAME: i4 [[TMP0:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP1:%.*]] = trunc i8 0 to i4 +; CHECK-NEXT: [[TMP2:%.*]] = trunc i8 0 to i4 +; CHECK-NEXT: [[ADD_R:%.*]] = or i4 [[TMP1]], [[TMP0]] +; CHECK-NEXT: [[ADD_R14:%.*]] = or i4 0, [[TMP2]] +; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i4 [[ADD_R]], [[ADD_R14]] +; CHECK-NEXT: ret i32 0 +; +entry: + %1 = trunc i8 0 to i4 + %2 = trunc i8 0 to i4 + %add.r = or i4 %1, %0 + %add.r14 = or i4 0, %2 + %cmp.not = icmp eq i4 %add.r, %add.r14 + ret i32 0 +}