[AMDGPU] Remove trivially true predicates from GCNSubtarget. NFC. (#172830)
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@ -454,30 +454,6 @@ public:
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return getGeneration() == SOUTHERN_ISLANDS;
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}
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bool hasBFE() const {
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return true;
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}
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bool hasBFI() const {
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return true;
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}
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bool hasBFM() const {
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return hasBFE();
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}
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bool hasBCNT(unsigned Size) const {
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return true;
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}
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bool hasFFBL() const {
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return true;
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}
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bool hasFFBH() const {
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return true;
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}
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bool hasMed3_16() const {
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return getGeneration() >= AMDGPUSubtarget::GFX9;
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}
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@ -492,10 +468,6 @@ public:
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bool hasFmaMixBF16Insts() const { return HasFmaMixBF16Insts; }
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bool hasCARRY() const {
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return true;
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}
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bool hasFMA() const {
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return FMA;
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}
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@ -512,21 +512,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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if (Subtarget->hasMadMacF32Insts())
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setOperationAction(ISD::FMAD, MVT::f32, Legal);
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if (!Subtarget->hasBFI())
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// fcopysign can be done in a single instruction with BFI.
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setOperationAction(ISD::FCOPYSIGN, {MVT::f32, MVT::f64}, Expand);
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if (!Subtarget->hasBCNT(32))
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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if (!Subtarget->hasBCNT(64))
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setOperationAction(ISD::CTPOP, MVT::i64, Expand);
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if (Subtarget->hasFFBH())
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setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
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if (Subtarget->hasFFBL())
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setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
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setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
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setOperationAction({ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF}, MVT::i32, Custom);
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// We only really have 32-bit BFE instructions (and 16-bit on VI).
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//
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@ -536,8 +523,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
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// have some pass reduce 64-bit extracts to 32-bit if possible. Extracts that
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// span the midpoint are probably relatively rare, so don't worry about them
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// for now.
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if (Subtarget->hasBFE())
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setHasExtractBitsInsn(true);
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setHasExtractBitsInsn(true);
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// Clamp modifier on add/sub
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if (Subtarget->hasIntClamp())
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