diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s index d273b4bba15d..18ed30e723ec 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Apple/M1-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=apple-m1 -instruction-tables < %p/Inputs/basic-instructions.s 2>&1 | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=apple-m1 -instruction-tables < %p/../Inputs/basic-instructions.s 2>&1 | FileCheck %s # CHECK: warning: found a call in the input assembly sequence. # CHECK-NEXT: note: call instructions are not correctly modeled. Assume a latency of 100cy. diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/M1-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Apple/M1-neon-instructions.s index 25659180f780..c641d109eff5 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Apple/M1-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Apple/M1-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=apple-m1 -instruction-tables < %p/Inputs/neon-instructions.s 2>&1 | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=apple-m1 -instruction-tables < %p/../Inputs/neon-instructions.s 2>&1 | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s index 22c31bf5bbce..ea2ae01c0a93 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Cortex/A57-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a57 -skip-unsupported-instructions=parse-failure -instruction-tables < %p/../Neoverse/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a57 -skip-unsupported-instructions=parse-failure -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/basic-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/basic-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/bf16-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/bf16-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/bf16-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/complxnum-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/complxnum-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/complxnum-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/fp16fml-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fp16fml-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/fp16fml-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/fptoint-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/fptoint-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/fptoint-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/i8mm-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/i8mm-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/i8mm-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/mte-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/mte-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/mte-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/neon-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Apple/Inputs/neon-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/neon-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/rcpc-immo-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/rcpc-immo-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/rcpc-immo-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Inputs/sve-instructions.s similarity index 100% rename from llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/sve-instructions.s rename to llvm/test/tools/llvm-mca/AArch64/Inputs/sve-instructions.s diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/basic-instructions.s deleted file mode 100644 index f0a7bdfe1fa4..000000000000 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/basic-instructions.s +++ /dev/null @@ -1,1448 +0,0 @@ -#------------------------------------------------------------------------------ -# Add/sub (immediate) -#------------------------------------------------------------------------------ - -add w2, w3, #4095 -add w30, w29, #1, lsl #12 -add w13, w5, #4095, lsl #12 -add x5, x7, #1638 -add w20, wsp, #801 -add wsp, wsp, #1104 -add wsp, w30, #4084 -add x0, x24, #291 -add x3, x24, #4095, lsl #12 -add x8, sp, #1074 -add sp, x29, #3816 -sub w0, wsp, #4077 -sub w4, w20, #546, lsl #12 -sub sp, sp, #288 -sub wsp, w19, #16 -adds w13, w23, #291, lsl #12 -cmn w2, #4095 -adds w20, wsp, #0 -cmn x3, #1, lsl #12 -cmp wsp, #2342 -cmp sp, #20, lsl #12 -cmp x30, #4095 -subs x4, sp, #3822 -cmn w3, #291, lsl #12 -cmn wsp, #1365 -cmn sp, #1092, lsl #12 -mov x10, #-63432 - -#------------------------------------------------------------------------------ -# Add-subtract (shifted register) -#------------------------------------------------------------------------------ - -add wsp, wsp, w10 -add x25, x9, w25, uxtb -add w3, w5, w7 -add wzr, w3, w5 -add w20, wzr, w4 -add w4, w6, wzr -add w11, w13, w15 -add w9, w3, wzr, lsl #1 -add w17, w29, w20, lsl #31 -add w21, w22, w23, lsr #0 -add w24, w25, w26, lsr #18 -add w27, w28, w29, lsr #31 -add w2, w3, w4, asr #0 -add w5, w6, w7, asr #21 -add w8, w9, w10, asr #31 -add x3, x5, x7 -add xzr, x3, x5 -add x20, xzr, x4 -add x4, x6, xzr -add x11, x13, x15 -add x9, x3, xzr, lsl #10 -add x17, x29, x20, lsl #3 -add x21, x22, x23, lsr #0 -add x24, x25, x26, lsr #18 -add x27, x28, x29, lsr #63 -add x2, x3, x4, asr #0 -add x5, x6, x7, asr #21 -add x8, x9, x10, asr #63 -adds w3, w5, w7 -adds w17, wsp, w25 -adds x13, x23, w8, uxtb -cmn w3, w5 -adds w20, wzr, w4 -adds w4, w6, wzr -adds w11, w13, w15 -adds w9, w3, wzr, lsl #1 -adds w17, w29, w20, lsl #31 -adds w21, w22, w23, lsr #0 -adds w24, w25, w26, lsr #18 -adds w27, w28, w29, lsr #31 -adds w2, w3, w4, asr #0 -adds w5, w6, w7, asr #21 -adds w8, w9, w10, asr #31 -adds x3, x5, x7 -cmn x3, x5 -adds x20, xzr, x4 -adds x4, x6, xzr -adds x11, x13, x15 -adds x9, x3, xzr, lsl #10 -adds x17, x29, x20, lsl #3 -adds x21, x22, x23, lsr #0 -adds x24, x25, x26, lsr #18 -adds x27, x28, x29, lsr #63 -adds x2, x3, x4, asr #0 -adds x5, x6, x7, asr #21 -adds x8, x9, x10, asr #63 -sub w3, w5, w7 -sub wzr, w3, w5 -sub w4, w6, wzr -sub w11, w13, w15 -sub w9, w3, wzr, lsl #1 -sub w17, w29, w20, lsl #31 -sub w21, w22, w23, lsr #0 -sub w24, w25, w26, lsr #18 -sub w27, w28, w29, lsr #31 -sub w2, w3, w4, asr #0 -sub w5, w6, w7, asr #21 -sub w8, w9, w10, asr #31 -sub x3, x5, x7 -sub xzr, x3, x5 -sub x4, x6, xzr -sub x11, x13, x15 -sub x9, x3, xzr, lsl #10 -sub x17, x29, x20, lsl #3 -sub x21, x22, x23, lsr #0 -sub x24, x25, x26, lsr #18 -sub x27, x28, x29, lsr #63 -sub x2, x3, x4, asr #0 -sub x5, x6, x7, asr #21 -sub x8, x9, x10, asr #63 -sub w13, wsp, w10 -sub x16, x2, w19, uxtb -subs x13, x15, x14, sxtx #1 -subs w3, w5, w7 -cmp w3, w5 -subs w4, w6, wzr -subs w11, w13, w15 -subs w9, w3, wzr, lsl #1 -subs w17, w29, w20, lsl #31 -subs w21, w22, w23, lsr #0 -subs w24, w25, w26, lsr #18 -subs w27, w28, w29, lsr #31 -subs w2, w3, w4, asr #0 -subs w5, w6, w7, asr #21 -subs w8, w9, w10, asr #31 -subs x3, x5, x7 -cmp x3, x5 -subs x4, x6, xzr -subs x11, x13, x15 -subs x9, x3, xzr, lsl #10 -subs x17, x29, x20, lsl #3 -subs x21, x22, x23, lsr #0 -subs x24, x25, x26, lsr #18 -subs x27, x28, x29, lsr #63 -subs x2, x3, x4, asr #0 -subs x5, x6, x7, asr #21 -subs x8, x9, x10, asr #63 -cmn wzr, w4 -cmn w5, wzr -cmn w6, w7 -cmn w8, w9, lsl #1 -cmn w10, w11, lsl #31 -cmn w12, w13, lsr #0 -cmn w14, w15, lsr #21 -cmn w16, w17, lsr #31 -cmn w18, w19, asr #0 -cmn w20, w21, asr #22 -cmn w22, w23, asr #31 -cmn x0, x3 -cmn xzr, x4 -cmn x5, xzr -cmn x6, x7 -cmn x8, x9, lsl #15 -cmn x10, x11, lsl #3 -cmn x12, x13, lsr #0 -cmn x14, x15, lsr #41 -cmn x16, x17, lsr #63 -cmn x18, x19, asr #0 -cmn x20, x21, asr #55 -cmn x22, x23, asr #63 -cmp w0, w3 -cmp wzr, w4 -cmp w5, wzr -cmp w6, w7 -cmp w8, w9, lsl #1 -cmp w10, w11, lsl #31 -cmp w12, w13, lsr #0 -cmp w14, w15, lsr #21 -cmp w18, w19, asr #0 -cmp w20, w21, asr #22 -cmp w22, w23, asr #31 -cmp wsp, w26 -cmp x16, w27, uxtb -cmp x0, x3 -cmp xzr, x4 -cmp x5, xzr -cmp x6, x7 -cmp x8, x9, lsl #15 -cmp x10, x11, lsl #3 -cmp x12, x13, lsr #0 -cmp x14, x15, lsr #41 -cmp x16, x17, lsr #63 -cmp x18, x19, asr #0 -cmp x20, x21, asr #55 -cmp x22, x23, asr #63 -cmp wzr, w0 -cmp xzr, x0 -mov sp, x30 -mov wsp, w20 -mov x11, sp -mov w24, wsp - -#------------------------------------------------------------------------------ -# Add-subtract (shifted register) -#------------------------------------------------------------------------------ - -adc w29, w27, w25 -adc wzr, w3, w4 -adc w9, wzr, w10 -adc w20, w0, wzr -adc x29, x27, x25 -adc xzr, x3, x4 -adc x9, xzr, x10 -adc x20, x0, xzr -adcs w29, w27, w25 -adcs wzr, w3, w4 -adcs w9, wzr, w10 -adcs w20, w0, wzr -adcs x29, x27, x25 -adcs xzr, x3, x4 -adcs x9, xzr, x10 -adcs x20, x0, xzr -sbc w29, w27, w25 -sbc wzr, w3, w4 -ngc w9, w10 -sbc w20, w0, wzr -sbc x29, x27, x25 -sbc xzr, x3, x4 -ngc x9, x10 -sbc x20, x0, xzr -sbcs w29, w27, w25 -sbcs wzr, w3, w4 -ngcs w9, w10 -sbcs w20, w0, wzr -sbcs x29, x27, x25 -sbcs xzr, x3, x4 -ngcs x9, x10 -sbcs x20, x0, xzr -ngc w3, w12 -ngc wzr, w9 -ngc w23, wzr -ngc x29, x30 -ngc xzr, x0 -ngc x0, xzr -ngcs w3, w12 -ngcs wzr, w9 -ngcs w23, wzr -ngcs x29, x30 -ngcs xzr, x0 -ngcs x0, xzr - -#------------------------------------------------------------------------------ -# Compare and branch (immediate) -#------------------------------------------------------------------------------ - -sbfx x1, x2, #3, #2 -asr x3, x4, #63 -asr wzr, wzr, #31 -sbfx w12, w9, #0, #1 -ubfiz x4, x5, #52, #11 -ubfx xzr, x4, #0, #1 -ubfiz x4, xzr, #1, #6 -lsr x5, x6, #12 -bfi x4, x5, #52, #11 -bfxil xzr, x4, #0, #1 -bfi x4, xzr, #1, #6 -bfxil x5, x6, #12, #52 -sxtb w1, w2 -sxtb xzr, w3 -sxth w9, w10 -sxth x0, w1 -sxtw x3, w30 -uxtb w1, w2 -uxth w9, w10 -ubfx x3, x30, #0, #32 -asr w3, w2, #0 -asr w9, w10, #31 -asr x20, x21, #63 -asr w1, wzr, #3 -lsr w3, w2, #0 -lsr w9, w10, #31 -lsr x20, x21, #63 -lsr wzr, wzr, #3 -lsl w9, w10, #31 -lsl x20, x21, #63 -lsl w1, wzr, #3 -sbfiz x2, x3, #63, #1 -sbfiz x9, x10, #5, #59 -sbfiz w11, w12, #31, #1 -sbfiz w13, w14, #29, #3 -sbfiz xzr, xzr, #10, #11 -sbfx w9, w10, #0, #1 -asr x2, x3, #63 -asr x19, x20, #0 -asr x9, x10, #5 -asr w9, w10, #0 -asr w11, w12, #31 -asr w13, w14, #29 -sbfx xzr, xzr, #10, #11 -bfi x2, x3, #63, #1 -bfi x9, x10, #5, #59 -bfi w11, w12, #31, #1 -bfi w13, w14, #29, #3 -bfi xzr, xzr, #10, #11 -bfxil w9, w10, #0, #1 -bfxil x2, x3, #63, #1 -bfxil x19, x20, #0, #64 -bfxil x9, x10, #5, #59 -bfxil w9, w10, #0, #32 -bfxil w11, w12, #31, #1 -bfxil w13, w14, #29, #3 -bfxil xzr, xzr, #10, #11 -lsl x2, x3, #63 -lsl x9, x10, #5 -lsl w11, w12, #31 -lsl w13, w14, #29 -ubfiz xzr, xzr, #10, #11 -ubfx w9, w10, #0, #1 -lsr x2, x3, #63 -lsr x19, x20, #0 -lsr x9, x10, #5 -lsr w9, w10, #0 -lsr w11, w12, #31 -lsr w13, w14, #29 -ubfx xzr, xzr, #10, #11 - -#------------------------------------------------------------------------------ -# Compare and branch (immediate) -#------------------------------------------------------------------------------ - -cbz w5, #4 -cbz x5, #0 -cbnz x2, #-4 -cbnz x26, #1048572 -cbz wzr, #0 -cbnz xzr, #0 -cbnz w21, test - -#------------------------------------------------------------------------------ -# Conditional branch (immediate) -#------------------------------------------------------------------------------ - -b.ne #4 -b.ge #1048572 -b.ge #-4 - -#------------------------------------------------------------------------------ -# Conditional compare (immediate) -#------------------------------------------------------------------------------ - -ccmp w1, #31, #0, eq -ccmp w3, #0, #15, hs -ccmp wzr, #15, #13, hs -ccmp x9, #31, #0, le -ccmp x3, #0, #15, gt -ccmp xzr, #5, #7, ne -ccmn w1, #31, #0, eq -ccmn w3, #0, #15, hs -ccmn wzr, #15, #13, hs -ccmn x9, #31, #0, le -ccmn x3, #0, #15, gt -ccmn xzr, #5, #7, ne - -#------------------------------------------------------------------------------ -# Conditional compare (register) -#------------------------------------------------------------------------------ - -ccmp w1, wzr, #0, eq -ccmp w3, w0, #15, hs -ccmp wzr, w15, #13, hs -ccmp x9, xzr, #0, le -ccmp x3, x0, #15, gt -ccmp xzr, x5, #7, ne -ccmn w1, wzr, #0, eq -ccmn w3, w0, #15, hs -ccmn wzr, w15, #13, hs -ccmn x9, xzr, #0, le -ccmn x3, x0, #15, gt -ccmn xzr, x5, #7, ne - -#------------------------------------------------------------------------------ -# Conditional branch (immediate) -#------------------------------------------------------------------------------ - -csel w1, w0, w19, ne -csel wzr, w5, w9, eq -csel w9, wzr, w30, gt -csel w1, w28, wzr, mi -csel x19, x23, x29, lt -csel xzr, x3, x4, ge -csel x5, xzr, x6, hs -csel x7, x8, xzr, lo -csinc w1, w0, w19, ne -csinc wzr, w5, w9, eq -csinc w9, wzr, w30, gt -csinc w1, w28, wzr, mi -csinc x19, x23, x29, lt -csinc xzr, x3, x4, ge -csinc x5, xzr, x6, hs -csinc x7, x8, xzr, lo -csinv w1, w0, w19, ne -csinv wzr, w5, w9, eq -csinv w9, wzr, w30, gt -csinv w1, w28, wzr, mi -csinv x19, x23, x29, lt -csinv xzr, x3, x4, ge -csinv x5, xzr, x6, hs -csinv x7, x8, xzr, lo -csneg w1, w0, w19, ne -csneg wzr, w5, w9, eq -csneg w9, wzr, w30, gt -csneg w1, w28, wzr, mi -csneg x19, x23, x29, lt -csneg xzr, x3, x4, ge -csneg x5, xzr, x6, hs -csneg x7, x8, xzr, lo -cset w3, eq -cset x9, pl -csetm w20, ne -csetm x30, ge -csinc w2, wzr, wzr, al -csinv x3, xzr, xzr, nv -cinc w3, w5, gt -cinc wzr, w4, le -cset w9, lt -cinc x3, x5, gt -cinc xzr, x4, le -cset x9, lt -csinc w5, w6, w6, nv -csinc x1, x2, x2, al -cinv w3, w5, gt -cinv wzr, w4, le -csetm w9, lt -cinv x3, x5, gt -cinv xzr, x4, le -csetm x9, lt -csinv x1, x0, x0, al -csinv w9, w8, w8, nv -cneg w3, w5, gt -cneg wzr, w4, le -cneg w9, wzr, lt -cneg x3, x5, gt -cneg xzr, x4, le -cneg x9, xzr, lt -csneg x4, x8, x8, al - -#------------------------------------------------------------------------------ -# Data-processing (1 source) -#------------------------------------------------------------------------------ - -rbit w0, w7 -rbit x18, x3 -rev16 w17, w1 -rev16 x5, x2 -rev w18, w0 -rev32 x20, x1 -rev x22, x2 -clz w24, w3 -clz x26, x4 -cls w3, w5 -cls x20, x5 - -#------------------------------------------------------------------------------ -# Data-processing (2 source) -#------------------------------------------------------------------------------ - -udiv w0, w7, w10 -udiv x9, x22, x4 -sdiv w12, w21, w0 -sdiv x13, x2, x1 -lsl w11, w12, w13 -lsl x14, x15, x16 -lsr w17, w18, w19 -lsr x20, x21, x22 -asr w23, w24, w25 -asr x26, x27, x28 -ror w0, w1, w2 -ror x3, x4, x5 -lsl w6, w7, w8 -lsl x9, x10, x11 -lsr w12, w13, w14 -lsr x15, x16, x17 -asr w18, w19, w20 -asr x21, x22, x23 -ror w24, w25, w26 -ror x27, x28, x29 - -#------------------------------------------------------------------------------ -# Data-processing (3 sources) -#------------------------------------------------------------------------------ - -crc32cb w30, w23, w15 -crc32cb w31, w12, w14 -crc32cb w28, w10, w11 -crc32b w27, w12, w15 -crc32h w3, w15, w21 -crc32w w9, w18, w24 -crc32x w19, w6, x25 -crc32ch w25, w26, w16 -crc32cw w27, w12, w23 -crc32cx w21, w28, x5 -smulh x30, x29, x28 -smulh xzr, x27, x26 -umulh x30, x29, x28 -umulh x23, x30, xzr -madd w1, w3, w7, w4 -madd wzr, w0, w9, w11 -madd w13, wzr, w4, w4 -madd w19, w30, wzr, w29 -mul w4, w5, w6 -madd x1, x3, x7, x4 -madd xzr, x0, x9, x11 -madd x13, xzr, x4, x4 -madd x19, x30, xzr, x29 -mul x4, x5, x6 -msub w1, w3, w7, w4 -msub wzr, w0, w9, w11 -msub w13, wzr, w4, w4 -msub w19, w30, wzr, w29 -mneg w4, w5, w6 -msub x1, x3, x7, x4 -msub xzr, x0, x9, x11 -msub x13, xzr, x4, x4 -msub x19, x30, xzr, x29 -mneg x4, x5, x6 -smaddl x3, w5, w2, x9 -smaddl xzr, w10, w11, x12 -smaddl x13, wzr, w14, x15 -smaddl x16, w17, wzr, x18 -smull x19, w20, w21 -smsubl x3, w5, w2, x9 -smsubl xzr, w10, w11, x12 -smsubl x13, wzr, w14, x15 -smsubl x16, w17, wzr, x18 -smnegl x19, w20, w21 -umaddl x3, w5, w2, x9 -umaddl xzr, w10, w11, x12 -umaddl x13, wzr, w14, x15 -umaddl x16, w17, wzr, x18 -umull x19, w20, w21 -umsubl x3, w5, w2, x9 -umsubl x16, w17, wzr, x18 -umnegl x19, w20, w21 -smulh x23, x22, xzr -umulh x23, x22, xzr -mul x19, x20, xzr -mneg w21, w22, w23 -smull x11, w13, w17 -umull x11, w13, w17 -smnegl x11, w13, w17 -umnegl x11, w13, w17 - -#------------------------------------------------------------------------------ -# Extract (immediate) -#------------------------------------------------------------------------------ - -extr w3, w5, w7, #0 -extr w11, w13, w17, #31 -extr x3, x5, x7, #15 -extr x11, x13, x17, #63 -ror x19, x23, #24 -ror x29, xzr, #63 -ror w9, w13, #31 - -#------------------------------------------------------------------------------ -# Floating-point compare -#------------------------------------------------------------------------------ - -fcmp h5, h21 -fcmp h5, #0.0 -fcmpe h22, h21 -fcmpe h13, #0.0 -fcmp s3, s5 -fcmp s31, #0.0 -fcmpe s29, s30 -fcmpe s15, #0.0 -fcmp d4, d12 -fcmp d23, #0.0 -fcmpe d26, d22 -fcmpe d29, #0.0 - -#------------------------------------------------------------------------------ -# Floating-point conditional compare -#------------------------------------------------------------------------------ - -fccmp s1, s31, #0, eq -fccmp s3, s0, #15, hs -fccmp s31, s15, #13, hs -fccmp d9, d31, #0, le -fccmp d3, d0, #15, gt -fccmp d31, d5, #7, ne -fccmp h31, h3, #11, hs -fccmpe h6, h1, #12, ne -fccmpe s1, s31, #0, eq -fccmpe s3, s0, #15, hs -fccmpe s31, s15, #13, hs -fccmpe d9, d31, #0, le -fccmpe d3, d0, #15, gt -fccmpe d31, d5, #7, ne - -#------------------------------------------------------------------------------- -# Floating-point conditional compare -#------------------------------------------------------------------------------- - -fcsel s3, s20, s9, pl -fcsel d9, d10, d11, mi -fcsel h26, h2, h11, hs - -#------------------------------------------------------------------------------ -# Floating-point data-processing (1 source) -#------------------------------------------------------------------------------ - -fmov h18, h28 -fmov s0, s1 -fabs s2, s3 -fneg h2, h9 -fneg s4, s5 -fsqrt s6, s7 -fcvt d8, s9 -fcvt h10, s11 -frintn h12, h3 -frintn s12, s13 -frintp h17, h31 -frintp s14, s15 -frintm h0, h21 -frintm s16, s17 -frintz h10, h29 -frintz s18, s19 -frinta h22, h10 -frinta s20, s21 -frintx h4, h5 -frintx s22, s23 -frinti s24, s25 -frinti h31, h14 -fmov d0, d1 -fabs d2, d3 -fneg d4, d5 -fsqrt h13, h24 -fsqrt d6, d7 -fcvt s8, d9 -fcvt h10, d11 -frintn d12, d13 -frintp d14, d15 -frintm d16, d17 -frintz d18, d19 -frinta d20, d21 -frintx d22, d23 -frinti d24, d25 -fcvt s26, h27 -fcvt d28, h29 - -#------------------------------------------------------------------------------ -# Floating-point data-processing (2 sources) -#------------------------------------------------------------------------------ - -fmul s20, s19, s17 -fdiv h1, h26, h23 -fdiv s1, s2, s3 -fadd h23, h27, h22 -fadd s4, s5, s6 -fsub h20, h11, h18 -fsub s7, s8, s9 -fmax s10, s11, s12 -fmax h8, h7, h11 -fmin s13, s14, s15 -fmaxnm h29, h13, h14 -fmaxnm s16, s17, s18 -fminnm s19, s20, s21 -fnmul h3, h15, h7 -fnmul s22, s23, s2 -fmul d20, d19, d17 -fdiv d1, d2, d3 -fadd d4, d5, d6 -fsub d7, d8, d9 -fmax d10, d11, d12 -fmin d13, d14, d15 -fmin h4, h13, h17 -fmaxnm d16, d17, d18 -fminnm d19, d20, d21 -fminnm h29, h23, h17 -fnmul d22, d23, d24 - -#------------------------------------------------------------------------------ -# Floating-point data-processing (1 source) -#------------------------------------------------------------------------------ - -fmadd h27, h0, h6, h28 -fmadd s3, s5, s6, s31 -fmadd d3, d13, d0, d23 -fmsub h25, h28, h12, h24 -fmsub s3, s5, s6, s31 -fmsub d3, d13, d0, d23 -fnmadd h3, h18, h31, h24 -fnmadd s3, s5, s6, s31 -fnmadd d3, d13, d0, d23 -fnmsub s3, s5, s6, s31 -fnmsub d3, d13, d0, d23 -fnmsub h3, h29, h24, h17 - -#------------------------------------------------------------------------------ -# Floating-point <-> fixed-point conversion -#------------------------------------------------------------------------------ - -fcvtzs w3, h5, #1 -fcvtzs wzr, h20, #13 -fcvtzs w19, h0, #32 -fcvtzs x3, h5, #1 -fcvtzs x12, h30, #45 -fcvtzs x19, h0, #64 -fcvtzs w3, s5, #1 -fcvtzs wzr, s20, #13 -fcvtzs w19, s0, #32 -fcvtzs x3, s5, #1 -fcvtzs x12, s30, #45 -fcvtzs x19, s0, #64 -fcvtzs w3, d5, #1 -fcvtzs wzr, d20, #13 -fcvtzs w19, d0, #32 -fcvtzs x3, d5, #1 -fcvtzs x12, d30, #45 -fcvtzs x19, d0, #64 -fcvtzu w3, h5, #1 -fcvtzu wzr, h20, #13 -fcvtzu w19, h0, #32 -fcvtzu x3, h5, #1 -fcvtzu x12, h30, #45 -fcvtzu x19, h0, #64 -fcvtzu w3, s5, #1 -fcvtzu wzr, s20, #13 -fcvtzu w19, s0, #32 -fcvtzu x3, s5, #1 -fcvtzu x12, s30, #45 -fcvtzu x19, s0, #64 -fcvtzu w3, d5, #1 -fcvtzu wzr, d20, #13 -fcvtzu w19, d0, #32 -fcvtzu x3, d5, #1 -fcvtzu x12, d30, #45 -fcvtzu x19, d0, #64 -scvtf h23, w19, #1 -scvtf h31, wzr, #20 -scvtf h14, w0, #32 -scvtf h23, x19, #1 -scvtf h31, xzr, #20 -scvtf h14, x0, #64 -scvtf s23, w19, #1 -scvtf s31, wzr, #20 -scvtf s14, w0, #32 -scvtf s23, x19, #1 -scvtf s31, xzr, #20 -scvtf s14, x0, #64 -scvtf d23, w19, #1 -scvtf d31, wzr, #20 -scvtf d14, w0, #32 -scvtf d23, x19, #1 -scvtf d31, xzr, #20 -scvtf d14, x0, #64 -ucvtf h23, w19, #1 -ucvtf h31, wzr, #20 -ucvtf h14, w0, #32 -ucvtf h23, x19, #1 -ucvtf h31, xzr, #20 -ucvtf h14, x0, #64 -ucvtf s23, w19, #1 -ucvtf s31, wzr, #20 -ucvtf s14, w0, #32 -ucvtf s23, x19, #1 -ucvtf s31, xzr, #20 -ucvtf s14, x0, #64 -ucvtf d23, w19, #1 -ucvtf d31, wzr, #20 -ucvtf d14, w0, #32 -ucvtf d23, x19, #1 -ucvtf d31, xzr, #20 -ucvtf d14, x0, #64 - -#------------------------------------------------------------------------------ -# Floating-point <-> integer conversion -#------------------------------------------------------------------------------ - -fcvtns w3, h31 -fcvtns xzr, h12 -fcvtnu wzr, h12 -fcvtnu x0, h0 -fcvtps wzr, h9 -fcvtps x12, h20 -fcvtpu w30, h23 -fcvtpu x29, h3 -fcvtms w2, h3 -fcvtms x4, h5 -fcvtmu w6, h7 -fcvtmu x8, h9 -fcvtzs w10, h11 -fcvtzs x12, h13 -fcvtzu w14, h15 -fcvtzu x15, h16 -scvtf h17, w18 -scvtf h19, x20 -ucvtf h21, w22 -scvtf h23, x24 -fcvtas w25, h26 -fcvtas x27, h28 -fcvtau w29, h30 -fcvtau xzr, h0 -fcvtns w3, s31 -fcvtns xzr, s12 -fcvtnu wzr, s12 -fcvtnu x0, s0 -fcvtps wzr, s9 -fcvtps x12, s20 -fcvtpu w30, s23 -fcvtpu x29, s3 -fcvtms w2, s3 -fcvtms x4, s5 -fcvtmu w6, s7 -fcvtmu x8, s9 -fcvtzs w10, s11 -fcvtzs x12, s13 -fcvtzu w14, s15 -fcvtzu x15, s16 -scvtf s17, w18 -scvtf s19, x20 -ucvtf s21, w22 -scvtf s23, x24 -fcvtas w25, s26 -fcvtas x27, s28 -fcvtau w29, s30 -fcvtau xzr, s0 -fcvtns w3, d31 -fcvtns xzr, d12 -fcvtnu wzr, d12 -fcvtnu x0, d0 -fcvtps wzr, d9 -fcvtps x12, d20 -fcvtpu w30, d23 -fcvtpu x29, d3 -fcvtms w2, d3 -fcvtms x4, d5 -fcvtmu w6, d7 -fcvtmu x8, d9 -fcvtzs w10, d11 -fcvtzs x12, d13 -fcvtzu w14, d15 -fcvtzu x15, d16 -scvtf d17, w18 -scvtf d19, x20 -ucvtf d21, w22 -ucvtf d23, x24 -fcvtas w25, d26 -fcvtas x27, d28 -fcvtau w29, d30 -fcvtau xzr, d0 -fmov h6, w5 -fmov h16, x27 -fmov w15, h31 -fmov w3, s9 -fmov s9, w3 -fmov x21, h14 -fmov x20, d31 -fmov d1, x15 -fmov x3, v12.d[1] -fmov v1.d[1], x19 - -#------------------------------------------------------------------------------ -# Floating-point immediate -#------------------------------------------------------------------------------ - -fmov h29, #0.50000000 -fmov s2, #0.12500000 -fmov s3, #1.00000000 -fmov d30, #16.00000000 -fmov s4, #1.06250000 -fmov d10, #1.93750000 -fmov s12, #-1.00000000 -fmov d16, #8.50000000 - -#------------------------------------------------------------------------------ -# Load-register (literal) -#------------------------------------------------------------------------------ - -ldr w3, #0 -ldr x29, #4 -ldrsw xzr, #-4 -ldr s0, #8 -ldr d0, #1048572 -ldr q0, #-1048576 -prfm pldl1strm, #0 -prfm #22, #0 - -#------------------------------------------------------------------------------ -# Load/store exclusive -#------------------------------------------------------------------------------ - -stxrb w18, w8, [sp] -stxrh w24, w15, [x16] -stxr w5, w6, [x17] -stxr w1, x10, [x21] -ldxrb w30, [x0] -ldxrh w17, [x4] -ldxr w22, [sp] -ldxr x11, [x29] -stxp w12, w11, w10, [sp] -stxp wzr, x27, x9, [x12] -ldxp w0, wzr, [sp] -ldxp x17, x0, [x18] -stlxrb w12, w22, [x0] -stlxrh w10, w1, [x1] -stlxr w9, w2, [x2] -stlxr w9, x3, [sp] -ldaxrb w8, [x4] -ldaxrh w7, [x5] -ldaxr w6, [sp] -ldaxr x5, [x6] -stlxp w4, w5, w6, [sp] -stlxp wzr, x6, x7, [x1] -ldaxp w5, w18, [sp] -ldaxp x6, x19, [x22] -stlrb w24, [sp] -stlrh w25, [x30] -stlr w26, [x29] -stlr x27, [x28] -ldarb w16, [x21] -ldarb w23, [sp] -ldarh w22, [x30] -ldar wzr, [x29] -ldar x21, [x28] - -#------------------------------------------------------------------------------ -# Load/store (unscaled immediate) -#------------------------------------------------------------------------------ - -sturb w9, [sp] -sturh wzr, [x12, #255] -stur w16, [x0, #-256] -stur x28, [x14, #1] -ldurb w1, [x20, #255] -ldurh w20, [x1, #255] -ldur w12, [sp, #255] -ldur xzr, [x12, #255] -ldursb x9, [x7, #-256] -ldursh x17, [x19, #-256] -ldursw x20, [x15, #-256] -prfum pldl2keep, [sp, #-256] -ldursb w19, [x1, #-256] -ldursh w15, [x21, #-256] -stur b0, [sp, #1] -stur h12, [x12, #-1] -stur s15, [x0, #255] -stur d31, [x5, #25] -stur q9, [x5] -ldur b3, [sp] -ldur h5, [x4, #-256] -ldur s7, [x12, #-1] -ldur d11, [x19, #4] -ldur q13, [x1, #2] - -#------------------------------------------------------------------------------ -# Load/store (immediate post-indexed) -#------------------------------------------------------------------------------ - -strb w9, [x2], #255 -strb w10, [x3], #1 -strb w10, [x3], #-256 -strh w9, [x2], #255 -strh w9, [x2], #1 -strh w10, [x3], #-256 -str w19, [sp], #255 -str w20, [x30], #1 -str w21, [x12], #-256 -str xzr, [x9], #255 -str x2, [x3], #1 -str x19, [x12], #-256 -ldrb w9, [x2], #255 -ldrb w10, [x3], #1 -ldrb w10, [x3], #-256 -ldrh w9, [x2], #255 -ldrh w9, [x2], #1 -ldrh w10, [x3], #-256 -ldr w19, [sp], #255 -ldr w20, [x30], #1 -ldr w21, [x12], #-256 -ldr xzr, [x9], #255 -ldr x2, [x3], #1 -ldr x19, [x12], #-256 -ldrsb xzr, [x9], #255 -ldrsb x2, [x3], #1 -ldrsb x19, [x12], #-256 -ldrsh xzr, [x9], #255 -ldrsh x2, [x3], #1 -ldrsh x19, [x12], #-256 -ldrsw xzr, [x9], #255 -ldrsw x2, [x3], #1 -ldrsw x19, [x12], #-256 -ldrsb wzr, [x9], #255 -ldrsb w2, [x3], #1 -ldrsb w19, [x12], #-256 -ldrsh wzr, [x9], #255 -ldrsh w2, [x3], #1 -ldrsh w19, [x12], #-256 -str b0, [x0], #255 -str b3, [x3], #1 -str b5, [sp], #-256 -str h10, [x10], #255 -str h13, [x23], #1 -str h15, [sp], #-256 -str s20, [x20], #255 -str s23, [x23], #1 -str s25, [x0], #-256 -str d20, [x20], #255 -str d23, [x23], #1 -str d25, [x0], #-256 -ldr b0, [x0], #255 -ldr b3, [x3], #1 -ldr b5, [sp], #-256 -ldr h10, [x10], #255 -ldr h13, [x23], #1 -ldr h15, [sp], #-256 -ldr s20, [x20], #255 -ldr s23, [x23], #1 -ldr s25, [x0], #-256 -ldr d20, [x20], #255 -ldr d23, [x23], #1 -ldr d25, [x0], #-256 -ldr q20, [x1], #255 -ldr q23, [x9], #1 -ldr q25, [x20], #-256 -str q10, [x1], #255 -str q22, [sp], #1 -str q21, [x20], #-256 - -#------------------------------------------------------------------------------- -# Load-store register (immediate pre-indexed) -#------------------------------------------------------------------------------- - -ldr x3, [x4, #0]! -strb w9, [x2, #255]! -strb w10, [x3, #1]! -strb w10, [x3, #-256]! -strh w9, [x2, #255]! -strh w9, [x2, #1]! -strh w10, [x3, #-256]! -str w19, [sp, #255]! -str w20, [x30, #1]! -str w21, [x12, #-256]! -str xzr, [x9, #255]! -str x2, [x3, #1]! -str x19, [x12, #-256]! -ldrb w9, [x2, #255]! -ldrb w10, [x3, #1]! -ldrb w10, [x3, #-256]! -ldrh w9, [x2, #255]! -ldrh w9, [x2, #1]! -ldrh w10, [x3, #-256]! -ldr w19, [sp, #255]! -ldr w20, [x30, #1]! -ldr w21, [x12, #-256]! -ldr xzr, [x9, #255]! -ldr x2, [x3, #1]! -ldr x19, [x12, #-256]! -ldrsb xzr, [x9, #255]! -ldrsb x2, [x3, #1]! -ldrsb x19, [x12, #-256]! -ldrsh xzr, [x9, #255]! -ldrsh x2, [x3, #1]! -ldrsh x19, [x12, #-256]! -ldrsw xzr, [x9, #255]! -ldrsw x2, [x3, #1]! -ldrsw x19, [x12, #-256]! -ldrsb wzr, [x9, #255]! -ldrsb w2, [x3, #1]! -ldrsb w19, [x12, #-256]! -ldrsh wzr, [x9, #255]! -ldrsh w2, [x3, #1]! -ldrsh w19, [x12, #-256]! -str b0, [x0, #255]! -str b3, [x3, #1]! -str b5, [sp, #-256]! -str h10, [x10, #255]! -str h13, [x23, #1]! -str h15, [sp, #-256]! -str s20, [x20, #255]! -str s23, [x23, #1]! -str s25, [x0, #-256]! -str d20, [x20, #255]! -str d23, [x23, #1]! -str d25, [x0, #-256]! -ldr b0, [x0, #255]! -ldr b3, [x3, #1]! -ldr b5, [sp, #-256]! -ldr h10, [x10, #255]! -ldr h13, [x23, #1]! -ldr h15, [sp, #-256]! -ldr s20, [x20, #255]! -ldr s23, [x23, #1]! -ldr s25, [x0, #-256]! -ldr d20, [x20, #255]! -ldr d23, [x23, #1]! -ldr d25, [x0, #-256]! -ldr q20, [x1, #255]! -ldr q23, [x9, #1]! -ldr q25, [x20, #-256]! -str q10, [x1, #255]! -str q22, [sp, #1]! -str q21, [x20, #-256]! - -#------------------------------------------------------------------------------ -# Load/store (unprivileged) -#------------------------------------------------------------------------------ - -sttrb w9, [sp] -sttrh wzr, [x12, #255] -sttr w16, [x0, #-256] -sttr x28, [x14, #1] -ldtrb w1, [x20, #255] -ldtrh w20, [x1, #255] -ldtr w12, [sp, #255] -ldtr xzr, [x12, #255] -ldtrsb x9, [x7, #-256] -ldtrsh x17, [x19, #-256] -ldtrsw x20, [x15, #-256] -ldtrsb w19, [x1, #-256] -ldtrsh w15, [x21, #-256] - -#------------------------------------------------------------------------------ -# Load/store (unsigned immediate) -#------------------------------------------------------------------------------ - -ldr x4, [x29] -ldr x30, [x12, #32760] -ldr x20, [sp, #8] -ldr xzr, [sp] -ldr w2, [sp] -ldr w17, [sp, #16380] -ldr w13, [x2, #4] -ldrsw x2, [x5, #4] -ldrsw x23, [sp, #16380] -ldrsw x21, [x25, x7] -ldrh w2, [x4] -ldrsh w23, [x6, #8190] -ldrsh wzr, [sp, #2] -ldrsh x29, [x2, #2] -ldrsh x25, [x8, w13, uxtw] -ldrb w26, [x3, #121] -ldrb w12, [x2] -ldrsb w27, [sp, #4095] -ldrsb xzr, [x15] -ldrsb x12, [x28, x27] -str x30, [sp] -str w20, [x4, #16380] -str b5, [x11] -str h23, [x15] -str s25, [x19] -str d15, [x2] -strh w17, [sp, #8190] -strb w23, [x3, #4095] -strb wzr, [x2] -ldr b31, [sp, #4095] -ldr h20, [x2, #8190] -ldr s10, [x19, #16380] -ldr d3, [x10, #32760] -str q12, [sp, #65520] -ldr q14, [x6, #4624] - -#------------------------------------------------------------------------------ -# Load/store (register offset) -#------------------------------------------------------------------------------ - -ldrb w3, [sp, x5] -ldrb w9, [x27, x6] -ldrsb w10, [x30, x7] -ldrb w11, [x29, x3, sxtx] -strb w12, [x28, xzr, sxtx] -strb w5, [x26, w7, uxtw] -ldrb w14, [x26, w6, uxtw] -ldrsb w15, [x25, w7, uxtw] -ldrb w17, [x23, w9, sxtw] -ldrsb x18, [x22, w10, sxtw] -ldrsh w3, [sp, x5] -ldrsh w9, [x27, x6] -ldrh w10, [x30, x7, lsl #1] -strh w11, [x29, x3, sxtx] -ldrh w12, [x28, xzr, sxtx] -ldrsh x13, [x27, x5, sxtx #1] -ldrh w14, [x26, w6, uxtw] -ldrh w15, [x25, w7, uxtw] -ldrsh w16, [x24, w8, uxtw #1] -ldrh w17, [x23, w9, sxtw] -ldrh w18, [x22, w10, sxtw] -strh w19, [x21, wzr, sxtw #1] -ldr b25, [x21, w8, uxtw] -ldr b8, [x30, x10] -str b14, [x13, x25] -str b30, [x16, w26, uxtw] -ldr h3, [sp, x5] -ldr h9, [x27, x6] -ldr h10, [x30, x7, lsl #1] -str h11, [x29, x3, sxtx] -str h12, [x28, xzr, sxtx] -str h13, [x27, x5, sxtx #1] -ldr h14, [x26, w6, uxtw] -ldr h15, [x25, w7, uxtw] -ldr h16, [x24, w8, uxtw #1] -ldr h17, [x23, w9, sxtw] -str h18, [x22, w10, sxtw] -ldr h19, [x21, wzr, sxtw #1] -ldr s12, [x30, w5, uxtw] -ldr d24, [x26, w7, uxtw] -str s20, [x24, w10, uxtw] -str d5, [x26, x6] -ldr w3, [sp, x5] -ldr s9, [x27, x6] -ldr w10, [x30, x7, lsl #2] -ldr w11, [x29, x3, sxtx] -str s12, [x28, xzr, sxtx] -str w13, [x27, x5, sxtx #2] -str w14, [x26, w6, uxtw] -ldr w15, [x25, w7, uxtw] -ldr w16, [x24, w8, uxtw #2] -ldrsw x17, [x23, w9, sxtw] -ldr w18, [x22, w10, sxtw] -ldrsw x19, [x21, wzr, sxtw #2] -ldr x3, [sp, x5] -str x9, [x27, x6] -ldr d10, [x30, x7, lsl #3] -str x11, [x29, x3, sxtx] -ldr x12, [x28, xzr, sxtx] -ldr x13, [x27, x5, sxtx #3] -prfm pldl1keep, [x26, w6, uxtw] -ldr x15, [x25, w7, uxtw] -str x27, [x26, w24, uxtw] -ldr x16, [x24, w8, uxtw #3] -ldr x17, [x23, w9, sxtw] -ldr x18, [x22, w10, sxtw] -str d19, [x21, wzr, sxtw #3] -ldr q3, [sp, x5] -ldr q9, [x27, x6] -ldr q10, [x30, x7, lsl #4] -str q11, [x29, x3, sxtx] -str q12, [x28, xzr, sxtx] -str q13, [x27, x5, sxtx #4] -ldr q14, [x26, w6, uxtw] -ldr q15, [x25, w7, uxtw] -ldr q16, [x24, w8, uxtw #4] -ldr q17, [x23, w9, sxtw] -str q18, [x22, w10, sxtw] -ldr q19, [x21, wzr, sxtw #4] - -#------------------------------------------------------------------------------ -# Load/store register pair (offset) -#------------------------------------------------------------------------------ - -ldp w3, w5, [sp] -stp wzr, w9, [sp, #252] -ldp w2, wzr, [sp, #-256] -ldp w9, w10, [sp, #4] -ldpsw x9, x10, [sp, #4] -ldpsw x9, x10, [x2, #-256] -ldpsw x20, x30, [sp, #252] -ldp x21, x29, [x2, #504] -ldp x22, x23, [x3, #-512] -ldp x24, x25, [x4, #8] -ldp s29, s28, [sp, #252] -stp s27, s26, [sp, #-256] -ldp s1, s2, [x3, #44] -stp d3, d5, [x9, #504] -stp d7, d11, [x10, #-512] -stnp x20, x16, [x8] -stp x3, x6, [x16] -ldp d2, d3, [x30, #-8] -stp q3, q5, [sp] -stp q17, q19, [sp, #1008] -ldp q23, q29, [x1, #-1024] - -#------------------------------------------------------------------------------ -# Load/store register pair (post-indexed) -#------------------------------------------------------------------------------ - -ldp w3, w5, [sp], #0 -stp wzr, w9, [sp], #252 -ldp w2, wzr, [sp], #-256 -ldp w9, w10, [sp], #4 -ldpsw x9, x10, [sp], #4 -ldpsw x9, x10, [x2], #-256 -ldpsw x20, x30, [sp], #252 -ldp x21, x29, [x2], #504 -ldp x22, x23, [x3], #-512 -ldp x24, x25, [x4], #8 -ldp s29, s28, [sp], #252 -stp s27, s26, [sp], #-256 -ldp s1, s2, [x3], #44 -stp d3, d5, [x9], #504 -stp d7, d11, [x10], #-512 -ldp d2, d3, [x30], #-8 -stp q3, q5, [sp], #0 -stp q17, q19, [sp], #1008 -ldp q23, q29, [x1], #-1024 - -#------------------------------------------------------------------------------ -# Load/store register pair (pre-indexed) -#------------------------------------------------------------------------------ - -ldp w3, w5, [sp, #0]! -stp wzr, w9, [sp, #252]! -ldp w2, wzr, [sp, #-256]! -ldp w9, w10, [sp, #4]! -ldpsw x9, x10, [sp, #4]! -ldpsw x9, x10, [x2, #-256]! -ldpsw x20, x30, [sp, #252]! -ldp x21, x29, [x2, #504]! -ldp x22, x23, [x3, #-512]! -ldp x24, x25, [x4, #8]! -ldp s29, s28, [sp, #252]! -stp s27, s26, [sp, #-256]! -ldp s1, s2, [x3, #44]! -stp d3, d5, [x9, #504]! -stp d7, d11, [x10, #-512]! -ldp d2, d3, [x30, #-8]! -stp q3, q5, [sp, #0]! -stp q17, q19, [sp, #1008]! -ldp q23, q29, [x1, #-1024]! - -#------------------------------------------------------------------------------ -# Load/store register pair (offset) -#------------------------------------------------------------------------------ - -ldnp w3, w5, [sp] -stnp wzr, w9, [sp, #252] -ldnp w2, wzr, [sp, #-256] -ldnp w9, w10, [sp, #4] -ldnp x21, x29, [x2, #504] -ldnp x22, x23, [x3, #-512] -ldnp x24, x25, [x4, #8] -ldnp s29, s28, [sp, #252] -stnp s27, s26, [sp, #-256] -ldnp s1, s2, [x3, #44] -stnp d3, d5, [x9, #504] -stnp d7, d11, [x10, #-512] -ldnp d2, d3, [x30, #-8] -stnp q3, q5, [sp] -stnp q17, q19, [sp, #1008] -ldnp q23, q29, [x1, #-1024] - -#------------------------------------------------------------------------------ -# Logical (immediate) -#------------------------------------------------------------------------------ - -and wsp, w16, #0xe00 -and x2, x22, #0x1e00 -ands w14, w8, #0x70 -ands x4, x10, #0x60 -eor wsp, w4, #0xe00 -eor x27, x25, #0x1e00 -mov w3, #983055 -mov x10, #-6148914691236517206 - -#------------------------------------------------------------------------------ -# Logical (shifted register) -#------------------------------------------------------------------------------ - -and w12, w23, w21 -and w16, w15, w1, lsl #1 -and w9, w4, w10, lsl #31 -and w3, w30, w11 -and x3, x5, x7, lsl #63 -and x5, x14, x19, asr #4 -and w3, w17, w19, ror #31 -and w0, w2, wzr, lsr #17 -and w3, w30, w11, asr #2 -and xzr, x4, x26 -and w3, wzr, w20, ror #2 -and x7, x20, xzr, asr #63 -bic x13, x20, x14, lsl #47 -bic w2, w7, w9 -eon w29, w4, w19 -eon x19, x12, x2 -eor w8, w27, w2 -eor x22, x16, x6 -orr w2, w7, w0, asr #31 -orr x8, x9, x10, lsl #12 -orn x3, x5, x7, asr #2 -orn w2, w5, w29 -ands w7, wzr, w9, lsl #1 -ands x3, x5, x20, ror #63 -bics w3, w5, w7 -bics x3, xzr, x3, lsl #1 -tst w3, w7, lsl #31 -tst x2, x20, asr #2 -mov x3, x6 -mov x3, xzr -mov wzr, w2 -mov w3, w5 - -#------------------------------------------------------------------------------ -# Move wide (immediate) -#------------------------------------------------------------------------------ - -movz w2, #0, lsl #16 -mov w2, #-1235 -mov x2, #5299989643264 -mov x2, #0 -movk w3, #0 -movz x4, #0, lsl #16 -movk w5, #0, lsl #16 -movz x6, #0, lsl #32 -movk x7, #0, lsl #32 -movz x8, #0, lsl #48 -movk x9, #0, lsl #48 - -#------------------------------------------------------------------------------ -# Move immediate to Special Register -#------------------------------------------------------------------------------ - -msr DAIFSet, #0 - -#------------------------------------------------------------------------------ -# PC-relative addressing -#------------------------------------------------------------------------------ - -adr x2, #1600 -adrp x21, #6553600 -adr x0, #262144 - -#------------------------------------------------------------------------------ -# Test and branch (immediate) -#------------------------------------------------------------------------------ - -tbz x12, #62, #0 -tbz x12, #62, #4 -tbz x12, #62, #-32768 -tbz w17, #16, test -tbnz x12, #60, #32764 -tbnz w3, #28, test - -#------------------------------------------------------------------------------ -# Unconditional branch (immediate) -#------------------------------------------------------------------------------ - -b #4 -b #-4 -b #134217724 -bl test - -#------------------------------------------------------------------------------ -# Unconditional branch (register) -#------------------------------------------------------------------------------ - -br x20 -blr xzr -ret x10 -ret -eret -drps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/neon-instructions.s deleted file mode 100644 index b034633a80e6..000000000000 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/Inputs/neon-instructions.s +++ /dev/null @@ -1,1559 +0,0 @@ -abs d29, d24 -abs v0.16b, v0.16b -abs v0.2d, v0.2d -abs v0.2s, v0.2s -abs v0.4h, v0.4h -abs v0.4s, v0.4s -abs v0.8b, v0.8b -abs v0.8h, v0.8h -add d17, d31, d29 -add v0.8b, v0.8b, v0.8b -addhn v0.2s, v0.2d, v0.2d -addhn v0.4h, v0.4s, v0.4s -addhn v0.8b, v0.8h, v0.8h -addhn2 v0.16b, v0.8h, v0.8h -addhn2 v0.4s, v0.2d, v0.2d -addhn2 v0.8h, v0.4s, v0.4s -addp v7.2s, v1.2s, v2.2s -addp v0.2d, v0.2d, v0.2d -addp v0.8b, v0.8b, v0.8b -addp d1, v14.2d -addv s0, v0.4s -addv h0, v0.4h -addv h0, v0.8h -addv b0, v0.8b -addv b0, v0.16b -aesd v0.16b, v0.16b -aese v0.16b, v0.16b -aesimc v0.16b, v0.16b -aesmc v0.16b, v0.16b -and v0.8b, v0.8b, v0.8b -bic v0.4h, #15, lsl #8 -bic v23.8h, #101 -bic v0.8b, v0.8b, v0.8b -bic v25.16b, v10.16b, v9.16b -bic v24.2s, #70 -bit v5.8b, v12.8b, v22.8b -bif v0.8b, v25.8b, v4.8b -bif v0.16b, v0.16b, v0.16b -bit v0.16b, v0.16b, v0.16b -bsl v0.8b, v0.8b, v0.8b -bsl v27.16b, v13.16b, v21.16b -cls v0.16b, v0.16b -cls v0.2s, v0.2s -cls v0.4h, v0.4h -cls v0.4s, v0.4s -cls v0.8b, v0.8b -cls v0.8h, v0.8h -clz v0.16b, v0.16b -clz v0.2s, v0.2s -clz v0.4h, v0.4h -clz v0.4s, v0.4s -clz v0.8b, v0.8b -clz v0.8h, v0.8h -cmeq v9.8h, v16.8h, v24.8h -cmeq v14.4h, v18.4h, #0 -cmeq d20, d21, 0 -cmeq d20, d21, d22 -cmeq v0.16b, v0.16b, 0 -cmeq v0.16b, v0.16b, v0.16b -cmge v22.8h, v16.8h, v3.8h -cmge v22.16b, v30.16b, #0 -cmge d20, d21, 0 -cmge d20, d21, d22 -cmge v0.4h, v0.4h, v0.4h -cmge v0.8b, v0.8b, 0 -cmgt v3.2d, v29.2d, v11.2d -cmgt d20, d21, 0 -cmgt d20, d21, d22 -cmgt v0.2s, v0.2s, 0 -cmgt v0.4s, v0.4s, v0.4s -cmhi v28.4h, v25.4h, v21.4h -cmhi d20, d21, d22 -cmhi v0.8h, v0.8h, v0.8h -cmhs d20, d21, d22 -cmhs v0.8b, v0.8b, v0.8b -cmle v21.2s, v19.2s, #0 -cmle d20, d21, 0 -cmle v0.2d, v0.2d, 0 -cmlt v26.4h, v12.4h, #0 -cmlt d20, d21, 0 -cmlt v0.8h, v0.8h, 0 -cmtst d20, d21, d22 -cmtst v0.2s, v0.2s, v0.2s -cmtst v13.2d, v13.2d, v13.2d -cnt v0.16b, v0.16b -cnt v0.8b, v0.8b -dup v0.16b,w28 -dup v0.2d,x28 -dup v0.2s,w28 -dup v0.4h,w28 -dup v0.4s,w28 -dup v0.8b,w28 -dup v0.8h,w28 -dup b0, v0.b[1] -dup d0, v0.d[1] -dup h0, v0.h[1] -dup s0, v0.s[1] -dup v0.16b, v0.b[1] -dup v0.2d, v0.d[1] -dup v0.2s, v0.s[1] -dup v0.4h, v0.h[1] -dup v0.4s, v0.s[1] -dup v0.8b, v0.b[1] -dup v0.8h, v0.h[1] -eor v0.16b, v0.16b, v0.16b -ext v0.16b, v0.16b, v0.16b, #3 -ext v0.8b, v0.8b, v0.8b, #3 -fabd d29, d24, d20 -fabd s29, s24, s20 -fabd h27, h20, h17 -fabd v13.8h, v28.8h, v12.8h -fabd v0.4s, v0.4s, v0.4s -fabs h25, h7 -fabs v0.2d, v0.2d -fabs v0.2s, v0.2s -fabs v0.4h, v0.4h -fabs v0.4s, v0.4s -fabs v0.8h, v0.8h -facge d20, d21, d22 -facge s10, s11, s12 -facge h24, h26, h29 -facge v25.4h, v16.4h, v11.4h -facge v19.2s, v24.2s, v5.2s -facge v0.4s, v0.4s, v0.4s -facgt d20, d21, d22 -facgt s10, s11, s12 -facgt h0, h4, h10 -facgt v0.2d, v0.2d, v0.2d -facgt v22.8h, v14.8h, v31.8h -facgt v22.4s, v8.4s, v2.4s -fadd v0.4s, v0.4s, v0.4s -faddp h10, v19.2h -faddp d11, v28.2d -faddp v0.2s, v0.2s, v0.2s -faddp v0.4s, v0.4s, v0.4s -faddp v16.2d, v11.2d, v5.2d -fcmeq h30, h6, h1 -fcmeq h19, h23, #0.0 -fcmeq d20, d21, #0.0 -fcmeq d20, d21, d22 -fcmeq s10, s11, #0.0 -fcmeq s10, s11, s12 -fcmeq v0.2s, v0.2s, #0.0 -fcmeq v0.2s, v0.2s, v0.2s -fcmeq v12.4s, v11.4s, v26.4s -fcmeq v18.2d, v17.2d, #0.0 -fcmge h10, h23, #0.0 -fcmge h1, h16, h12 -fcmge d20, d21, #0.0 -fcmge d20, d21, d22 -fcmge s10, s11, #0.0 -fcmge s10, s11, s12 -fcmge v0.2d, v0.2d, #0.0 -fcmge v17.2d, v11.2d, v13.2d -fcmge v0.4s, v0.4s, v0.4s -fcmge v18.4h, v27.4h, #0.0 -fcmge v20.8h, v19.8h, v22.8h -fcmge v17.2s, v11.2s, #0.0 -fcmgt h4, h5, h0 -fcmgt h0, h18, #0.0 -fcmgt d20, d21, #0.0 -fcmgt d20, d21, d22 -fcmgt s10, s11, #0.0 -fcmgt s10, s11, s12 -fcmgt v0.4s, v0.4s, #0.0 -fcmgt v0.4s, v0.4s, v0.4s -fcmgt v24.8h, v24.8h, v28.8h -fcmgt v0.8h, v11.8h, #0.0 -fcmgt v19.2d, v31.2d, #0.0 -fcmle v16.8h, v11.8h, #0.0 -fcmle v22.4s, v30.4s, #0.0 -fcmle d20, d21, #0.0 -fcmle s10, s11, #0.0 -fcmle v0.2d, v0.2d, #0.0 -fcmle h18, h28, #0.0 -fcmlt h23, h7, #0.0 -fcmlt d20, d21, #0.0 -fcmlt s10, s11, #0.0 -fcmlt v0.4s, v0.4s, #0.0 -fcmlt v8.4h, v2.4h, #0.0 -fcmlt v7.2d, v16.2d, #0.0 -fcvtas d21, d14 -fcvtas s12, s13 -fcvtas h12, h13 -fcvtas v0.2d, v0.2d -fcvtas v0.2s, v0.2s -fcvtas v0.4h, v0.4h -fcvtas v0.4s, v0.4s -fcvtas v0.8h, v0.8h -fcvtau d21, d14 -fcvtau s12, s13 -fcvtau h12, h13 -fcvtau v0.2d, v0.2d -fcvtau v0.2s, v0.2s -fcvtau v0.4h, v0.4h -fcvtau v0.4s, v0.4s -fcvtau v0.8h, v0.8h -fcvtl v0.2d, v0.2s -fcvtl v0.4s, v0.4h -fcvtl2 v0.2d, v0.4s -fcvtl2 v0.4s, v0.8h -fcvtms d21, d14 -fcvtms s22, s13 -fcvtms h22, h13 -fcvtms v0.2d, v0.2d -fcvtms v0.2s, v0.2s -fcvtms v0.4h, v0.4h -fcvtms v0.4s, v0.4s -fcvtms v0.8h, v0.8h -fcvtmu d21, d14 -fcvtmu s12, s13 -fcvtmu h12, h13 -fcvtmu v0.2d, v0.2d -fcvtmu v0.2s, v0.2s -fcvtmu v0.4h, v0.4h -fcvtmu v0.4s, v0.4s -fcvtmu v0.8h, v0.8h -fcvtn v0.2s, v0.2d -fcvtn v0.4h, v0.4s -fcvtn2 v0.4s, v0.2d -fcvtn2 v0.8h, v0.4s -fcvtns d21, d14 -fcvtns s22, s13 -fcvtns h22, h13 -fcvtns v0.2d, v0.2d -fcvtns v0.2s, v0.2s -fcvtns v0.4h, v0.4h -fcvtns v0.4s, v0.4s -fcvtns v0.8h, v0.8h -fcvtnu d21, d14 -fcvtnu s12, s13 -fcvtnu h12, h13 -fcvtnu v0.2d, v0.2d -fcvtnu v0.2s, v0.2s -fcvtnu v0.4h, v0.4h -fcvtnu v0.4s, v0.4s -fcvtnu v0.8h, v0.8h -fcvtps d21, d14 -fcvtps s22, s13 -fcvtps h22, h13 -fcvtps v0.2d, v0.2d -fcvtps v0.2s, v0.2s -fcvtps v0.4h, v0.4h -fcvtps v0.4s, v0.4s -fcvtps v0.8h, v0.8h -fcvtpu d21, d14 -fcvtpu s12, s13 -fcvtpu h12, h13 -fcvtpu v0.2d, v0.2d -fcvtpu v0.2s, v0.2s -fcvtpu v0.4h, v0.4h -fcvtpu v0.4s, v0.4s -fcvtpu v0.8h, v0.8h -fcvtxn s22, d13 -fcvtxn v0.2s, v0.2d -fcvtxn2 v0.4s, v0.2d -fcvtzs d21, d12, #1 -fcvtzs d21, d14 -fcvtzs s12, s13 -fcvtzs s21, s12, #1 -fcvtzs h21, h14 -fcvtzs h21, h12, #1 -fcvtzs v0.2d, v0.2d -fcvtzs v0.2d, v0.2d, #3 -fcvtzs v0.2s, v0.2s -fcvtzs v0.2s, v0.2s, #3 -fcvtzs v0.4h, v0.4h -fcvtzs v20.4h, v24.4h, #11 -fcvtzs v0.4s, v0.4s -fcvtzs v0.4s, v0.4s, #3 -fcvtzs v0.8h, v0.8h -fcvtzs v18.8h, v10.8h, #7 -fcvtzu d21, d12, #1 -fcvtzu d21, d14 -fcvtzu s12, s13 -fcvtzu s21, s12, #1 -fcvtzu h12, h13 -fcvtzu h21, h12, #1 -fcvtzu v0.2d, v0.2d -fcvtzu v0.2d, v0.2d, #3 -fcvtzu v0.2s, v0.2s -fcvtzu v0.2s, v0.2s, #3 -fcvtzu v0.4h, v0.4h -fcvtzu v19.4h, v26.4h, #9 -fcvtzu v0.4s, v0.4s -fcvtzu v0.4s, v0.4s, #3 -fcvtzu v0.8h, v0.8h -fcvtzu v27.8h, v6.8h, #11 -fdiv v0.2d, v0.2d, v0.2d -fdiv v0.2s, v0.2s, v0.2s -fdiv v0.4h, v0.4h, v0.4h -fdiv v0.4s, v0.4s, v0.4s -fdiv v0.8h, v0.8h, v0.8h -fmax v0.2d, v0.2d, v0.2d -fmax v0.2s, v0.2s, v0.2s -fmax v0.4s, v0.4s, v0.4s -fmaxnm v0.2d, v0.2d, v0.2d -fmaxnm v0.2s, v0.2s, v0.2s -fmaxnm v0.4s, v0.4s, v0.4s -fmaxnmp h25, v19.2h -fmaxnmp d17, v29.2d -fmaxnmp v0.2d, v0.2d, v0.2d -fmaxnmp v0.2s, v0.2s, v0.2s -fmaxnmp v0.4s, v0.4s, v0.4s -fmaxnmv h0, v13.4h -fmaxnmv h12, v11.8h -fmaxnmv s28, v31.4s -fmaxp v0.2d, v0.2d, v0.2d -fmaxp v0.2s, v0.2s, v0.2s -fmaxp v0.4s, v0.4s, v0.4s -fmaxp h15, v25.2h -fmaxp s6, v2.2s -fmaxv h0, v0.4h -fmaxv h0, v0.8h -fmaxv s0, v0.4s -fmin v0.2d, v0.2d, v0.2d -fmin v0.2s, v0.2s, v0.2s -fmin v0.4s, v0.4s, v0.4s -fminnm v0.2d, v0.2d, v0.2d -fminnm v0.2s, v0.2s, v0.2s -fminnm v0.4s, v0.4s, v0.4s -fminnmp h20, v14.2h -fminnmp d15, v8.2d -fminnmp v0.2d, v0.2d, v0.2d -fminnmp v0.2s, v0.2s, v0.2s -fminnmp v0.4s, v0.4s, v0.4s -fminnmv h19, v25.4h -fminnmv h23, v17.8h -fminnmv s29, v17.4s -fminp v0.2d, v0.2d, v0.2d -fminp v0.2s, v0.2s, v0.2s -fminp v0.4s, v0.4s, v0.4s -fminp h7, v10.2h -fminp s17, v7.2s -fminv h3, v30.4h -fminv h29, v12.8h -fminv s16, v19.4s -fmla d0, d1, v0.d[1] -fmla h23, h24, v15.h[4] -fmla s0, s1, v0.s[3] -fmla v0.2s, v0.2s, v0.2s -fmla v29.8h, v15.8h, v10.h[4] -fmla v2.2s, v16.2s, v28.s[0] -fmla v14.4s, v14.4s, v5.s[3] -fmla v1.4s, v24.4s, v12.4s -fmla v10.2d, v14.2d, v21.d[1] -fmls d0, d4, v0.d[1] -fmls h8, h14, v7.h[4] -fmls s3, s5, v0.s[3] -fmls v0.2s, v0.2s, v0.2s -fmls v30.8h, v18.8h, v4.h[6] -fmls v10.2s, v27.2s, v0.s[0] -fmls v27.4s, v7.4s, v24.s[0] -fmls v10.2d, v22.2d, v29.d[0] -fmls v6.8h, v15.8h, v23.8h -fmov v0.2d, #-1.25 -fmov v0.2s, #13.0 -fmov v0.4s, #1.0 -fmul h18, h4, v7.h[3] -fmul v10.4h, v2.4h, v7.h[5] -fmul v5.2s, v12.2s, v9.s[0] -fmul v15.4s, v30.4s, v2.s[3] -fmul v11.2d, v31.2d, v24.d[1] -fmul h28, h14, h3 -fmul d0, d1, v0.d[1] -fmul s0, s1, v0.s[3] -fmul v0.2s, v0.2s, v0.2s -fmulx d0, d4, v0.d[1] -fmulx d23, d11, d1 -fmulx s20, s22, s15 -fmulx h18, h17, v7.h[1] -fmulx h20, h25, h0 -fmulx s3, s5, v0.s[3] -fmulx v0.2d, v0.2d, v0.2d -fmulx v28.4h, v25.4h, v15.h[1] -fmulx v3.2s, v22.2s, v23.s[3] -fmulx v0.2s, v0.2s, v0.2s -fmulx v0.4s, v0.4s, v0.4s -fmulx v5.4s, v28.4s, v15.s[3] -fmulx v22.2d, v18.2d, v25.d[1] -fneg v0.2d, v0.2d -fneg v0.2s, v0.2s -fneg v0.4h, v0.4h -fneg v0.4s, v0.4s -fneg v0.8h, v0.8h -frecpe h20, h8 -frecpe d13, d13 -frecpe s19, s14 -frecpe v0.2d, v0.2d -frecpe v0.2s, v0.2s -frecpe v0.4h, v0.4h -frecpe v0.4s, v0.4s -frecpe v0.8h, v0.8h -frecps h29, h19, h8 -frecpx h18, h11 -frecps v12.8h, v25.8h, v4.8h -frecps v0.4s, v0.4s, v0.4s -frecps d22, d30, d21 -frecps s21, s16, s13 -frecps v7.2d, v29.2d, v18.2d -frecpx d16, d19 -frecpx s18, s10 -frinta v0.2d, v0.2d -frinta v0.2s, v0.2s -frinta v0.4h, v0.4h -frinta v0.4s, v0.4s -frinta v0.8h, v0.8h -frinti v0.2d, v0.2d -frinti v0.2s, v0.2s -frinti v0.4h, v0.4h -frinti v0.4s, v0.4s -frinti v0.8h, v0.8h -frintm v0.2d, v0.2d -frintm v0.2s, v0.2s -frintm v0.4h, v0.4h -frintm v0.4s, v0.4s -frintm v0.8h, v0.8h -frintn v0.2d, v0.2d -frintn v0.2s, v0.2s -frintn v0.4h, v0.4h -frintn v0.4s, v0.4s -frintn v0.8h, v0.8h -frintp v0.2d, v0.2d -frintp v0.2s, v0.2s -frintp v0.4h, v0.4h -frintp v0.4s, v0.4s -frintp v0.8h, v0.8h -frintx v0.2d, v0.2d -frintx v0.2s, v0.2s -frintx v0.4h, v0.4h -frintx v0.4s, v0.4s -frintx v0.8h, v0.8h -frintz v0.2d, v0.2d -frintz v0.2s, v0.2s -frintz v0.4h, v0.4h -frintz v0.4s, v0.4s -frintz v0.8h, v0.8h -frsqrte h23, h26 -frsqrte d21, d12 -frsqrte s22, s13 -frsqrte v0.2d, v0.2d -frsqrte v0.2s, v0.2s -frsqrte v0.4h, v0.4h -frsqrte v0.4s, v0.4s -frsqrts v20.4s, v26.4s, v27.4s -frsqrts v8.4h, v9.4h, v30.4h -frsqrte v0.8h, v0.8h -frsqrts h28, h26, h1 -frsqrts d8, d22, d18 -frsqrts s21, s5, s12 -frsqrts v0.2d, v0.2d, v0.2d -fsqrt v0.2d, v0.2d -fsqrt v0.2s, v0.2s -fsqrt v0.4h, v0.4h -fsqrt v0.4s, v0.4s -fsqrt v0.8h, v0.8h -fsub v13.8h, v15.8h, v17.8h -fsub v0.2s, v0.2s, v0.2s -ld1 { v0.16b }, [x0] -ld1 { v0.16b, v1.16b }, [x14] -ld1 { v19.16b, v20.16b, v21.16b }, [x10] -ld1 { v13.16b, v14.16b, v15.16b, v16.16b }, [x9] -ld1 { v24.8h }, [x27] -ld1 { v1.8h, v2.8h }, [x27] -ld1 { v0.8h, v1.8h }, [sp], #32 -ld1 { v21.8h, v22.8h, v23.8h }, [x22] -ld1 { v0.8h, v1.8h, v2.8h, v3.8h }, [x21] -ld1 { v3.4s }, [x4] -ld1 { v11.4s, v12.4s }, [x30] -ld1 { v0.4s, v1.4s, v2.4s }, [x24] -ld1 { v15.4s, v16.4s, v17.4s, v18.4s }, [x28] -ld1 { v0.4s, v1.4s, v2.4s }, [x0], #48 -ld1 { v3.2d }, [x28] -ld1 { v13.2d, v14.2d }, [x13] -ld1 { v12.2d, v13.2d, v14.2d }, [x15] -ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 -ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] -ld1 { v0.1d }, [x15], x2 -ld1 { v27.1d, v28.1d }, [x7] -ld1 { v14.1d, v15.1d, v16.1d }, [x3] -ld1 { v22.1d, v23.1d, v24.1d, v25.1d }, [x4] -ld1 { v0.2s, v1.2s }, [x15] -ld1 { v16.2s, v17.2s, v18.2s }, [x27] -ld1 { v21.2s, v22.2s, v23.2s, v24.2s }, [x21] -ld1 { v25.4h, v26.4h }, [x3] -ld1 { v20.4h, v21.4h, v22.4h, v23.4h }, [x15] -ld1 { v0.4h, v1.4h, v2.4h }, [sp] -ld1 { v24.8b, v25.8b }, [x6] -ld1 { v7.8b, v8.8b, v9.8b }, [x12] -ld1 { v4.8b, v5.8b, v6.8b, v7.8b }, [x13] -ld1 { v0.4s, v1.4s }, [sp], #32 -ld1 { v0.4s, v1.4s, v2.4s }, [sp] -ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 -ld1 { v0.b }[7], [x0] -ld1 { v0.h }[3], [x0], #2 -ld1 { v18.h }[3], [x1] -ld1 { v0.s }[1], [x15] -ld1 { v0.d }[0], [x15], #8 -ld1 { v11.d }[0], [x13] -ld1 { v0.8h }, [x15], x2 -ld1 { v0.8h, v1.8h }, [x15] -ld1 { v0.b }[9], [x0] -ld1 { v0.b }[9], [x0], #1 -ld1r { v0.16b }, [x0] -ld1r { v0.8h }, [x0], #2 -ld1r { v0.4s }, [x15] -ld1r { v3.1d }, [x15] -ld1r { v0.2d }, [x15], x16 -ld1r { v18.2d }, [x0] -ld1r { v8.8b }, [x23] -ld1r { v28.4h }, [x9] -ld1r { v3.8h }, [x16] -ld1r { v10.2s }, [x20] -ld2 { v0.4h, v1.4h }, [x21] -ld2 { v8.8h, v9.8h }, [x28] -ld2 { v2.2s, v3.2s }, [x16] -ld2 { v22.4s, v23.4s }, [x4] -ld2 { v22.2d, v23.2d }, [x17] -ld2 { v29.b, v30.b }[3], [x1] -ld2 { v26.s, v27.s }[1], [x17] -ld2 { v1.d, v2.d }[0], [x10] -ld2 { v0.16b, v1.16b }, [x0] -ld2 { v13.8b, v14.8b }, [x4] -ld2 { v0.8b, v1.8b }, [x0], #16 -ld1r { v0.16b }, [x0], #1 -ld1r { v0.8h }, [x15] -ld1r { v0.8h }, [x15], #2 -ld2 { v0.16b, v1.16b }, [x0], x1 -ld2 { v0.8b, v1.8b }, [x0] -ld2 { v0.h, v1.h }[7], [x15] -ld2 { v0.h, v1.h }[7], [x15], x8 -ld2 { v0.h, v1.h }[7], [x15], #4 -ld2r { v0.8b, v1.8b }, [x0] -ld2r { v10.16b, v11.16b }, [x23] -ld2r { v0.4h, v1.4h }, [x0], #4 -ld2r { v25.4h, v26.4h }, [x11] -ld2r { v23.8h, v24.8h }, [x10] -ld2r { v0.2s, v1.2s }, [sp] -ld2r { v8.4s, v9.4s }, [x17] -ld2r { v0.1d, v1.1d }, [sp], x8 -ld2r { v9.1d, v10.1d }, [x25] -ld2r { v26.2d, v27.2d }, [x8] -ld3 { v8.8b, v9.8b, v10.8b }, [x0] -ld3 { v15.16b, v16.16b, v17.16b }, [x5] -ld2r { v0.2d, v1.2d }, [x0] -ld2r { v0.2d, v1.2d }, [x0], #16 -ld2r { v0.4s, v1.4s }, [sp] -ld2r { v0.4s, v1.4s }, [sp], #8 -ld3 { v0.4h, v1.4h, v2.4h }, [x15] -ld3 { v0.8h, v1.8h, v2.8h }, [x15], #48 -ld3 { v7.8h, v8.8h, v9.8h }, [x21] -ld3 { v16.2s, v17.2s, v18.2s }, [x0] -ld3 { v12.4s, v13.4s, v14.4s }, [x25] -ld3 { v17.b, v18.b, v19.b }[2], [x27] -ld3 { v18.h, v19.h, v20.h }[5], [x16] -ld3 { v10.2d, v11.2d, v12.2d }, [x18] -ld3 { v0.8h, v1.8h, v2.8h }, [x15], x2 -ld3 { v0.s, v1.s, v2.s }[3], [sp] -ld3 { v0.s, v1.s, v2.s }[3], [sp], x3 -ld3 { v5.d, v6.d, v7.d }[1], [x14] -ld3r { v0.8b, v1.8b, v2.8b }, [x15] -ld3r { v17.16b, v18.16b, v19.16b }, [x3] -ld3r { v0.4h, v1.4h, v2.4h }, [x15] -ld3r { v0.4h, v1.4h, v2.4h }, [x15], #6 -ld3r { v3.4h, v4.4h, v5.4h }, [x1] -ld3r { v6.8h, v7.8h, v8.8h }, [x28] -ld3r { v0.2s, v1.2s, v2.2s }, [x0] -ld3r { v28.4s, v29.4s, v30.4s }, [x2] -ld3r { v0.1d, v1.1d, v2.1d }, [x0], x0 -ld3r { v1.1d, v2.1d, v3.1d }, [x28] -ld3r { v8.2d, v9.2d, v10.2d }, [x3] -ld4 { v6.8b, v7.8b, v8.8b, v9.8b }, [x27] -ld4 { v11.16b, v12.16b, v13.16b, v14.16b }, [x5] -ld4 { v21.4h, v22.4h, v23.4h, v24.4h }, [x14] -ld4 { v9.8h, v10.8h, v11.8h, v12.8h }, [x1] -ld4 { v17.4s, v18.4s, v19.4s, v20.4s }, [x4] -ld3r { v0.8b, v1.8b, v2.8b }, [x0] -ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 -ld4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] -ld4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 -ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] -ld4 { v2.2d, v3.2d, v4.2d, v5.2d }, [x24] -ld4 { v4.b, v5.b, v6.b, v7.b }[12], [x27] -ld4 { v5.h, v6.h, v7.h, v8.h }[0], [x4] -ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 -ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 -ld4 { v0.s, v1.s, v2.s, v3.s }[0], [x26] -ld4r { v20.8b, v21.8b, v22.8b, v23.8b }, [x23] -ld4r { v1.16b, v2.16b, v3.16b, v4.16b }, [x25] -ld4r { v16.4h, v17.4h, v18.4h, v19.4h }, [x6] -ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp] -ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [sp] -ld4r { v4.8h, v5.8h, v6.8h, v7.8h }, [x23] -ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [x30] -ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], #16 -ld4r { v7.4s, v8.4s, v9.4s, v10.4s }, [x23] -ld4r { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], x8 -ld4r { v0.1d, v1.1d, v2.1d, v3.1d }, [sp], x7 -ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] -ld4r { v0.2s, v1.2s, v2.2s, v3.2s }, [sp], x30 -mla v0.8b, v0.8b, v0.8b -mla v15.8h, v22.8h, v4.h[3] -mla v28.2s, v10.2s, v2.s[0] -mls v0.4h, v0.4h, v0.4h -mls v25.8h, v29.8h, v0.h[4] -mls v22.2s, v29.2s, v0.s[3] -mls v26.4s, v5.4s, v28.4s -mov b0, v0.b[15] -mov d6, v0.d[1] -mov h2, v0.h[5] -mov s17, v0.s[2] -mov w8, v8.s[0] -mov x30, v18.d[0] -mov v2.b[0], v0.b[0] -mov v2.h[1], v0.h[1] -mov v2.s[2], v0.s[2] -mov v2.d[1], v0.d[1] -mov v0.b[0], w8 -mov v0.h[1], w8 -mov v0.s[2], w8 -mov v0.d[1], x8 -mov v0.16b, v0.16b -mov v0.8b, v0.8b -movi d15, #0xff00ff00ff00ff -movi v0.16b, #31 -movi v14.8h, #174 -movi v13.4h, #74, lsl #8 -movi v0.2d, #0xff0000ff0000ffff -movi v0.2s, #8, msl #8 -movi v19.2s, #226 -movi v1.4s, #122, msl #8 -movi v0.4s, #255, lsl #24 -movi v0.8b, #255 -mul v0.8b, v0.8b, v0.8b -mul v26.4h, v20.4h, v14.h[5] -mul v5.8h, v21.8h, v3.h[7] -mul v29.2s, v10.2s, v3.s[1] -mul v30.4s, v11.4s, v4.s[0] -mul v30.4s, v11.4s, v4.4s -mul v3.8h, v9.8h, v8.8h -mvni v9.4h, #237 -mvni v8.8h, #171, lsl #8 -mvni v22.4s, #15, lsl #8 -mvni v0.2s, 0 -mvni v0.4s, #16, msl #16 -neg d29, d24 -neg v0.16b, v0.16b -neg v0.2d, v0.2d -neg v0.2s, v0.2s -neg v0.4h, v0.4h -neg v0.4s, v0.4s -neg v0.8b, v0.8b -neg v0.8h, v0.8h -not v0.16b, v0.16b -not v0.8b, v0.8b -orn v0.16b, v0.16b, v0.16b -orn v29.8b, v19.8b, v16.8b -orr v0.16b, v0.16b, v0.16b -orr v9.4h, #18 -orr v0.8h, #31 -orr v4.4s, #0 -pmul v0.16b, v0.16b, v0.16b -pmul v0.8b, v0.8b, v0.8b -pmull v0.8h, v0.8b, v0.8b -pmull2 v0.8h, v0.16b, v0.16b -raddhn v0.2s, v0.2d, v0.2d -raddhn v0.4h, v0.4s, v0.4s -raddhn v0.8b, v0.8h, v0.8h -raddhn2 v0.16b, v0.8h, v0.8h -raddhn2 v0.4s, v0.2d, v0.2d -raddhn2 v0.8h, v0.4s, v0.4s -rbit v0.16b, v0.16b -rbit v0.8b, v0.8b -rev16 v21.8b, v1.8b -rev16 v30.16b, v31.16b -rev32 v0.4h, v9.4h -rev32 v21.8b, v1.8b -rev32 v30.16b, v31.16b -rev32 v4.8h, v7.8h -rev64 v0.16b, v31.16b -rev64 v1.8b, v9.8b -rev64 v13.4h, v21.4h -rev64 v2.8h, v4.8h -rev64 v4.2s, v0.2s -rev64 v6.4s, v8.4s -rshrn v0.2s, v0.2d, #3 -rshrn v0.4h, v0.4s, #3 -rshrn v0.8b, v0.8h, #3 -rshrn2 v0.16b, v0.8h, #3 -rshrn2 v0.4s, v0.2d, #3 -rshrn2 v0.8h, v0.4s, #3 -rsubhn v0.2s, v0.2d, v0.2d -rsubhn v0.4h, v0.4s, v0.4s -rsubhn v0.8b, v0.8h, v0.8h -rsubhn2 v0.16b, v0.8h, v0.8h -rsubhn2 v0.4s, v0.2d, v0.2d -rsubhn2 v0.8h, v0.4s, v0.4s -saba v0.16b, v0.16b, v0.16b -sabal v0.2d, v0.2s, v0.2s -sabal v0.4s, v0.4h, v0.4h -sabal v0.8h, v0.8b, v0.8b -sabal2 v0.2d, v0.4s, v0.4s -sabal2 v0.4s, v0.8h, v0.8h -sabal2 v0.8h, v0.16b, v0.16b -sabd v0.4h, v0.4h, v0.4h -sabd v12.2s, v11.2s, v27.2s -sabdl v0.2d, v0.2s, v0.2s -sabdl v0.4s, v0.4h, v0.4h -sabdl v0.8h, v0.8b, v0.8b -sabdl2 v0.2d, v0.4s, v0.4s -sabdl2 v0.4s, v0.8h, v0.8h -sabdl2 v0.8h, v0.16b, v0.16b -sadalp v0.1d, v0.2s -sadalp v0.2d, v0.4s -sadalp v0.2s, v0.4h -sadalp v0.4h, v0.8b -sadalp v0.4s, v0.8h -sadalp v0.8h, v0.16b -saddl v0.2d, v0.2s, v0.2s -saddl v0.4s, v0.4h, v0.4h -saddl v0.8h, v0.8b, v0.8b -saddl2 v0.2d, v0.4s, v0.4s -saddl2 v0.4s, v0.8h, v0.8h -saddl2 v0.8h, v0.16b, v0.16b -saddlp v0.1d, v0.2s -saddlp v0.2d, v0.4s -saddlp v0.2s, v0.4h -saddlp v0.4h, v0.8b -saddlp v0.4s, v0.8h -saddlp v0.8h, v0.16b -saddlv d0, v0.4s -saddlv s0, v0.4h -saddlv s0, v0.8h -saddlv h0, v0.8b -saddlv h0, v0.16b -saddw v0.2d, v0.2d, v0.2s -saddw v0.4s, v0.4s, v0.4h -saddw v0.8h, v0.8h, v0.8b -saddw2 v0.2d, v0.2d, v0.4s -saddw2 v0.4s, v0.4s, v0.8h -saddw2 v0.8h, v0.8h, v0.16b -scvtf h4, h8, #9 -scvtf h5, h14 -scvtf d21, d12 -scvtf d21, d12, #64 -scvtf s22, s13 -scvtf s22, s13, #32 -scvtf v0.2d, v0.2d -scvtf v0.2d, v0.2d, #3 -scvtf v0.2s, v0.2s -scvtf v0.2s, v0.2s, #3 -scvtf v0.4h, v0.4h -scvtf v0.4s, v0.4s -scvtf v0.4s, v0.4s, #3 -scvtf v25.4h, v13.4h, #8 -scvtf v0.8h, v0.8h -scvtf v4.8h, v8.8h, #10 -sdot v0.2s, v0.8b, v0.4b[2] -sdot v0.2s, v0.8b, v0.8b -sdot v0.4s, v0.16b, v0.16b -sdot v0.4s, v0.16b, v0.4b[2] -shadd v0.8b, v0.8b, v0.8b -shadd v25.16b, v1.16b, v10.16b -shl d7, d10, #12 -shl v23.8b, v18.8b, #6 -shl v0.16b, v0.16b, #3 -shl v0.2d, v0.2d, #3 -shl v0.4h, v0.4h, #3 -shl v0.8h, v23.8h, #10 -shl v0.4s, v0.4s, #3 -shll v0.4s, v0.4h, #16 -shll v0.8h, v0.8b, #8 -shll v0.2d, v0.2s, #32 -shll2 v0.2d, v0.4s, #32 -shll2 v0.4s, v0.8h, #16 -shll2 v0.8h, v0.16b, #8 -shrn v0.2s, v0.2d, #3 -shrn v0.4h, v0.4s, #3 -shrn v0.8b, v0.8h, #3 -shrn2 v0.16b, v0.8h, #3 -shrn2 v0.4s, v0.2d, #3 -shrn2 v0.8h, v0.4s, #3 -shsub v0.2s, v0.2s, v0.2s -shsub v0.4h, v0.4h, v0.4h -shsub v15.8h, v5.8h, v27.8h -sli d10, d14, #12 -sli v0.16b, v0.16b, #3 -sli v0.2d, v0.2d, #3 -sli v0.2s, v0.2s, #3 -sli v0.4h, v0.4h, #3 -sli v0.4s, v0.4s, #3 -sli v0.8b, v0.8b, #3 -sli v0.8h, v0.8h, #3 -smax v0.2s, v0.2s, v0.2s -smax v0.4h, v0.4h, v0.4h -smax v0.8b, v0.8b, v0.8b -smax v30.16b, v3.16b, v30.16b -smaxp v0.2s, v0.2s, v0.2s -smaxp v0.4h, v0.4h, v0.4h -smaxp v21.8h, v16.8h, v7.8h -smaxp v0.8b, v0.8b, v0.8b -smaxv b0, v0.8b -smaxv b0, v0.16b -smaxv h0, v0.4h -smaxv h0, v0.8h -smaxv s0, v0.4s -smin v0.16b, v0.16b, v0.16b -smin v0.4s, v0.4s, v0.4s -smin v0.8h, v0.8h, v0.8h -sminp v0.16b, v0.16b, v0.16b -sminp v0.4s, v0.4s, v0.4s -sminp v0.8h, v0.8h, v0.8h -sminv b0, v0.8b -sminv b0, v0.16b -sminv h0, v0.4h -sminv h0, v0.8h -sminv s0, v0.4s -smlal v0.2d, v0.2s, v0.2s -smlal v0.2d, v25.2s, v1.s[1] -smlal v0.4s, v0.4h, v0.4h -smlal v16.4s, v9.4h, v11.h[4] -smlal v0.8h, v0.8b, v0.8b -smlal2 v0.2d, v0.4s, v0.4s -smlal2 v30.2d, v22.4s, v7.s[2] -smlal2 v0.4s, v0.8h, v0.8h -smlal2 v0.8h, v0.16b, v0.16b -smlsl v0.2d, v0.2s, v0.2s -smlsl v25.2d, v27.2s, v1.s[1] -smlsl v0.4s, v0.4h, v0.4h -smlsl v14.4s, v23.4h, v12.h[7] -smlsl v0.8h, v0.8b, v0.8b -smlal2 v1.4s, v9.8h, v0.h[6] -smlsl2 v12.4s, v11.8h, v12.h[0] -smlsl2 v0.2d, v0.4s, v0.4s -smlsl2 v11.2d, v28.4s, v7.s[2] -smlsl2 v0.4s, v0.8h, v0.8h -smlsl2 v0.8h, v0.16b, v0.16b -smull v0.2d, v0.2s, v0.2s -smull v31.2d, v23.2s, v6.s[2] -smull v0.4s, v0.4h, v0.4h -smull v3.4s, v26.4h, v1.h[5] -smull v0.8h, v0.8b, v0.8b -smull2 v0.2d, v0.4s, v0.4s -smull2 v11.2d, v1.4s, v7.s[0] -smull2 v0.4s, v0.8h, v0.8h -smull2 v13.4s, v18.8h, v0.h[3] -smull2 v0.8h, v0.16b, v0.16b -sqabs b19, b14 -sqabs d18, d12 -sqabs h21, h15 -sqabs s20, s12 -sqabs v0.16b, v0.16b -sqabs v0.2d, v0.2d -sqabs v0.2s, v0.2s -sqabs v0.4h, v0.4h -sqabs v0.4s, v0.4s -sqabs v0.8b, v0.8b -sqabs v0.8h, v0.8h -sqadd b20, b11, b15 -sqadd h12, h18, h10 -sqadd v0.16b, v0.16b, v0.16b -sqadd v0.2s, v0.2s, v0.2s -sqdmlal d19, s24, s12 -sqdmlal d8, s9, v0.s[1] -sqdmlal s0, h0, v0.h[3] -sqdmlal s17, h27, h12 -sqdmlal v0.2d, v0.2s, v0.2s -sqdmlal v11.2d, v24.2s, v0.s[3] -sqdmlal v0.4s, v0.4h, v0.4h -sqdmlal v20.4s, v30.4h, v12.h[3] -sqdmlal2 v0.2d, v0.4s, v0.4s -sqdmlal2 v23.2d, v30.4s, v6.s[0] -sqdmlal2 v0.4s, v0.8h, v0.8h -sqdmlal2 v2.4s, v17.8h, v5.h[6] -sqdmulh v8.4h, v16.4h, v5.h[4] -sqdmulh v16.2s, v24.2s, v7.s[2] -sqdmull v8.4s, v19.4h, v1.h[2] -sqdmull v20.2d, v10.2s, v6.s[2] -sqdmull2 v10.4s, v25.8h, v0.h[7] -sqdmull2 v4.2d, v29.4s, v2.s[3] -sqrdmulh v0.8h, v15.8h, v0.h[5] -sqrdmulh v6.2s, v29.2s, v4.s[2] -sqrdmulh v31.2s, v17.2s, v4.2s -sqdmlsl d12, s23, s13 -sqdmlsl d8, s9, v0.s[1] -sqdmlsl s0, h0, v0.h[3] -sqdmlsl s14, h12, h25 -sqdmlsl v0.2d, v0.2s, v0.2s -sqdmlsl v26.2d, v7.2s, v3.s[0] -sqdmlsl v0.4s, v0.4h, v0.4h -sqdmlsl v4.4s, v22.4h, v13.h[2] -sqdmlsl2 v0.2d, v0.4s, v0.4s -sqdmlsl2 v4.2d, v3.4s, v3.s[2] -sqdmlsl2 v0.4s, v0.8h, v0.8h -sqdmlsl2 v2.4s, v28.8h, v4.h[6] -sqdmulh h10, h11, h12 -sqdmulh h7, h15, v0.h[3] -sqdmulh s15, s14, v0.s[1] -sqdmulh s20, s21, s2 -sqdmulh v0.2s, v0.2s, v0.2s -sqdmulh v0.4s, v0.4s, v0.4s -sqdmull d1, s1, v0.s[1] -sqdmull d15, s22, s12 -sqdmull s1, h1, v0.h[3] -sqdmull s12, h22, h12 -sqdmull v0.2d, v0.2s, v0.2s -sqdmull v0.4s, v0.4h, v0.4h -sqdmull2 v0.2d, v0.4s, v0.4s -sqdmull2 v0.4s, v0.8h, v0.8h -sqneg b19, b14 -sqneg d18, d12 -sqneg h21, h15 -sqneg s20, s12 -sqneg v0.16b, v0.16b -sqneg v0.2d, v0.2d -sqneg v0.2s, v0.2s -sqneg v0.4h, v0.4h -sqneg v0.4s, v0.4s -sqneg v0.8b, v0.8b -sqneg v0.8h, v0.8h -sqrdmlah h0, h1, v2.h[3] -sqrdmlah v0.4h, v1.4h, v2.h[3] -sqrdmlah v0.8h, v1.8h, v2.h[3] -sqrdmlah s0, s1, v2.s[1] -sqrdmlah v0.2s, v1.2s, v2.s[1] -sqrdmlah v0.4s, v1.4s, v2.s[1] -sqrdmlah h0, h1, h2 -sqrdmlah v0.4h, v1.4h, v2.4h -sqrdmlah v0.8h, v1.8h, v2.8h -sqrdmlah s0, s1, s2 -sqrdmlah v0.2s, v1.2s, v2.2s -sqrdmlah v0.4s, v1.4s, v2.4s -sqrdmlsh h0, h1, v2.h[3] -sqrdmlsh v0.4h, v1.4h, v2.h[3] -sqrdmlsh v0.8h, v1.8h, v2.h[3] -sqrdmlsh s0, s1, v2.s[1] -sqrdmlsh v0.2s, v1.2s, v2.s[1] -sqrdmlsh v0.4s, v1.4s, v2.s[1] -sqrdmlsh h0, h1, h2 -sqrdmlsh v0.4h, v1.4h, v2.4h -sqrdmlsh v0.8h, v1.8h, v2.8h -sqrdmlsh s0, s1, s2 -sqrdmlsh v0.2s, v1.2s, v2.2s -sqrdmlsh v0.4s, v1.4s, v2.4s -sqrdmulh h10, h11, h12 -sqrdmulh h7, h15, v0.h[3] -sqrdmulh s15, s14, v0.s[1] -sqrdmulh s20, s21, s2 -sqrdmulh v0.4h, v0.4h, v0.4h -sqrdmulh v0.8h, v0.8h, v0.8h -sqrshl d31, d31, d31 -sqrshl h3, h4, h15 -sqrshl v0.2s, v0.2s, v0.2s -sqrshl v0.4h, v0.4h, v0.4h -sqrshl v0.8b, v0.8b, v0.8b -sqshl s17, s4, s23 -sqsub b3, b13, b12 -sqsub v20.8h, v18.8h, v12.8h -sqrshrn b10, h13, #2 -sqrshrn h15, s10, #6 -sqrshrn s15, d12, #9 -sqrshrn v0.2s, v0.2d, #3 -sqrshrn v0.4h, v0.4s, #3 -sqrshrn v0.8b, v0.8h, #3 -sqrshrn2 v0.16b, v0.8h, #3 -sqrshrn2 v0.4s, v0.2d, #3 -sqrshrn2 v0.8h, v0.4s, #3 -sqrshrun b17, h10, #6 -sqrshrun h10, s13, #15 -sqrshrun s22, d16, #31 -sqrshrun v0.2s, v0.2d, #3 -sqrshrun v0.4h, v0.4s, #3 -sqrshrun v0.8b, v0.8h, #3 -sqrshrun2 v0.16b, v0.8h, #3 -sqrshrun2 v0.4s, v0.2d, #3 -sqrshrun2 v0.8h, v0.4s, #3 -sqshl b11, b19, #7 -sqshl d15, d16, #51 -sqshl d31, d31, d31 -sqshl h13, h18, #11 -sqshl h3, h4, h15 -sqshl s14, s17, #22 -sqshl v0.16b, v0.16b, #3 -sqshl v23.16b, v23.16b, v23.16b -sqshl v0.2d, v0.2d, #3 -sqshl v0.2s, v0.2s, #3 -sqshl v0.2s, v0.2s, v0.2s -sqshl v0.4h, v0.4h, #3 -sqshl v0.4h, v0.4h, v0.4h -sqshl v0.4s, v0.4s, #3 -sqshl v0.8b, v0.8b, #3 -sqshl v0.8b, v0.8b, v0.8b -sqshl v0.8h, v0.8h, #3 -sqshlu b15, b18, #6 -sqshlu d11, d13, #32 -sqshlu h19, h17, #6 -sqshlu s16, s14, #25 -sqshlu v0.16b, v0.16b, #3 -sqshlu v0.2d, v0.2d, #3 -sqshlu v0.2s, v0.2s, #3 -sqshlu v0.4h, v0.4h, #3 -sqshlu v0.4s, v0.4s, #3 -sqshlu v0.8b, v0.8b, #3 -sqshlu v0.8h, v0.8h, #3 -sqshrn b10, h15, #5 -sqshrn h17, s10, #4 -sqshrn s18, d10, #31 -sqshrn v0.2s, v0.2d, #3 -sqshrn v0.4h, v0.4s, #3 -sqshrn v0.8b, v0.8h, #3 -sqshrn2 v0.16b, v0.8h, #3 -sqshrn2 v0.4s, v0.2d, #3 -sqshrn2 v0.8h, v0.4s, #3 -sqshrun b15, h10, #7 -sqshrun h20, s14, #3 -sqshrun s10, d15, #15 -sqshrun v0.2s, v0.2d, #3 -sqshrun v0.4h, v0.4s, #3 -sqshrun v0.8b, v0.8h, #3 -sqshrun2 v0.16b, v0.8h, #3 -sqshrun2 v0.4s, v0.2d, #3 -sqshrun2 v0.8h, v0.4s, #3 -sqsub s20, s10, s7 -sqsub v0.2d, v0.2d, v0.2d -sqsub v0.4s, v0.4s, v0.4s -sqsub v0.8b, v0.8b, v0.8b -sqxtn b18, h18 -sqxtn h20, s17 -sqxtn s19, d14 -sqxtn v0.2s, v0.2d -sqxtn v0.4h, v0.4s -sqxtn v0.8b, v0.8h -sqxtn2 v0.16b, v0.8h -sqxtn2 v0.4s, v0.2d -sqxtn2 v0.8h, v0.4s -sqxtun b19, h14 -sqxtun h21, s15 -sqxtun s20, d12 -sqxtun v0.2s, v0.2d -sqxtun v0.4h, v0.4s -sqxtun v0.8b, v0.8h -sqxtun2 v0.16b, v0.8h -sqxtun2 v0.4s, v0.2d -sqxtun2 v0.8h, v0.4s -srhadd v0.2s, v0.2s, v0.2s -srhadd v0.4h, v0.4h, v0.4h -srhadd v0.8b, v0.8b, v0.8b -sri d10, d12, #14 -sri v0.16b, v0.16b, #3 -sri v0.2d, v0.2d, #3 -sri v0.2s, v0.2s, #3 -sri v0.4h, v0.4h, #3 -sri v0.4s, v0.4s, #3 -sri v0.8b, v0.8b, #3 -sri v0.8h, v0.8h, #3 -srshl d16, d16, d16 -srshl v0.2s, v0.2s, v0.2s -srshl v0.4h, v0.4h, v0.4h -srshl v0.8b, v0.8b, v0.8b -srshr d19, d18, #7 -srshr v0.16b, v0.16b, #3 -srshr v0.2d, v0.2d, #3 -srshr v0.2s, v0.2s, #3 -srshr v0.4h, v0.4h, #3 -srshr v0.4s, v0.4s, #3 -srshr v0.8b, v0.8b, #3 -srshr v0.8h, v0.8h, #3 -srsra d15, d11, #19 -srsra v0.16b, v0.16b, #3 -srsra v0.2d, v0.2d, #3 -srsra v0.2s, v0.2s, #3 -srsra v0.4h, v0.4h, #3 -srsra v0.4s, v0.4s, #3 -srsra v0.8b, v0.8b, #3 -srsra v0.8h, v0.8h, #3 -sshl d31, d31, d31 -sshl v0.2d, v0.2d, v0.2d -sshl v0.2s, v0.2s, v0.2s -sshl v0.4h, v0.4h, v0.4h -sshl v0.8b, v0.8b, v0.8b -sshll v9.8h, v2.8b, #0 -sshll v12.4s, v3.4h, #4 -sshll v0.2d, v0.2s, #3 -sshll2 v28.8h, v12.16b, #7 -sshll2 v0.4s, v0.8h, #3 -sshll2 v17.2d, v13.4s, #22 -sshr d15, d16, #12 -sshr v0.16b, v0.16b, #3 -sshr v0.2d, v0.2d, #3 -sshr v0.2s, v0.2s, #3 -sshr v0.4h, v0.4h, #3 -sshr v0.4s, v0.4s, #3 -sshr v0.8b, v0.8b, #3 -sshr v0.8h, v0.8h, #3 -ssra d18, d12, #21 -ssra v0.16b, v0.16b, #3 -ssra v0.2d, v0.2d, #3 -ssra v0.2s, v0.2s, #3 -ssra v0.4h, v0.4h, #3 -ssra v0.4s, v0.4s, #3 -ssra v0.8b, v0.8b, #3 -ssra v0.8h, v0.8h, #3 -ssubl v0.2d, v0.2s, v0.2s -ssubl v0.4s, v0.4h, v0.4h -ssubl v0.8h, v0.8b, v0.8b -ssubl2 v0.2d, v0.4s, v0.4s -ssubl2 v0.4s, v0.8h, v0.8h -ssubl2 v0.8h, v0.16b, v0.16b -ssubw v0.2d, v0.2d, v0.2s -ssubw v0.4s, v0.4s, v0.4h -ssubw v0.8h, v0.8h, v0.8b -ssubw2 v0.2d, v0.2d, v0.4s -ssubw2 v0.4s, v0.4s, v0.8h -ssubw2 v0.8h, v0.8h, v0.16b -st1 { v18.8b }, [x15] -st1 { v8.8b, v9.8b }, [x18] -st1 { v15.8b, v16.8b, v17.8b }, [x0] -st1 { v21.8b, v22.8b, v23.8b, v24.8b }, [x14] -st1 { v0.16b }, [x0] -st1 { v1.16b, v2.16b }, [x4] -st1 { v27.16b, v28.16b, v29.16b }, [x18] -st1 { v18.16b, v19.16b, v20.16b, v21.16b }, [x29] -st1 { v19.4h }, [x7] -st1 { v22.4h, v23.4h }, [x22] -st1 { v13.4h, v14.4h, v15.4h }, [x7] -st1 { v23.4h, v24.4h, v25.4h, v26.4h }, [x24] -st1 { v27.8h }, [x17] -st1 { v8.8h, v9.8h, v10.8h }, [x16] -st1 { v7.8h, v8.8h, v9.8h, v10.8h }, [x19] -st1 { v25.2s }, [x6] -st1 { v13.2s, v14.2s }, [x9] -st1 { v12.2s, v13.2s, v14.2s }, [x3] -st1 { v6.2s, v7.2s, v8.2s, v9.2s }, [x13] -st1 { v0.4s, v1.4s }, [sp], #32 -st1 { v22.4s }, [x19] -st1 { v15.4s, v16.4s }, [x12] -st1 { v26.4s, v27.4s, v28.4s, v29.4s }, [x12] -st1 { v20.1d }, [x10] -st1 { v21.1d, v22.1d }, [x29] -st1 { v5.1d, v6.1d, v7.1d }, [x3] -st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x10] -st1 { v26.2d, v27.2d }, [x28] -st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 -st1 { v13.2d, v14.2d, v15.2d }, [x27] -st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] -st1 { v8.2d }, [x15] -st1 { v0.8h }, [x15], x2 -st1 { v0.8h, v1.8h }, [x15] -st1 { v0.4s, v1.4s }, [sp], #32 -st1 { v0.4s, v1.4s, v2.4s }, [sp] -st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 -st1 { v1.b }[5], [x1] -st1 { v0.h }[2], [x1] -st1 { v31.s }[1], [x16] -st1 { v0.8h }, [x15], x2 -st1 { v0.8h, v1.8h }, [x15] -st1 { v0.d }[1], [x0] -st1 { v0.d }[1], [x0], #8 -st2 { v0.16b, v1.16b }, [x0], x1 -st2 { v0.8b, v1.8b }, [x0] -st2 { v6.16b, v7.16b }, [x23] -st2 { v10.4h, v11.4h }, [x18] -st2 { v10.8h, v11.8h }, [x18] -st2 { v25.2s, v26.2s }, [x29] -st2 { v26.4s, v27.4s }, [x14] -st2 { v10.2d, v11.2d }, [x1] -st2 { v21.b, v22.b }[15], [x15] -st2 { v28.h, v29.h }[2], [x6] -st2 { v0.s, v1.s }[3], [sp] -st2 { v0.s, v1.s }[3], [sp], #8 -st2 { v17.d, v18.d }[1], [x1] -st3 { v10.8b, v11.8b, v12.8b }, [x18] -st3 { v26.16b, v27.16b, v28.16b }, [x4] -st3 { v0.4h, v1.4h, v2.4h }, [x15] -st3 { v0.8h, v1.8h, v2.8h }, [x15], x2 -st3 { v0.8h, v1.8h, v2.8h }, [x0] -st3 { v19.2s, v20.2s, v21.2s }, [x30] -st3 { v24.4s, v25.4s, v26.4s }, [x8] -st3 { v24.2d, v25.2d, v26.2d }, [x25] -st3 { v8.b, v9.b, v10.b }[4], [x18] -st3 { v0.h, v1.h, v2.h }[7], [x15] -st3 { v0.h, v1.h, v2.h }[7], [x15], #6 -st3 { v9.s, v10.s, v11.s }[2], [x20] -st3 { v16.d, v17.d, v18.d }[0], [x13] -st4 { v17.8b, v18.8b, v19.8b, v20.8b }, [x8] -st4 { v7.16b, v8.16b, v9.16b, v10.16b }, [x15] -st4 { v5.4h, v6.4h, v7.4h, v8.4h }, [x13] -st4 { v11.8h, v12.8h, v13.8h, v14.8h }, [x1] -st4 { v0.2s, v1.2s, v2.2s, v3.2s }, [sp] -st4 { v0.4s, v1.4s, v2.4s, v3.4s }, [sp], #64 -st4 { v21.4s, v22.4s, v23.4s, v24.4s }, [x6] -st4 { v25.2d, v26.2d, v27.2d, v28.2d }, [x16] -st4 { v0.b, v1.b, v2.b, v3.b }[15], [x0] -st4 { v5.h, v6.h, v7.h, v8.h }[4], [x13] -st4 { v22.s, v23.s, v24.s, v25.s }[0], [x7] -st4 { v23.d, v24.d, v25.d, v26.d }[1], [x5] -st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] -st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 -st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], x5 -sub d15, d5, d16 -sub v0.2d, v0.2d, v0.2d -sub v15.2s, v14.2s, v11.2s -subhn v7.4h, v10.4s, v13.4s -subhn2 v24.4s, v24.2d, v8.2d -suqadd b19, b14 -suqadd d18, d22 -suqadd h20, h15 -suqadd s21, s12 -suqadd v0.16b, v0.16b -suqadd v0.2d, v0.2d -suqadd v0.2s, v0.2s -suqadd v0.4h, v0.4h -suqadd v0.4s, v0.4s -suqadd v0.8b, v0.8b -suqadd v0.8h, v0.8h -tbl v0.16b, { v0.16b }, v0.16b -tbl v0.16b, { v0.16b, v1.16b }, v0.16b -tbl v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b -tbl v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b -tbl v0.8b, { v0.16b }, v0.8b -tbl v0.8b, { v0.16b, v1.16b }, v0.8b -tbl v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b -tbl v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b -tbx v0.16b, { v0.16b }, v0.16b -tbx v0.16b, { v0.16b, v1.16b }, v0.16b -tbx v0.16b, { v0.16b, v1.16b, v2.16b }, v0.16b -tbx v0.16b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.16b -tbx v0.8b, { v0.16b }, v0.8b -tbx v0.8b, { v0.16b, v1.16b }, v0.8b -tbx v0.8b, { v0.16b, v1.16b, v2.16b }, v0.8b -tbx v0.8b, { v0.16b, v1.16b, v2.16b, v3.16b }, v0.8b -trn1 v0.16b, v0.16b, v0.16b -trn1 v0.2d, v0.2d, v0.2d -trn1 v0.2s, v0.2s, v0.2s -trn1 v0.4h, v0.4h, v0.4h -trn1 v0.4s, v0.4s, v0.4s -trn1 v0.8b, v0.8b, v0.8b -trn1 v0.8h, v0.8h, v0.8h -trn2 v0.16b, v0.16b, v0.16b -trn2 v0.2d, v0.2d, v0.2d -trn2 v0.2s, v0.2s, v0.2s -trn2 v0.4h, v0.4h, v0.4h -trn2 v0.4s, v0.4s, v0.4s -trn2 v0.8b, v0.8b, v0.8b -trn2 v0.8h, v0.8h, v0.8h -uaba v0.8b, v0.8b, v0.8b -uaba v13.16b, v14.16b, v19.16b -uabal v0.2d, v0.2s, v0.2s -uabal v0.4s, v0.4h, v0.4h -uabal v0.8h, v0.8b, v0.8b -uabal2 v0.2d, v0.4s, v0.4s -uabal2 v0.4s, v0.8h, v0.8h -uabal2 v0.8h, v0.16b, v0.16b -uabd v0.4h, v0.4h, v0.4h -uabd v23.4s, v4.4s, v30.4s -uabdl v0.2d, v0.2s, v0.2s -uabdl v0.4s, v0.4h, v0.4h -uabdl v0.8h, v0.8b, v0.8b -uabdl2 v0.2d, v0.4s, v0.4s -uabdl2 v0.4s, v0.8h, v0.8h -uabdl2 v0.8h, v0.16b, v0.16b -uadalp v0.1d, v0.2s -uadalp v0.2d, v0.4s -uadalp v0.2s, v0.4h -uadalp v0.4h, v0.8b -uadalp v0.4s, v0.8h -uadalp v0.8h, v0.16b -uaddl v0.2d, v0.2s, v0.2s -uaddl v0.4s, v0.4h, v0.4h -uaddl v0.8h, v0.8b, v0.8b -uaddl2 v0.2d, v0.4s, v0.4s -uaddl2 v0.4s, v0.8h, v0.8h -uaddl2 v0.8h, v0.16b, v0.16b -uaddlp v0.1d, v0.2s -uaddlp v0.2d, v0.4s -uaddlp v0.2s, v0.4h -uaddlp v0.4h, v0.8b -uaddlp v0.4s, v0.8h -uaddlp v0.8h, v0.16b -uaddlv d0, v0.4s -uaddlv s0, v0.4h -uaddlv s0, v0.8h -uaddlv h0, v0.8b -uaddlv h0, v0.16b -uaddw v0.2d, v0.2d, v0.2s -uaddw v0.4s, v0.4s, v0.4h -uaddw v0.8h, v0.8h, v0.8b -uaddw2 v0.2d, v0.2d, v0.4s -uaddw2 v0.4s, v0.4s, v0.8h -uaddw2 v0.8h, v0.8h, v0.16b -ucvtf h17, x12 -ucvtf h22, h16, #11 -ucvtf h7, h21 -ucvtf d21, d14 -ucvtf d21, d14, #64 -ucvtf s8, x0 -ucvtf s22, s13 -ucvtf s22, s13, #32 -ucvtf v0.2d, v0.2d -ucvtf v0.2d, v0.2d, #3 -ucvtf v0.2s, v0.2s -ucvtf v0.2s, v0.2s, #3 -ucvtf v0.4h, v0.4h -ucvtf v0.4s, v0.4s -ucvtf v0.4s, v0.4s, #3 -ucvtf v18.4h, v11.4h, #7 -ucvtf v0.8h, v0.8h -ucvtf v22.8h, v20.8h, #10 -udot v0.2s, v0.8b, v0.4b[2] -udot v0.2s, v0.8b, v0.8b -udot v0.4s, v0.16b, v0.16b -udot v0.4s, v0.16b, v0.4b[2] -uhadd v0.16b, v0.16b, v0.16b -uhadd v0.8h, v0.8h, v0.8h -uhsub v12.4h, v16.4h, v28.4h -uhsub v0.4s, v0.4s, v0.4s -umax v0.16b, v0.16b, v0.16b -umax v0.4s, v0.4s, v0.4s -umax v0.8h, v0.8h, v0.8h -umaxp v0.16b, v0.16b, v0.16b -umaxp v0.4s, v0.4s, v0.4s -umaxp v0.8h, v0.8h, v0.8h -umaxv b0, v0.8b -umaxv b0, v0.16b -umaxv h0, v0.4h -umaxv h0, v0.8h -umaxv s0, v0.4s -umin v0.2s, v0.2s, v0.2s -umin v0.4h, v0.4h, v0.4h -umin v0.8b, v0.8b, v0.8b -umin v0.16b, v26.16b, v2.16b -uminp v0.2s, v0.2s, v0.2s -uminp v28.4s, v16.4s, v15.4s -uminp v0.4h, v0.4h, v0.4h -uminp v0.8b, v0.8b, v0.8b -uminv b0, v0.8b -uminv b0, v0.16b -uminv h0, v0.4h -uminv h0, v0.8h -uminv s0, v0.4s -umlal v0.2d, v0.2s, v0.2s -umlal v28.2d, v31.2s, v0.s[1] -umlal v0.4s, v0.4h, v0.4h -umlal v22.4s, v14.4h, v0.h[6] -umlal v0.8h, v0.8b, v0.8b -umlal2 v10.2d, v4.4s, v3.s[2] -umlal2 v31.4s, v7.8h, v15.h[5] -umlal2 v0.2d, v0.4s, v0.4s -umlal2 v0.4s, v0.8h, v0.8h -umlal2 v0.8h, v0.16b, v0.16b -umlsl v0.2d, v0.2s, v0.2s -umlsl v20.2d, v20.2s, v2.s[0] -umlsl v0.4s, v0.4h, v0.4h -umlsl v21.4s, v12.4h, v7.h[5] -umlsl v0.8h, v0.8b, v0.8b -umlsl2 v0.2d, v0.4s, v0.4s -umlsl2 v30.2d, v23.4s, v1.s[2] -umlsl2 v0.4s, v0.8h, v0.8h -umlsl2 v27.4s, v28.8h, v6.h[4] -umlsl2 v0.8h, v0.16b, v0.16b -umov w6, v22.b[0] -umov w0, v0.b[1] -umov w10, v25.h[0] -umov w0, v0.h[1] -umov w0, v0.s[1] -umov x0, v0.d[1] -umull v0.2d, v0.2s, v0.2s -umull v22.2d, v28.2s, v6.s[1] -umull v0.4s, v0.4h, v0.4h -umull v27.4s, v1.4h, v8.h[6] -umull v0.8h, v0.8b, v0.8b -umull2 v0.2d, v0.4s, v0.4s -umull2 v28.2d, v21.4s, v1.s[0] -umull2 v0.4s, v0.8h, v0.8h -umull2 v18.4s, v26.8h, v10.h[1] -umull2 v0.8h, v0.16b, v0.16b -uqadd h0, h1, h5 -uqadd s0, s24, s30 -uqadd v0.8h, v0.8h, v0.8h -uqadd v14.2d, v22.2d, v20.2d -uqrshl b11, b20, b30 -uqrshl s23, s20, s16 -uqrshl v25.8b, v13.8b, v23.8b -uqrshl v0.16b, v0.16b, v0.16b -uqrshl v0.4s, v0.4s, v0.4s -uqrshl v0.8h, v0.8h, v0.8h -uqrshrn b10, h12, #5 -uqrshrn h12, s10, #14 -uqrshrn s10, d10, #25 -uqrshrn v0.2s, v0.2d, #3 -uqrshrn v0.4h, v0.4s, #3 -uqrshrn v0.8b, v0.8h, #3 -uqrshrn2 v0.16b, v0.8h, #3 -uqrshrn2 v0.4s, v0.2d, #3 -uqrshrn2 v0.8h, v0.4s, #3 -uqshl b11, b20, b30 -uqshl b18, b15, #6 -uqshl d15, d12, #19 -uqshl h11, h18, #7 -uqshl s14, s19, #18 -uqshl s23, s20, s16 -uqshl v0.16b, v0.16b, #3 -uqshl v0.16b, v0.16b, v0.16b -uqshl v0.2d, v0.2d, #3 -uqshl v0.2d, v0.2d, v0.2d -uqshl v0.2s, v0.2s, #3 -uqshl v0.4h, v0.4h, #3 -uqshl v8.4h, v17.4h, v13.4h -uqshl v0.4s, v0.4s, #3 -uqshl v0.4s, v0.4s, v0.4s -uqshl v0.8b, v0.8b, #3 -uqshl v0.8h, v0.8h, #3 -uqshl v0.8h, v0.8h, v0.8h -uqshrn b12, h10, #7 -uqshrn h10, s14, #5 -uqshrn s10, d12, #13 -uqshrn v0.2s, v0.2d, #3 -uqshrn v0.4h, v0.4s, #3 -uqshrn v0.8b, v0.8h, #3 -uqshrn2 v0.16b, v0.8h, #3 -uqshrn2 v0.4s, v0.2d, #3 -uqshrn2 v0.8h, v0.4s, #3 -uqsub s16, s21, s6 -uqsub d16, d16, d16 -uqsub v0.4h, v0.4h, v0.4h -uqsub v19.4s, v0.4s, v5.4s -uqxtn b18, h18 -uqxtn h20, s17 -uqxtn s19, d14 -uqxtn v0.2s, v0.2d -uqxtn v0.4h, v0.4s -uqxtn v0.8b, v0.8h -uqxtn2 v0.16b, v0.8h -uqxtn2 v0.4s, v0.2d -uqxtn2 v0.8h, v0.4s -urecpe v0.2s, v0.2s -urecpe v0.4s, v0.4s -urhadd v0.16b, v0.16b, v0.16b -urhadd v0.4s, v0.4s, v0.4s -urhadd v0.8h, v0.8h, v0.8h -urhadd v16.2s, v19.2s, v2.2s -urshl d8, d7, d4 -urshl v31.8b, v5.8b, v3.8b -urshl v0.16b, v0.16b, v0.16b -urshl v0.2d, v0.2d, v0.2d -urshl v0.4s, v0.4s, v0.4s -urshl v0.8h, v0.8h, v0.8h -urshr d20, d23, #31 -urshr v0.16b, v0.16b, #3 -urshr v0.2d, v0.2d, #3 -urshr v0.2s, v0.2s, #3 -urshr v0.4h, v0.4h, #3 -urshr v0.4s, v0.4s, #3 -urshr v0.8b, v0.8b, #3 -urshr v0.8h, v0.8h, #3 -ursqrte v0.2s, v0.2s -ursqrte v0.4s, v0.4s -ursra d18, d10, #13 -ursra v0.16b, v0.16b, #3 -ursra v0.2d, v0.2d, #3 -ursra v0.2s, v0.2s, #3 -ursra v0.4h, v0.4h, #3 -ursra v0.4s, v0.4s, #3 -ursra v0.8b, v0.8b, #3 -ursra v0.8h, v0.8h, #3 -ushl d0, d0, d0 -ushl v6.8b, v26.8b, v6.8b -ushl v0.16b, v0.16b, v0.16b -ushl v0.4s, v0.4s, v0.4s -ushl v0.8h, v0.8h, v0.8h -ushll v0.4s, v0.4h, #3 -ushll v18.8h, v24.8b, #4 -ushll v16.2d, v16.2s, #31 -ushll2 v31.2d, v12.4s, #11 -ushll2 v18.4s, v22.8h, #13 -ushll2 v0.8h, v0.16b, #3 -ushr d10, d17, #18 -ushr v0.16b, v0.16b, #3 -ushr v0.2d, v0.2d, #3 -ushr v0.2s, v0.2s, #3 -ushr v0.4h, v0.4h, #3 -ushr v0.4s, v0.4s, #3 -ushr v0.8b, v0.8b, #3 -ushr v0.8h, v0.8h, #3 -smov w15, v22.b[0] -smov w26, v27.h[0] -smov x21, v0.b[0] -smov x9, v27.h[0] -smov x15, v3.s[0] -smov w0, v0.b[1] -smov w0, v0.h[1] -smov x0, v0.b[1] -smov x0, v0.h[1] -smov x0, v0.s[1] -usqadd b19, b14 -usqadd d18, d22 -usqadd h20, h15 -usqadd s21, s12 -usqadd v0.16b, v0.16b -usqadd v0.2d, v0.2d -usqadd v0.2s, v0.2s -usqadd v0.4h, v0.4h -usqadd v0.4s, v0.4s -usqadd v0.8b, v0.8b -usqadd v0.8h, v0.8h -usra d20, d13, #61 -usra v0.16b, v0.16b, #3 -usra v0.2d, v0.2d, #3 -usra v0.2s, v0.2s, #3 -usra v0.4h, v0.4h, #3 -usra v0.4s, v0.4s, #3 -usra v0.8b, v0.8b, #3 -usra v0.8h, v0.8h, #3 -usubl v0.2d, v0.2s, v0.2s -usubl v0.4s, v0.4h, v0.4h -usubl v0.8h, v0.8b, v0.8b -usubl2 v0.2d, v0.4s, v0.4s -usubl2 v0.4s, v0.8h, v0.8h -usubl2 v0.8h, v0.16b, v0.16b -usubw v0.2d, v0.2d, v0.2s -usubw v0.4s, v0.4s, v0.4h -usubw v0.8h, v0.8h, v0.8b -usubw2 v0.2d, v0.2d, v0.4s -usubw2 v0.4s, v0.4s, v0.8h -usubw2 v0.8h, v0.8h, v0.16b -uzp1 v0.16b, v0.16b, v0.16b -uzp1 v0.2d, v0.2d, v0.2d -uzp1 v0.2s, v0.2s, v0.2s -uzp1 v0.4h, v0.4h, v0.4h -uzp1 v0.4s, v0.4s, v0.4s -uzp1 v0.8b, v0.8b, v0.8b -uzp1 v0.8h, v0.8h, v0.8h -uzp2 v0.16b, v0.16b, v0.16b -uzp2 v0.2d, v0.2d, v0.2d -uzp2 v0.2s, v0.2s, v0.2s -uzp2 v0.4h, v0.4h, v0.4h -uzp2 v0.4s, v0.4s, v0.4s -uzp2 v0.8b, v0.8b, v0.8b -uzp2 v0.8h, v0.8h, v0.8h -xtn v0.2s, v0.2d -xtn v0.4h, v0.4s -xtn v0.8b, v0.8h -xtn2 v0.16b, v0.8h -xtn2 v0.4s, v0.2d -xtn2 v0.8h, v0.4s -zip1 v0.16b, v0.16b, v0.16b -zip1 v0.2d, v0.2d, v0.2d -zip1 v0.2s, v0.2s, v0.2s -zip1 v0.4h, v0.4h, v0.4h -zip1 v0.4s, v0.4s, v0.4s -zip1 v0.8b, v0.8b, v0.8b -zip1 v0.8h, v0.8h, v0.8h -zip2 v0.16b, v0.16b, v0.16b -zip2 v0.2d, v0.2d, v0.2d -zip2 v0.2s, v0.2s, v0.2s -zip2 v0.4h, v0.4h, v0.4h -zip2 v0.4s, v0.4s, v0.4s -zip2 v0.8b, v0.8b, v0.8b -zip2 v0.8h, v0.8h, v0.8h diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s index 0a36c14e4395..4803f1e68648 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n1 -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n1 -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s index 270990154f24..a88d19da25cd 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N1-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n1 -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n1 -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s index 11ba3d45162a..5f8ffd8bf655 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-bf16-instructions.s index 38dad09b2d1a..11306a6acfd6 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-bf16-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-bf16-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/bf16-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-complxnum-instructions.s index 0fb5dc4848b0..2f4692406b13 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-complxnum-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-complxnum-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/complxnum-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fp16fml-instructions.s index c95d7f503d2b..c746b2c23901 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fp16fml-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fp16fml-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/fp16fml-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fptoint-instructions.s index 375e528d2274..3314806e0bd8 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fptoint-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-fptoint-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/fptoint-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/fptoint-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-i8mm-instructions.s index 5cbaa56b9ba6..fc138b5bccbc 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-i8mm-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-i8mm-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/i8mm-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s index 07816d95eaed..39f3295bac19 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-mte-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/mte-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/mte-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s index fcb796dc74ce..0e074d4543e9 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -mattr=+aes -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s index bb33ff91758a..bbe58dbb418c 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/Inputs/rcpc-immo-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s index 82c2ccec7c06..01af6c1bedf2 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/Inputs/sve-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/../Inputs/sve-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s index f2efce90c626..b45edae2c005 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-bf16-instructions.s index 02e547f75add..22f04771b555 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-bf16-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-bf16-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/bf16-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-complxnum-instructions.s index 6fab828dfb31..a01bb55d6669 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-complxnum-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-complxnum-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/complxnum-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fp16fml-instructions.s index 394599140b48..38ed6332e0f1 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fp16fml-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fp16fml-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/fp16fml-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fptoint-instructions.s index d7958c7c0cee..de4c325a76f5 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fptoint-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-fptoint-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/fptoint-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/fptoint-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-i8mm-instructions.s index 1ff0ebaf136b..f52835a1924e 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-i8mm-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-i8mm-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/i8mm-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s index 114e21549e32..b15fe5a29acb 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-mte-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/mte-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/mte-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s index d25122b474de..e8ce5d3d9db5 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -mattr=+aes -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s index bf0ee9d4f51a..62df43d5745a 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/Inputs/rcpc-immo-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s index 6109991999c1..4a1d1a56d2e0 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-sve-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/Inputs/sve-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-n3 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/../Inputs/sve-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s index 801a5d85e541..d06db4b366e1 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s index 4b49d72b5d2e..fa8a5b7b3e2f 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-bf16-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/bf16-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-complxnum-instructions.s index 9acba778ec50..fadee2e50355 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-complxnum-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-complxnum-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/complxnum-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-fp16fml-instructions.s index 18eee106749a..ac1c3c2eab0e 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-fp16fml-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-fp16fml-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/fp16fml-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-i8mm-instructions.s index 638aa0146671..8a56e206addb 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-i8mm-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-i8mm-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/i8mm-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s index 72369cb94eef..0cd253b983a8 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s index 5a5603f16699..fc4932749e5e 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/Inputs/rcpc-immo-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v1 -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s index dbe52eef122e..b58cc28c1e53 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s index e96fbb52ee63..81964d84ac04 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-bf16-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/bf16-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-complxnum-instructions.s index a61a0cae20ac..32649b9fb049 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-complxnum-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-complxnum-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/complxnum-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fp16fml-instructions.s index d826870b0f02..e891e2efc42b 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fp16fml-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fp16fml-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/fp16fml-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s index b4221be05ed1..d3864abbe9b9 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-fptoint-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/fptoint-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/fptoint-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-i8mm-instructions.s index adfb6bbf6657..c8f44c72ce41 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-i8mm-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-i8mm-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/i8mm-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-mte-instructions.s index 6b9f9d4e4564..7313f615b28b 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-mte-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-mte-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/mte-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/mte-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s index 6580d6a6590b..14e46e89a846 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+aes -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s index 00c24cec0a43..9102dc15f6bf 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/Inputs/rcpc-immo-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s index 28fe7216bd26..96e4806bf446 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-sve-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/Inputs/sve-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v2 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/../Inputs/sve-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s index 343753568654..6a643a514056 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-bf16-instructions.s index 6622307ae4df..11da3d9f6f55 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-bf16-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-bf16-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/bf16-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-complxnum-instructions.s index 86f434d020f7..b5eeccdcc033 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-complxnum-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-complxnum-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/complxnum-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fp16fml-instructions.s index 017568cf5b0d..59c52629bd9c 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fp16fml-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fp16fml-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/fp16fml-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fptoint-instructions.s index 6a823470af0b..0187f63b3d20 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fptoint-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-fptoint-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/fptoint-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/fptoint-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-i8mm-instructions.s index 9ed5bd395da4..f3d685f41cb2 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-i8mm-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-i8mm-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/i8mm-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-mte-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-mte-instructions.s index 4b40a1ca7dc8..96f38ab8d92d 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-mte-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-mte-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/mte-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/mte-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s index 7e53aa03caf7..9ee039d5ce61 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -mattr=+aes -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s index aee01b3e8bf8..f419c92eb81b 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/Inputs/rcpc-immo-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-sve-instructions.s index 6b3652b29996..1f3a9f6f1828 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-sve-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/Inputs/sve-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3 -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/../Inputs/sve-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s index e5c459fb704d..033500199bfd 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-basic-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/basic-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/basic-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-bf16-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-bf16-instructions.s index e244e0d64119..94513cc58735 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-bf16-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-bf16-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/bf16-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/bf16-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-complxnum-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-complxnum-instructions.s index eb4e5918b078..7a4ad033f461 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-complxnum-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-complxnum-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/complxnum-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/complxnum-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fp16fml-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fp16fml-instructions.s index d853614b37b1..0f58d035ea47 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fp16fml-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fp16fml-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/fp16fml-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/fp16fml-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fptoint-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fptoint-instructions.s index 4056a20f685d..b41ba6583f5d 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fptoint-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-fptoint-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/fptoint-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/fptoint-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-i8mm-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-i8mm-instructions.s index 0d30c2586283..e6ef3228b785 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-i8mm-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-i8mm-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/i8mm-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/i8mm-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s index 29516d3ece77..b37eff1ae2da 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-neon-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -mattr=+aes -instruction-tables < %p/Inputs/neon-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -mattr=+aes -instruction-tables < %p/../Inputs/neon-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s index 0fcf3bd0993f..68b4c1610017 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/Inputs/rcpc-immo-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -instruction-tables < %p/../Inputs/rcpc-immo-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s index 663968a6478b..bed7ffc9089e 100644 --- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s +++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-sve-instructions.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/Inputs/sve-instructions.s | FileCheck %s +# RUN: llvm-mca -mtriple=aarch64 -mcpu=neoverse-v3ae -mattr=+sve2-aes,+sve2-sha3,+sve2-sm4 -instruction-tables < %p/../Inputs/sve-instructions.s | FileCheck %s # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps