From 39c9dda1aa593bb129c7a2ef7724c212255a58d6 Mon Sep 17 00:00:00 2001
From: David Green <david.green@arm.com>
Date: Mon, 16 Dec 2024 15:46:48 +0000
Subject: [PATCH] [AArch64] Move SME_ZA_LDR and SME_ZA_STR into
 FIRST_TARGET_MEMORY_OPCODE. NFCI (#120091)

These opcodes are currently in the "strictfp" section. They should
either be in "memory", or moved into the generic ocodes.

Note that isTargetMemoryOpcode/FIRST_TARGET_MEMORY_OPCODE doesn't seem
to be used for anything at the moment.
---
 llvm/lib/Target/AArch64/AArch64ISelLowering.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index d51b36f7e499..4ab8e0103fa2 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -480,10 +480,6 @@ enum NodeType : unsigned {
   STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE,
   STRICT_FCMPE,
 
-  // SME ZA loads and stores
-  SME_ZA_LDR,
-  SME_ZA_STR,
-
   // NEON Load/Store with post-increment base updates
   LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
   LD3post,
@@ -520,6 +516,10 @@ enum NodeType : unsigned {
   STP,
   STILP,
   STNP,
+
+  // SME ZA loads and stores
+  SME_ZA_LDR,
+  SME_ZA_STR,
 };
 
 } // end namespace AArch64ISD