[LV] Conservatively predicate SDiv/SRem (#170818)
Conservatively predicate sdiv/srem: - RHS may carry poison in masked‑off lanes. - RHS could be −1 while LHS has masked‑off lanes (risking INT_MIN/−1 overflow). We’ll relax this once we can prove non‑wrap/non‑poison conditions. Fixes #170775.
This commit is contained in:
Shih-Po Hung
GitHub
parent
1eb0bbdea5
commit
39d6f10e33
@ -2902,11 +2902,14 @@ bool LoopVectorizationCostModel::isPredicatedInst(Instruction *I) const {
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TheLoop->isLoopInvariant(cast<StoreInst>(I)->getValueOperand()));
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}
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case Instruction::UDiv:
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case Instruction::SDiv:
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case Instruction::SRem:
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case Instruction::URem:
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// If the divisor is loop-invariant no predication is needed.
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return !Legal->isInvariant(I->getOperand(1));
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case Instruction::SDiv:
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case Instruction::SRem:
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// Conservative for now, since masked-off lanes may be poison and could
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// trigger signed overflow.
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return true;
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}
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}
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@ -85,7 +85,8 @@ define void @vector_sdiv(ptr noalias nocapture %a, i64 %v, i64 %n) {
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; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])
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; CHECK-NEXT: [[TMP9:%.*]] = sdiv <vscale x 2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[BROADCAST_SPLAT]], <vscale x 2 x i64> splat (i64 1), i32 [[TMP10]])
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; CHECK-NEXT: [[TMP9:%.*]] = sdiv <vscale x 2 x i64> [[WIDE_LOAD]], [[TMP2]]
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; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP9]], ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP10]] to i64
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP8]], [[INDEX]]
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@ -213,7 +214,8 @@ define void @vector_srem(ptr noalias nocapture %a, i64 %v, i64 %n) {
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; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A:%.*]], i64 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])
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; CHECK-NEXT: [[TMP9:%.*]] = srem <vscale x 2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[BROADCAST_SPLAT]], <vscale x 2 x i64> splat (i64 1), i32 [[TMP10]])
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; CHECK-NEXT: [[TMP9:%.*]] = srem <vscale x 2 x i64> [[WIDE_LOAD]], [[TMP2]]
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; CHECK-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP9]], ptr align 8 [[TMP7]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP10]])
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; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP10]] to i64
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[TMP8]], [[INDEX]]
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@ -102,6 +102,366 @@ exit:
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ret void
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}
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define void @test_sdiv_divisor_invariant_nonconst(ptr noalias %a, i64 %b, ptr noalias %c) {
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; IF-EVL-LABEL: define void @test_sdiv_divisor_invariant_nonconst(
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; IF-EVL-SAME: ptr noalias [[A:%.*]], i64 [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
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; IF-EVL-NEXT: [[LOOP_PREHEADER:.*:]]
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; IF-EVL-NEXT: br label %[[VECTOR_PH:.*]]
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; IF-EVL: [[VECTOR_PH]]:
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; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[B]], i64 0
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; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]
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; IF-EVL: [[VECTOR_BODY]]:
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; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IF-EVL-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; IF-EVL-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[A]], i64 [[EVL_BASED_IV]]
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; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP1]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
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; IF-EVL-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[BROADCAST_SPLAT]], <vscale x 2 x i64> splat (i64 1), i32 [[TMP0]])
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; IF-EVL-NEXT: [[TMP3:%.*]] = sdiv <vscale x 2 x i64> [[VP_OP_LOAD]], [[TMP2]]
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; IF-EVL-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[EVL_BASED_IV]]
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; IF-EVL-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP3]], ptr align 8 [[TMP4]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
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; IF-EVL-NEXT: [[TMP5:%.*]] = zext i32 [[TMP0]] to i64
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; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP5]], [[EVL_BASED_IV]]
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; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
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; IF-EVL-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; IF-EVL-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
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; IF-EVL: [[MIDDLE_BLOCK]]:
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; IF-EVL-NEXT: br label %[[EXIT:.*]]
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; IF-EVL: [[EXIT]]:
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; IF-EVL-NEXT: ret void
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;
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; NO-VP-LABEL: define void @test_sdiv_divisor_invariant_nonconst(
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; NO-VP-SAME: ptr noalias [[A:%.*]], i64 [[B:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
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; NO-VP-NEXT: [[LOOP_PREHEADER:.*]]:
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; NO-VP-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
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; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
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; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
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; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; NO-VP: [[VECTOR_PH]]:
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; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
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; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 1
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; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
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; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
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; NO-VP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[B]], i64 0
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; NO-VP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]
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; NO-VP: [[VECTOR_BODY]]:
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; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; NO-VP-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
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; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP4]], align 8
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; NO-VP-NEXT: [[TMP5:%.*]] = sdiv <vscale x 2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
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; NO-VP-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
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; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP5]], ptr [[TMP6]], align 8
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; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
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; NO-VP-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; NO-VP-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; NO-VP: [[MIDDLE_BLOCK]]:
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; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
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; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; NO-VP: [[SCALAR_PH]]:
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; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[LOOP_PREHEADER]] ]
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; NO-VP-NEXT: br label %[[LOOP:.*]]
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; NO-VP: [[LOOP]]:
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; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
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; NO-VP-NEXT: [[A_GEP:%.*]] = getelementptr i64, ptr [[A]], i64 [[IV]]
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; NO-VP-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_GEP]], align 8
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; NO-VP-NEXT: [[TMP9:%.*]] = sdiv i64 [[TMP8]], [[B]]
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; NO-VP-NEXT: [[C_GEP:%.*]] = getelementptr i64, ptr [[C]], i64 [[IV]]
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; NO-VP-NEXT: store i64 [[TMP9]], ptr [[C_GEP]], align 8
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; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
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; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
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; NO-VP: [[EXIT]]:
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; NO-VP-NEXT: ret void
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;
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loop.preheader:
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br label %loop
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loop:
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%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
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%a.gep = getelementptr i64, ptr %a, i64 %iv
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%0 = load i64, ptr %a.gep
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%2 = sdiv i64 %0, %b
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%c.gep = getelementptr i64, ptr %c, i64 %iv
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store i64 %2, ptr %c.gep
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%iv.next = add i64 %iv, 1
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%done = icmp eq i64 %iv.next, 1024
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br i1 %done, label %exit, label %loop
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exit:
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ret void
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}
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define void @test_sdiv_both_invariant_nonconst(ptr noalias %a, i64 %b, i64 %b2, ptr noalias %c) {
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; IF-EVL-LABEL: define void @test_sdiv_both_invariant_nonconst(
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; IF-EVL-SAME: ptr noalias [[A:%.*]], i64 [[B:%.*]], i64 [[B2:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
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; IF-EVL-NEXT: [[LOOP_PREHEADER:.*:]]
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; IF-EVL-NEXT: br label %[[VECTOR_PH:.*]]
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; IF-EVL: [[VECTOR_PH]]:
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; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[B]], i64 0
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; IF-EVL-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; IF-EVL-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[B2]], i64 0
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; IF-EVL-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT1]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]
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; IF-EVL: [[VECTOR_BODY]]:
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; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; IF-EVL-NEXT: [[TMP1:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
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; IF-EVL-NEXT: [[TMP2:%.*]] = getelementptr i64, ptr [[A]], i64 [[EVL_BASED_IV]]
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; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP2]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP1]])
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; IF-EVL-NEXT: [[TMP7:%.*]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> [[BROADCAST_SPLAT2]], <vscale x 2 x i64> splat (i64 1), i32 [[TMP1]])
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; IF-EVL-NEXT: [[TMP8:%.*]] = sdiv <vscale x 2 x i64> [[BROADCAST_SPLAT]], [[TMP7]]
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; IF-EVL-NEXT: [[TMP3:%.*]] = add <vscale x 2 x i64> [[VP_OP_LOAD]], [[TMP8]]
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; IF-EVL-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[EVL_BASED_IV]]
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; IF-EVL-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP3]], ptr align 8 [[TMP4]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP1]])
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; IF-EVL-NEXT: [[TMP5:%.*]] = zext i32 [[TMP1]] to i64
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; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP5]], [[EVL_BASED_IV]]
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; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
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; IF-EVL-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
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; IF-EVL-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; IF-EVL: [[MIDDLE_BLOCK]]:
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; IF-EVL-NEXT: br label %[[EXIT:.*]]
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; IF-EVL: [[EXIT]]:
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; IF-EVL-NEXT: ret void
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;
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; NO-VP-LABEL: define void @test_sdiv_both_invariant_nonconst(
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; NO-VP-SAME: ptr noalias [[A:%.*]], i64 [[B:%.*]], i64 [[B2:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
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; NO-VP-NEXT: [[LOOP_PREHEADER:.*]]:
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; NO-VP-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
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; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
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; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
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; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; NO-VP: [[VECTOR_PH]]:
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; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
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; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 1
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; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
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; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
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; NO-VP-NEXT: [[TMP4:%.*]] = sdiv i64 [[B]], [[B2]]
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; NO-VP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x i64> poison, i64 [[TMP4]], i64 0
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; NO-VP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 2 x i64> [[BROADCAST_SPLATINSERT]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]
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; NO-VP: [[VECTOR_BODY]]:
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; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; NO-VP-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
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; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP5]], align 8
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; NO-VP-NEXT: [[TMP6:%.*]] = add <vscale x 2 x i64> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
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; NO-VP-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
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; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP6]], ptr [[TMP7]], align 8
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; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
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; NO-VP-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; NO-VP-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
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; NO-VP: [[MIDDLE_BLOCK]]:
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; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
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; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
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; NO-VP: [[SCALAR_PH]]:
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; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[LOOP_PREHEADER]] ]
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; NO-VP-NEXT: br label %[[LOOP:.*]]
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; NO-VP: [[LOOP]]:
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; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
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; NO-VP-NEXT: [[A_GEP:%.*]] = getelementptr i64, ptr [[A]], i64 [[IV]]
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; NO-VP-NEXT: [[TMP9:%.*]] = load i64, ptr [[A_GEP]], align 8
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; NO-VP-NEXT: [[TMP10:%.*]] = sdiv i64 [[B]], [[B2]]
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; NO-VP-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], [[TMP10]]
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; NO-VP-NEXT: [[C_GEP:%.*]] = getelementptr i64, ptr [[C]], i64 [[IV]]
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; NO-VP-NEXT: store i64 [[TMP11]], ptr [[C_GEP]], align 8
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; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
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; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
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; NO-VP: [[EXIT]]:
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; NO-VP-NEXT: ret void
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;
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loop.preheader:
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br label %loop
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loop:
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%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %b, %b2
|
||||
%3 = add i64 %0, %2
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %3, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1024
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_sdiv_divisor_invariant_minusone(ptr noalias %a, ptr noalias %c) {
|
||||
; IF-EVL-LABEL: define void @test_sdiv_divisor_invariant_minusone(
|
||||
; IF-EVL-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
|
||||
; IF-EVL-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; IF-EVL-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; IF-EVL: [[VECTOR_PH]]:
|
||||
; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; IF-EVL: [[VECTOR_BODY]]:
|
||||
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; IF-EVL-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
|
||||
; IF-EVL-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[A]], i64 [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP1]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
|
||||
; IF-EVL-NEXT: [[TMP2:%.*]] = call <vscale x 2 x i64> @llvm.vp.merge.nxv2i64(<vscale x 2 x i1> splat (i1 true), <vscale x 2 x i64> splat (i64 -1), <vscale x 2 x i64> splat (i64 1), i32 [[TMP0]])
|
||||
; IF-EVL-NEXT: [[TMP3:%.*]] = sdiv <vscale x 2 x i64> [[VP_OP_LOAD]], [[TMP2]]
|
||||
; IF-EVL-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP3]], ptr align 8 [[TMP4]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
|
||||
; IF-EVL-NEXT: [[TMP5:%.*]] = zext i32 [[TMP0]] to i64
|
||||
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP5]], [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP5]]
|
||||
; IF-EVL-NEXT: [[TMP6:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
|
||||
; IF-EVL-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
|
||||
; IF-EVL: [[MIDDLE_BLOCK]]:
|
||||
; IF-EVL-NEXT: br label %[[EXIT:.*]]
|
||||
; IF-EVL: [[EXIT]]:
|
||||
; IF-EVL-NEXT: ret void
|
||||
;
|
||||
; NO-VP-LABEL: define void @test_sdiv_divisor_invariant_minusone(
|
||||
; NO-VP-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
|
||||
; NO-VP-NEXT: [[LOOP_PREHEADER:.*]]:
|
||||
; NO-VP-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
|
||||
; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
|
||||
; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
|
||||
; NO-VP: [[VECTOR_PH]]:
|
||||
; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 1
|
||||
; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
|
||||
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
|
||||
; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; NO-VP: [[VECTOR_BODY]]:
|
||||
; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; NO-VP-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
|
||||
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP4]], align 8
|
||||
; NO-VP-NEXT: [[TMP5:%.*]] = sdiv <vscale x 2 x i64> [[WIDE_LOAD]], splat (i64 -1)
|
||||
; NO-VP-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
|
||||
; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP5]], ptr [[TMP6]], align 8
|
||||
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
|
||||
; NO-VP-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
; NO-VP: [[MIDDLE_BLOCK]]:
|
||||
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
; NO-VP: [[SCALAR_PH]]:
|
||||
; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[LOOP_PREHEADER]] ]
|
||||
; NO-VP-NEXT: br label %[[LOOP:.*]]
|
||||
; NO-VP: [[LOOP]]:
|
||||
; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
|
||||
; NO-VP-NEXT: [[A_GEP:%.*]] = getelementptr i64, ptr [[A]], i64 [[IV]]
|
||||
; NO-VP-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_GEP]], align 8
|
||||
; NO-VP-NEXT: [[TMP9:%.*]] = sdiv i64 [[TMP8]], -1
|
||||
; NO-VP-NEXT: [[C_GEP:%.*]] = getelementptr i64, ptr [[C]], i64 [[IV]]
|
||||
; NO-VP-NEXT: store i64 [[TMP9]], ptr [[C_GEP]], align 8
|
||||
; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
; NO-VP: [[EXIT]]:
|
||||
; NO-VP-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %0, -1
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1024
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_sdiv_divisor_invariant_safeimm(ptr noalias %a, ptr noalias %c) {
|
||||
; IF-EVL-LABEL: define void @test_sdiv_divisor_invariant_safeimm(
|
||||
; IF-EVL-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
|
||||
; IF-EVL-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; IF-EVL-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; IF-EVL: [[VECTOR_PH]]:
|
||||
; IF-EVL-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; IF-EVL: [[VECTOR_BODY]]:
|
||||
; IF-EVL-NEXT: [[EVL_BASED_IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_EVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; IF-EVL-NEXT: [[AVL:%.*]] = phi i64 [ 1024, %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; IF-EVL-NEXT: [[TMP0:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
|
||||
; IF-EVL-NEXT: [[TMP1:%.*]] = getelementptr i64, ptr [[A]], i64 [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x i64> @llvm.vp.load.nxv2i64.p0(ptr align 8 [[TMP1]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
|
||||
; IF-EVL-NEXT: [[TMP2:%.*]] = sdiv <vscale x 2 x i64> [[VP_OP_LOAD]], splat (i64 3)
|
||||
; IF-EVL-NEXT: [[TMP3:%.*]] = getelementptr i64, ptr [[C]], i64 [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: call void @llvm.vp.store.nxv2i64.p0(<vscale x 2 x i64> [[TMP2]], ptr align 8 [[TMP3]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP0]])
|
||||
; IF-EVL-NEXT: [[TMP4:%.*]] = zext i32 [[TMP0]] to i64
|
||||
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP4]], [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP4]]
|
||||
; IF-EVL-NEXT: [[TMP5:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
|
||||
; IF-EVL-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
; IF-EVL: [[MIDDLE_BLOCK]]:
|
||||
; IF-EVL-NEXT: br label %[[EXIT:.*]]
|
||||
; IF-EVL: [[EXIT]]:
|
||||
; IF-EVL-NEXT: ret void
|
||||
;
|
||||
; NO-VP-LABEL: define void @test_sdiv_divisor_invariant_safeimm(
|
||||
; NO-VP-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) #[[ATTR0]] {
|
||||
; NO-VP-NEXT: [[LOOP_PREHEADER:.*]]:
|
||||
; NO-VP-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; NO-VP-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 1
|
||||
; NO-VP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
|
||||
; NO-VP-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
|
||||
; NO-VP: [[VECTOR_PH]]:
|
||||
; NO-VP-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
|
||||
; NO-VP-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 1
|
||||
; NO-VP-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
|
||||
; NO-VP-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
|
||||
; NO-VP-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; NO-VP: [[VECTOR_BODY]]:
|
||||
; NO-VP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; NO-VP-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[INDEX]]
|
||||
; NO-VP-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 2 x i64>, ptr [[TMP4]], align 8
|
||||
; NO-VP-NEXT: [[TMP5:%.*]] = sdiv <vscale x 2 x i64> [[WIDE_LOAD]], splat (i64 3)
|
||||
; NO-VP-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[C]], i64 [[INDEX]]
|
||||
; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP5]], ptr [[TMP6]], align 8
|
||||
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
|
||||
; NO-VP-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
|
||||
; NO-VP: [[MIDDLE_BLOCK]]:
|
||||
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
; NO-VP: [[SCALAR_PH]]:
|
||||
; NO-VP-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[LOOP_PREHEADER]] ]
|
||||
; NO-VP-NEXT: br label %[[LOOP:.*]]
|
||||
; NO-VP: [[LOOP]]:
|
||||
; NO-VP-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
|
||||
; NO-VP-NEXT: [[A_GEP:%.*]] = getelementptr i64, ptr [[A]], i64 [[IV]]
|
||||
; NO-VP-NEXT: [[TMP8:%.*]] = load i64, ptr [[A_GEP]], align 8
|
||||
; NO-VP-NEXT: [[TMP9:%.*]] = sdiv i64 [[TMP8]], 3
|
||||
; NO-VP-NEXT: [[C_GEP:%.*]] = getelementptr i64, ptr [[C]], i64 [[IV]]
|
||||
; NO-VP-NEXT: store i64 [[TMP9]], ptr [[C_GEP]], align 8
|
||||
; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
|
||||
; NO-VP: [[EXIT]]:
|
||||
; NO-VP-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %0, 3
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1024
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_udiv(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; IF-EVL-LABEL: define void @test_udiv(
|
||||
@ -126,7 +486,7 @@ define void @test_udiv(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP14]], [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP14]]
|
||||
; IF-EVL-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
|
||||
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
; IF-EVL: [[MIDDLE_BLOCK]]:
|
||||
; IF-EVL-NEXT: br label %[[EXIT:.*]]
|
||||
; IF-EVL: [[EXIT]]:
|
||||
@ -156,7 +516,7 @@ define void @test_udiv(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP8]], ptr [[TMP9]], align 8
|
||||
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
|
||||
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
|
||||
; NO-VP-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
|
||||
; NO-VP: [[MIDDLE_BLOCK]]:
|
||||
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
@ -174,7 +534,7 @@ define void @test_udiv(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; NO-VP-NEXT: store i64 [[TMP2]], ptr [[C_GEP]], align 8
|
||||
; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
|
||||
; NO-VP: [[EXIT]]:
|
||||
; NO-VP-NEXT: ret void
|
||||
;
|
||||
@ -221,7 +581,7 @@ define void @test_srem(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP14]], [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP14]]
|
||||
; IF-EVL-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
|
||||
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
|
||||
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
; IF-EVL: [[MIDDLE_BLOCK]]:
|
||||
; IF-EVL-NEXT: br label %[[EXIT:.*]]
|
||||
; IF-EVL: [[EXIT]]:
|
||||
@ -251,7 +611,7 @@ define void @test_srem(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP8]], ptr [[TMP9]], align 8
|
||||
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
|
||||
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
; NO-VP-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]]
|
||||
; NO-VP: [[MIDDLE_BLOCK]]:
|
||||
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
@ -269,7 +629,7 @@ define void @test_srem(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; NO-VP-NEXT: store i64 [[TMP2]], ptr [[C_GEP]], align 8
|
||||
; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP15:![0-9]+]]
|
||||
; NO-VP: [[EXIT]]:
|
||||
; NO-VP-NEXT: ret void
|
||||
;
|
||||
@ -316,7 +676,7 @@ define void @test_urem(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add nuw i64 [[TMP14]], [[EVL_BASED_IV]]
|
||||
; IF-EVL-NEXT: [[AVL_NEXT]] = sub nuw i64 [[AVL]], [[TMP14]]
|
||||
; IF-EVL-NEXT: [[TMP13:%.*]] = icmp eq i64 [[AVL_NEXT]], 0
|
||||
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
|
||||
; IF-EVL-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
; IF-EVL: [[MIDDLE_BLOCK]]:
|
||||
; IF-EVL-NEXT: br label %[[EXIT:.*]]
|
||||
; IF-EVL: [[EXIT]]:
|
||||
@ -346,7 +706,7 @@ define void @test_urem(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; NO-VP-NEXT: store <vscale x 2 x i64> [[TMP8]], ptr [[TMP9]], align 8
|
||||
; NO-VP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]]
|
||||
; NO-VP-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
; NO-VP-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]]
|
||||
; NO-VP: [[MIDDLE_BLOCK]]:
|
||||
; NO-VP-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
|
||||
; NO-VP-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
|
||||
@ -364,7 +724,7 @@ define void @test_urem(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; NO-VP-NEXT: store i64 [[TMP2]], ptr [[C_GEP]], align 8
|
||||
; NO-VP-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
|
||||
; NO-VP-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], 1024
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
|
||||
; NO-VP-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
|
||||
; NO-VP: [[EXIT]]:
|
||||
; NO-VP-NEXT: ret void
|
||||
;
|
||||
@ -394,6 +754,10 @@ exit:
|
||||
; IF-EVL: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
|
||||
; IF-EVL: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
|
||||
; IF-EVL: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}
|
||||
; IF-EVL: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
|
||||
; IF-EVL: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
|
||||
; IF-EVL: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
|
||||
; IF-EVL: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]}
|
||||
;.
|
||||
; NO-VP: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
|
||||
; NO-VP: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
|
||||
@ -405,4 +769,12 @@ exit:
|
||||
; NO-VP: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]}
|
||||
; NO-VP: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
|
||||
; NO-VP: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]}
|
||||
; NO-VP: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
|
||||
; NO-VP: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]}
|
||||
; NO-VP: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]}
|
||||
; NO-VP: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]}
|
||||
; NO-VP: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]}
|
||||
; NO-VP: [[LOOP15]] = distinct !{[[LOOP15]], [[META2]], [[META1]]}
|
||||
; NO-VP: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]}
|
||||
; NO-VP: [[LOOP17]] = distinct !{[[LOOP17]], [[META2]], [[META1]]}
|
||||
;.
|
||||
|
||||
@ -19,21 +19,45 @@ define void @sdiv_feeding_gep(ptr %dst, i32 %x, i64 %M, i64 %conv6, i64 %N) {
|
||||
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4
|
||||
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]]
|
||||
; CHECK-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[N]], 1
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = sdiv i64 [[M]], [[CONV6]]
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP17]] to i32
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = mul i64 [[TMP17]], [[CONV61]]
|
||||
; CHECK-NEXT: [[TMP23:%.*]] = mul i32 [[X]], [[TMP19]]
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_SDIV_CONTINUE8:.*]] ]
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3>
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT2]]
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP6]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP16]], label %[[PRED_SDIV_IF:.*]], label %[[PRED_SDIV_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_SDIV_IF]]:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = sdiv i64 [[M]], [[CONV6]]
|
||||
; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE]]
|
||||
; CHECK: [[PRED_SDIV_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = phi i64 [ poison, %[[VECTOR_BODY]] ], [ [[TMP7]], %[[PRED_SDIV_IF]] ]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP6]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_SDIV_IF3:.*]], label %[[PRED_SDIV_CONTINUE4:.*]]
|
||||
; CHECK: [[PRED_SDIV_IF3]]:
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = sdiv i64 [[M]], [[CONV6]]
|
||||
; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE4]]
|
||||
; CHECK: [[PRED_SDIV_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP6]], i32 2
|
||||
; CHECK-NEXT: br i1 [[TMP11]], label %[[PRED_SDIV_IF5:.*]], label %[[PRED_SDIV_CONTINUE6:.*]]
|
||||
; CHECK: [[PRED_SDIV_IF5]]:
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = sdiv i64 [[M]], [[CONV6]]
|
||||
; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE6]]
|
||||
; CHECK: [[PRED_SDIV_CONTINUE6]]:
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP6]], i32 3
|
||||
; CHECK-NEXT: br i1 [[TMP13]], label %[[PRED_SDIV_IF7:.*]], label %[[PRED_SDIV_CONTINUE8]]
|
||||
; CHECK: [[PRED_SDIV_IF7]]:
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = sdiv i64 [[M]], [[CONV6]]
|
||||
; CHECK-NEXT: br label %[[PRED_SDIV_CONTINUE8]]
|
||||
; CHECK: [[PRED_SDIV_CONTINUE8]]:
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = trunc i64 [[TMP8]] to i32
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = mul i64 [[TMP8]], [[CONV61]]
|
||||
; CHECK-NEXT: [[TMP21:%.*]] = sub i64 [[INDEX]], [[TMP20]]
|
||||
; CHECK-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
|
||||
; CHECK-NEXT: [[TMP23:%.*]] = mul i32 [[X]], [[TMP15]]
|
||||
; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP23]], [[TMP22]]
|
||||
; CHECK-NEXT: [[TMP25:%.*]] = sext i32 [[TMP24]] to i64
|
||||
; CHECK-NEXT: [[TMP26:%.*]] = getelementptr double, ptr [[DST]], i64 [[TMP25]]
|
||||
|
||||
@ -49,8 +49,6 @@ define void @sink_replicate_region_1(i32 %x, ptr %ptr, ptr noalias %dst) optsize
|
||||
; CHECK-NEXT: loop.0:
|
||||
; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext vp<[[PRED1]]> to i32
|
||||
; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0>, ir<%conv>
|
||||
; CHECK-NEXT: WIDEN ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: WIDEN ir<%add> = add ir<%conv>, ir<%rem>
|
||||
; CHECK-NEXT: Successor(s): pred.store
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: <xVFxUF> pred.store: {
|
||||
@ -59,16 +57,18 @@ define void @sink_replicate_region_1(i32 %x, ptr %ptr, ptr noalias %dst) optsize
|
||||
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: pred.store.if:
|
||||
; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[STEPS]]>
|
||||
; CHECK-NEXT: REPLICATE ir<%add> = add ir<%conv>, ir<%rem>
|
||||
; CHECK-NEXT: REPLICATE store ir<%add>, ir<%gep.dst>
|
||||
; CHECK-NEXT: Successor(s): pred.store.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: pred.store.continue:
|
||||
; CHECK-NEXT: No successors
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: Successor(s): loop.1
|
||||
; CHECK-NEXT: Successor(s): loop.2
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: loop.1:
|
||||
; CHECK-NEXT: loop.2:
|
||||
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
|
||||
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
|
||||
; CHECK-NEXT: No successors
|
||||
@ -210,10 +210,27 @@ define i32 @sink_replicate_region_3_reduction(i32 %x, i8 %y, ptr %ptr) optsize {
|
||||
; CHECK-NEXT: EMIT vp<[[WIDEN_CAN:%.+]]> = WIDEN-CANONICAL-INDUCTION vp<[[CAN_IV]]>
|
||||
; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule vp<[[WIDEN_CAN]]>, vp<[[BTC]]>
|
||||
; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next>
|
||||
; CHECK-NEXT: WIDEN ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: WIDEN ir<%add> = add ir<%rem>, ir<%recur.next>
|
||||
; CHECK-NEXT: Successor(s): pred.srem
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: <xVFxUF> pred.srem: {
|
||||
; CHECK-NEXT: pred.srem.entry:
|
||||
; CHECK-NEXT: BRANCH-ON-MASK vp<[[MASK]]>
|
||||
; CHECK-NEXT: Successor(s): pred.srem.if, pred.srem.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: pred.srem.if:
|
||||
; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: Successor(s): pred.srem.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: pred.srem.continue:
|
||||
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%8> = ir<%rem>
|
||||
; CHECK-NEXT: No successors
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: Successor(s): loop.0
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: loop.0:
|
||||
; CHECK-NEXT: WIDEN ir<%add> = add vp<%8>, ir<%recur.next>
|
||||
; CHECK-NEXT: WIDEN ir<%and.red.next> = and ir<%and.red>, ir<%add>
|
||||
; CHECK-NEXT: EMIT vp<[[SEL:%.+]]> = select vp<[[MASK]]>, ir<%and.red.next>, ir<%and.red>
|
||||
; CHECK-NEXT: EMIT vp<[[SEL:%.+]]> = select vp<%6>, ir<%and.red.next>, ir<%and.red>
|
||||
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
|
||||
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
|
||||
; CHECK-NEXT: No successors
|
||||
@ -293,7 +310,6 @@ define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, ptr
|
||||
; CHECK-NEXT: loop.0:
|
||||
; CHECK-NEXT: WIDEN-CAST ir<%conv> = sext vp<[[PRED]]> to i32
|
||||
; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%0>, ir<%conv>
|
||||
; CHECK-NEXT: WIDEN ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: Successor(s): pred.load
|
||||
; CHECK-EMPTY:
|
||||
; CHECK: <xVFxUF> pred.load: {
|
||||
@ -302,18 +318,20 @@ define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, ptr
|
||||
; CHECK-NEXT: Successor(s): pred.load.if, pred.load.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK: pred.load.if:
|
||||
; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: REPLICATE ir<%lv.2> = load ir<%gep> (S->V)
|
||||
; CHECK-NEXT: Successor(s): pred.load.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK: pred.load.continue:
|
||||
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%9> = ir<%lv.2>
|
||||
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<[[REMPHI:%.+]]> = ir<%rem>
|
||||
; CHECK-NEXT: PHI-PREDICATED-INSTRUCTION vp<%10> = ir<%lv.2>
|
||||
; CHECK-NEXT: No successors
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: Successor(s): loop.1
|
||||
; CHECK-NEXT: Successor(s): loop.2
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: loop.1:
|
||||
; CHECK-NEXT: WIDEN ir<%add.1> = add ir<%conv>, ir<%rem>
|
||||
; CHECK-NEXT: WIDEN-CAST ir<%conv.lv.2> = sext vp<%9> to i32
|
||||
; CHECK-NEXT: loop.2:
|
||||
; CHECK-NEXT: WIDEN ir<%add.1> = add ir<%conv>, vp<[[REMPHI]]>
|
||||
; CHECK-NEXT: WIDEN-CAST ir<%conv.lv.2> = sext vp<%10> to i32
|
||||
; CHECK-NEXT: WIDEN ir<%add> = add ir<%add.1>, ir<%conv.lv.2>
|
||||
; CHECK-NEXT: Successor(s): pred.store
|
||||
; CHECK-EMPTY:
|
||||
@ -330,9 +348,9 @@ define void @sink_replicate_region_4_requires_split_at_end_of_block(i32 %x, ptr
|
||||
; CHECK-NEXT: pred.store.continue:
|
||||
; CHECK-NEXT: No successors
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: Successor(s): loop.2
|
||||
; CHECK-NEXT: Successor(s): loop.3
|
||||
; CHECK-EMPTY:
|
||||
; CHECK: loop.2:
|
||||
; CHECK: loop.3:
|
||||
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
|
||||
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
|
||||
; CHECK-NEXT: No successors
|
||||
@ -394,7 +412,6 @@ define void @sink_replicate_region_after_replicate_region(ptr %ptr, ptr noalias
|
||||
; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION ir<0>, ir<1>, vp<[[VF]]>
|
||||
; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv>, vp<[[BTC]]>
|
||||
; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%recur>, ir<%recur.next>
|
||||
; CHECK-NEXT: WIDEN ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: Successor(s): pred.store
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: <xVFxUF> pred.store: {
|
||||
@ -404,6 +421,7 @@ define void @sink_replicate_region_after_replicate_region(ptr %ptr, ptr noalias
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: pred.store.if:
|
||||
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
|
||||
; CHECK-NEXT: REPLICATE ir<%rem> = srem vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: REPLICATE ir<%rem.div> = sdiv ir<20>, ir<%rem>
|
||||
; CHECK-NEXT: REPLICATE ir<%gep> = getelementptr ir<%ptr>, vp<[[STEPS]]>
|
||||
; CHECK-NEXT: REPLICATE store ir<%rem.div>, ir<%gep>
|
||||
@ -414,9 +432,9 @@ define void @sink_replicate_region_after_replicate_region(ptr %ptr, ptr noalias
|
||||
; CHECK-NEXT: pred.store.continue:
|
||||
; CHECK-NEXT: No successors
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: Successor(s): loop.2
|
||||
; CHECK-NEXT: Successor(s): loop.3
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: loop.2:
|
||||
; CHECK-NEXT: loop.3:
|
||||
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
|
||||
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
|
||||
; CHECK-NEXT: No successors
|
||||
@ -474,7 +492,6 @@ define void @need_new_block_after_sinking_pr56146(i32 %x, ptr %src, ptr noalias
|
||||
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp ule vp<[[WIDE_IV]]>, vp<[[BTC]]>
|
||||
; CHECK-NEXT: CLONE ir<[[L]]> = load ir<%src>
|
||||
; CHECK-NEXT: EMIT vp<[[SPLICE:%.+]]> = first-order splice ir<%.pn>, ir<[[L]]>
|
||||
; CHECK-NEXT: WIDEN ir<%val> = sdiv vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: Successor(s): pred.store
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: <xVFxUF> pred.store: {
|
||||
@ -483,6 +500,7 @@ define void @need_new_block_after_sinking_pr56146(i32 %x, ptr %src, ptr noalias
|
||||
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: pred.store.if:
|
||||
; CHECK-NEXT: REPLICATE ir<%val> = sdiv vp<[[SPLICE]]>, ir<%x>
|
||||
; CHECK-NEXT: vp<[[SCALAR_STEPS:%.+]]> = SCALAR-STEPS vp<[[DERIVED_IV]]>, ir<1>, vp<[[VF]]>
|
||||
; CHECK-NEXT: REPLICATE ir<%gep.dst> = getelementptr ir<%dst>, vp<[[SCALAR_STEPS]]>
|
||||
; CHECK-NEXT: REPLICATE store ir<%val>, ir<%gep.dst>
|
||||
@ -491,9 +509,9 @@ define void @need_new_block_after_sinking_pr56146(i32 %x, ptr %src, ptr noalias
|
||||
; CHECK-NEXT: pred.store.continue:
|
||||
; CHECK-NEXT: No successors
|
||||
; CHECK-NEXT: }
|
||||
; CHECK-NEXT: Successor(s): loop.0
|
||||
; CHECK-NEXT: Successor(s): loop.1
|
||||
; CHECK-EMPTY:
|
||||
; CHECK-NEXT: loop.0:
|
||||
; CHECK-NEXT: loop.1:
|
||||
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
|
||||
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
|
||||
; CHECK-NEXT: No successors
|
||||
|
||||
@ -115,7 +115,8 @@ define void @loop_invariant_srem(ptr %p, i64 %a, i8 %b) {
|
||||
; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> [[TMP3]], <4 x i32> [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i32> [[PREDPHI]], splat (i32 8)
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = trunc <4 x i32> [[TMP7]] to <4 x i8>
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = srem <4 x i8> [[VEC_IND1]], [[TMP8]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP4]], <4 x i8> [[TMP8]], <4 x i8> splat (i8 1)
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = srem <4 x i8> [[VEC_IND1]], [[TMP9]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP4]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP10]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
|
||||
555
llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
Normal file
555
llvm/test/Transforms/LoopVectorize/tail-folding-div.ll
Normal file
@ -0,0 +1,555 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
|
||||
; RUN: opt -S --passes=loop-vectorize -prefer-predicate-over-epilogue=predicate-dont-vectorize -force-vector-width=2 < %s | FileCheck %s
|
||||
|
||||
; No predicate for sdiv because RHS has no masked-off lanes.
|
||||
define void @test_sdiv_variant_divisor_induction(ptr noalias %a, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_variant_divisor_induction(
|
||||
; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <2 x i64> [ <i64 1, i64 2>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE4]] ]
|
||||
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 1
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[INDEX]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[VEC_IV:%.*]] = add <2 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1>
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <2 x i64> [[VEC_IV]], splat (i64 1024)
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF]]:
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP5]], i32 0
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF1]]:
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP10]], i32 1
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i64> [ [[TMP7]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP11]], %[[PRED_LOAD_IF1]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> [[VEC_IND1]], <2 x i64> splat (i64 1)
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = sdiv <2 x i64> [[TMP12]], [[VEC_IND]]
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i64> [[TMP13]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP16]], ptr [[TMP15]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_IF3]]:
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i64> [[TMP13]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP19]], ptr [[TMP18]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND1]], splat (i64 2)
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 1, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %0, %iv
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1026
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Predicate for sdiv because RHS have masked-off lanes.
|
||||
define void @test_sdiv_variant_divisor_load(ptr noalias %a, ptr noalias %b, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_variant_divisor_load(
|
||||
; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE4]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <2 x i16> [[VEC_IND]], splat (i16 1024)
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF]]:
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP5]], i32 0
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i64, ptr [[B]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP7]], align 4
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = insertelement <2 x i64> poison, i64 [[TMP8]], i32 0
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP9]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP12]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF1]]:
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 4
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = insertelement <2 x i64> [[TMP10]], i64 [[TMP14]], i32 1
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[B]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = load i64, ptr [[TMP16]], align 4
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = insertelement <2 x i64> [[TMP11]], i64 [[TMP17]], i32 1
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = phi <2 x i64> [ [[TMP10]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP15]], %[[PRED_LOAD_IF1]] ]
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = phi <2 x i64> [ [[TMP11]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP18]], %[[PRED_LOAD_IF1]] ]
|
||||
; CHECK-NEXT: [[TMP21:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> [[TMP20]], <2 x i64> splat (i64 1)
|
||||
; CHECK-NEXT: [[TMP22:%.*]] = sdiv <2 x i64> [[TMP19]], [[TMP21]]
|
||||
; CHECK-NEXT: [[TMP23:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP23]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP25:%.*]] = extractelement <2 x i64> [[TMP22]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP25]], ptr [[TMP24]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP26:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP26]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_IF3]]:
|
||||
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP28:%.*]] = extractelement <2 x i64> [[TMP22]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP28]], ptr [[TMP27]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
|
||||
; CHECK-NEXT: [[TMP29:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%b.gep = getelementptr i64, ptr %b, i64 %iv
|
||||
%1 = load i64, ptr %b.gep
|
||||
%2 = sdiv i64 %0, %1
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1025
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Predicate for sdiv because RHS may be -1.
|
||||
define void @test_sdiv_invariant_divisor_nonconst(ptr noalias %a, i64 %b, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_invariant_divisor_nonconst(
|
||||
; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[B:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[B]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE4]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <2 x i16> [[VEC_IND]], splat (i16 1024)
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF]]:
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP5]], i32 0
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF1]]:
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP10]], i32 1
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i64> [ [[TMP7]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP11]], %[[PRED_LOAD_IF1]] ]
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> [[BROADCAST_SPLAT]], <2 x i64> splat (i64 1)
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = sdiv <2 x i64> [[TMP12]], [[TMP13]]
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i64> [[TMP14]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP17]], ptr [[TMP16]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_IF3]]:
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i64> [[TMP14]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP20]], ptr [[TMP19]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
|
||||
; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %0, %b
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1025
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; Predicate for sdiv because RHS is -1.
|
||||
define void @test_sdiv_invariant_divisor_minusone(ptr noalias %a, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_invariant_divisor_minusone(
|
||||
; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE4]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <2 x i16> [[VEC_IND]], splat (i16 1024)
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF]]:
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP5]], i32 0
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF1]]:
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP10]], i32 1
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i64> [ [[TMP7]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP11]], %[[PRED_LOAD_IF1]] ]
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> [[TMP2]], <2 x i64> splat (i64 -1), <2 x i64> splat (i64 1)
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = sdiv <2 x i64> [[TMP12]], [[TMP13]]
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i64> [[TMP14]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP17]], ptr [[TMP16]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_IF3]]:
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i64> [[TMP14]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP20]], ptr [[TMP19]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
|
||||
; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %0, -1
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1025
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; No predicate for sdiv because RHS is 3.
|
||||
define void @test_sdiv_invariant_divisor_safeimm(ptr noalias %a, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_invariant_divisor_safeimm(
|
||||
; CHECK-SAME: ptr noalias [[A:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE4:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE4]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = icmp ule <2 x i16> [[VEC_IND]], splat (i16 1024)
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP3]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF]]:
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP4]], align 4
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> poison, i64 [[TMP5]], i32 0
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP6]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP8]], label %[[PRED_LOAD_IF1:.*]], label %[[PRED_LOAD_CONTINUE2:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF1]]:
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP9]], align 4
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = insertelement <2 x i64> [[TMP7]], i64 [[TMP10]], i32 1
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE2]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = phi <2 x i64> [ [[TMP7]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP11]], %[[PRED_LOAD_IF1]] ]
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = sdiv <2 x i64> [[TMP12]], splat (i64 3)
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP2]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP14]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP0]]
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <2 x i64> [[TMP13]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP16]], ptr [[TMP15]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i1> [[TMP2]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP17]], label %[[PRED_STORE_IF3:.*]], label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_IF3]]:
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = extractelement <2 x i64> [[TMP13]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP19]], ptr [[TMP18]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE4]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %0, 3
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1025
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; No predicate for sdiv because LHS & RHS has no masked-off lanes.
|
||||
define void @test_sdiv_variant_dividend_induction(i64 %a, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_variant_dividend_induction(
|
||||
; CHECK-SAME: i64 [[A:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[A]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE2:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 0, i64 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE2]] ]
|
||||
; CHECK-NEXT: [[TMP0:%.*]] = icmp ule <2 x i64> [[VEC_IND]], splat (i64 1024)
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = select <2 x i1> [[TMP0]], <2 x i64> [[BROADCAST_SPLAT]], <2 x i64> splat (i64 1)
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = sdiv <2 x i64> [[VEC_IND]], [[TMP11]]
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i1> [[TMP0]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP2]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP3]]
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i64> [[TMP1]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP5]], ptr [[TMP4]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i1> [[TMP0]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP6]], label %[[PRED_STORE_IF1:.*]], label %[[PRED_STORE_CONTINUE2]]
|
||||
; CHECK: [[PRED_STORE_IF1]]:
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP7]]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i64> [[TMP1]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP8]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE2]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE2]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[VEC_IND]], splat (i64 2)
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%2 = sdiv i64 %iv, %a
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %2, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1025
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
||||
; No predicate for sdiv because both LHS & RHS have no masked-off lanes.
|
||||
define void @test_sdiv_both_invariant_nonconst(ptr noalias %a, i64 %b, i64 %b2, ptr noalias %c) {
|
||||
; CHECK-LABEL: define void @test_sdiv_both_invariant_nonconst(
|
||||
; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[B:%.*]], i64 [[B2:%.*]], ptr noalias [[C:%.*]]) {
|
||||
; CHECK-NEXT: [[LOOP_PREHEADER:.*:]]
|
||||
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
|
||||
; CHECK: [[VECTOR_PH]]:
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i64> poison, i64 [[B]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT]], <2 x i64> poison, <2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <2 x i64> poison, i64 [[B2]], i64 0
|
||||
; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <2 x i64> [[BROADCAST_SPLATINSERT1]], <2 x i64> poison, <2 x i32> zeroinitializer
|
||||
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
|
||||
; CHECK: [[VECTOR_BODY]]:
|
||||
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE6:.*]] ]
|
||||
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i16> [ <i16 0, i16 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE6]] ]
|
||||
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0
|
||||
; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1
|
||||
; CHECK-NEXT: [[TMP3:%.*]] = icmp ule <2 x i16> [[VEC_IND]], splat (i16 1024)
|
||||
; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP4]], label %[[PRED_LOAD_IF:.*]], label %[[PRED_LOAD_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF]]:
|
||||
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 4
|
||||
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <2 x i64> poison, i64 [[TMP6]], i32 0
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP8:%.*]] = phi <2 x i64> [ poison, %[[VECTOR_BODY]] ], [ [[TMP7]], %[[PRED_LOAD_IF]] ]
|
||||
; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP9]], label %[[PRED_LOAD_IF3:.*]], label %[[PRED_LOAD_CONTINUE4:.*]]
|
||||
; CHECK: [[PRED_LOAD_IF3]]:
|
||||
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i64, ptr [[A]], i64 [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP10]], align 4
|
||||
; CHECK-NEXT: [[TMP12:%.*]] = insertelement <2 x i64> [[TMP8]], i64 [[TMP11]], i32 1
|
||||
; CHECK-NEXT: br label %[[PRED_LOAD_CONTINUE4]]
|
||||
; CHECK: [[PRED_LOAD_CONTINUE4]]:
|
||||
; CHECK-NEXT: [[TMP22:%.*]] = phi <2 x i64> [ [[TMP8]], %[[PRED_LOAD_CONTINUE]] ], [ [[TMP12]], %[[PRED_LOAD_IF3]] ]
|
||||
; CHECK-NEXT: [[TMP13:%.*]] = select <2 x i1> [[TMP3]], <2 x i64> [[BROADCAST_SPLAT2]], <2 x i64> splat (i64 1)
|
||||
; CHECK-NEXT: [[TMP23:%.*]] = sdiv <2 x i64> [[BROADCAST_SPLAT]], [[TMP13]]
|
||||
; CHECK-NEXT: [[TMP14:%.*]] = add <2 x i64> [[TMP22]], [[TMP23]]
|
||||
; CHECK-NEXT: [[TMP15:%.*]] = extractelement <2 x i1> [[TMP3]], i32 0
|
||||
; CHECK-NEXT: br i1 [[TMP15]], label %[[PRED_STORE_IF:.*]], label %[[PRED_STORE_CONTINUE:.*]]
|
||||
; CHECK: [[PRED_STORE_IF]]:
|
||||
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP1]]
|
||||
; CHECK-NEXT: [[TMP17:%.*]] = extractelement <2 x i64> [[TMP14]], i32 0
|
||||
; CHECK-NEXT: store i64 [[TMP17]], ptr [[TMP16]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE]]:
|
||||
; CHECK-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[TMP3]], i32 1
|
||||
; CHECK-NEXT: br i1 [[TMP18]], label %[[PRED_STORE_IF5:.*]], label %[[PRED_STORE_CONTINUE6]]
|
||||
; CHECK: [[PRED_STORE_IF5]]:
|
||||
; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i64, ptr [[C]], i64 [[TMP2]]
|
||||
; CHECK-NEXT: [[TMP20:%.*]] = extractelement <2 x i64> [[TMP14]], i32 1
|
||||
; CHECK-NEXT: store i64 [[TMP20]], ptr [[TMP19]], align 4
|
||||
; CHECK-NEXT: br label %[[PRED_STORE_CONTINUE6]]
|
||||
; CHECK: [[PRED_STORE_CONTINUE6]]:
|
||||
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
|
||||
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i16> [[VEC_IND]], splat (i16 2)
|
||||
; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1026
|
||||
; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
|
||||
; CHECK: [[MIDDLE_BLOCK]]:
|
||||
; CHECK-NEXT: br label %[[EXIT:.*]]
|
||||
; CHECK: [[EXIT]]:
|
||||
; CHECK-NEXT: ret void
|
||||
;
|
||||
loop.preheader:
|
||||
br label %loop
|
||||
|
||||
loop:
|
||||
%iv = phi i64 [ %iv.next, %loop ], [ 0, %loop.preheader ]
|
||||
%a.gep = getelementptr i64, ptr %a, i64 %iv
|
||||
%0 = load i64, ptr %a.gep
|
||||
%2 = sdiv i64 %b, %b2
|
||||
%3 = add i64 %0, %2
|
||||
%c.gep = getelementptr i64, ptr %c, i64 %iv
|
||||
store i64 %3, ptr %c.gep
|
||||
%iv.next = add i64 %iv, 1
|
||||
%done = icmp eq i64 %iv.next, 1025
|
||||
br i1 %done, label %exit, label %loop
|
||||
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
;.
|
||||
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
|
||||
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
|
||||
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
|
||||
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]}
|
||||
; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
|
||||
; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]}
|
||||
; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
|
||||
; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]}
|
||||
; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
|
||||
;.
|
||||
Loading…
x
Reference in New Issue
Block a user