From 3d7eedce5658c41a1b22775938359bfafac47fc9 Mon Sep 17 00:00:00 2001 From: Jim Lin Date: Thu, 2 Apr 2026 08:21:33 +0800 Subject: [PATCH] [RISCV] Fix stackmap shadow trimming NOP size for compressed targets (#189774) The shadow trimming loop in LowerSTACKMAP hardcoded a 4-byte decrement per instruction, but when Zca is enabled NOPs are 2 bytes. Use NOPBytes instead of the hardcoded 4 so the shadow is correctly trimmed on compressed targets. Co-authored-by: Claude Opus 4.6 --- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 2 +- llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index eb15227a72a8..1c79d65db9cd 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -155,7 +155,7 @@ void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, MII->getOpcode() == TargetOpcode::STACKMAP) break; ++MII; - NumNOPBytes -= 4; + NumNOPBytes -= NOPBytes; } // Emit nops. diff --git a/llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll b/llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll index 68a7702a3df6..96d7f3349695 100644 --- a/llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll +++ b/llvm/test/CodeGen/RISCV/rv64-stackmap-nops.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=riscv64 | FileCheck %s +; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -mtriple=riscv64 -mattr=+c | FileCheck %s --check-prefix=RVC define void @test_shadow_optimization() { ; CHECK-LABEL: test_shadow_optimization: @@ -9,8 +10,19 @@ define void @test_shadow_optimization() { ; CHECK-NEXT: nop ; CHECK-NEXT: nop ; CHECK-NEXT: ret +; +; RVC-LABEL: test_shadow_optimization: +; RVC: # %bb.0: # %entry +; RVC-NEXT: .Ltmp0: +; RVC-NEXT: nop +; RVC-NEXT: nop +; RVC-NEXT: nop +; RVC-NEXT: nop +; RVC-NEXT: nop +; RVC-NEXT: nop +; RVC-NEXT: nop +; RVC-NEXT: ret entry: tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 16) ret void } -