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[X86] Teach combineToExtendBoolVectorInReg to create opportunities for using broadcast load instructions.

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If we're inserting a scalar that is smaller than the element
size of the final VT, the value of the extra bits doesn't matter.

Previously we any_extended in the scalar domain before inserting.

This patch changes this to use a broadcast of the original
scalar type and then a bitcast to the final type. This might
enable the use of a broadcast load.

This recovers regressions from 07d68c24aa19483e44db4336b0935b00a5d69949
and 9fcd212e2f678fdbdf304399a1e58ca490dc54d1 without relying on
alignment of the load.

Differential Revision: https://reviews.llvm.org/D75835
This commit is contained in:
Craig Topper 2020-03-09 10:35:31 -07:00
parent 8fc9eea43a
commit 3dcc0db15e
5 changed files with 29 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -44278,6 +44278,21 @@ combineToExtendBoolVectorInReg(SDNode *N, SelectionDAG &DAG,
for (unsigned i = 0; i != Scale; ++i)
ShuffleMask.append(EltSizeInBits, i);
Vec = DAG.getVectorShuffle(VT, DL, Vec, Vec, ShuffleMask);
} else if (Subtarget.hasAVX2() && NumElts < EltSizeInBits &&
(SclVT == MVT::i8 || SclVT == MVT::i16 || SclVT == MVT::i32)) {
// If we have register broadcast instructions, use the scalar size as the
// element type for the shuffle. Then cast to the wider element type. The
// widened bits won't be used, and this might allow the use of a broadcast
// load.
assert((EltSizeInBits % NumElts) == 0 && "Unexpected integer scale");
unsigned Scale = EltSizeInBits / NumElts;
EVT BroadcastVT =
EVT::getVectorVT(*DAG.getContext(), SclVT, NumElts * Scale);
Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, BroadcastVT, N00);
ShuffleMask.append(NumElts * Scale, 0);
Vec = DAG.getVectorShuffle(BroadcastVT, DL, Vec, Vec, ShuffleMask);
Vec = DAG.getBitcast(VT, Vec);
} else {
// For smaller scalar integers, we can simply any-extend it to the vector
// element size (we don't care about the upper bits) and broadcast it to all
@ -44285,8 +44300,8 @@ combineToExtendBoolVectorInReg(SDNode *N, SelectionDAG &DAG,
SDValue Scl = DAG.getAnyExtOrTrunc(N00, DL, SVT);
Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Scl);
ShuffleMask.append(NumElts, 0);
Vec = DAG.getVectorShuffle(VT, DL, Vec, Vec, ShuffleMask);
}
Vec = DAG.getVectorShuffle(VT, DL, Vec, Vec, ShuffleMask);
// Now, mask the relevant bit in each element.
SmallVector<SDValue, 32> Bits;

11
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
View File

@ -114,7 +114,7 @@ define <8 x i16> @ext_i8_8i16(i8 %a0) {
; AVX2-LABEL: ext_i8_8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
@ -273,7 +273,7 @@ define <8 x i32> @ext_i8_8i32(i8 %a0) {
; AVX2-LABEL: ext_i8_8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
@ -456,9 +456,8 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
;
; AVX2-LABEL: ext_i8_8i64:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $edi killed $edi def $rdi
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm1
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8]
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpcmpeqq %ymm0, %ymm2, %ymm0
@ -525,7 +524,7 @@ define <16 x i32> @ext_i16_16i32(i16 %a0) {
; AVX2-LABEL: ext_i16_16i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastd %xmm0, %ymm1
; AVX2-NEXT: vpbroadcastw %xmm0, %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm2, %ymm0

11
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
View File

@ -141,7 +141,7 @@ define <8 x i16> @ext_i8_8i16(i8 %a0) {
; AVX2-LABEL: ext_i8_8i16:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
@ -344,7 +344,7 @@ define <8 x i32> @ext_i8_8i32(i8 %a0) {
; AVX2-LABEL: ext_i8_8i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0
@ -583,9 +583,8 @@ define <8 x i64> @ext_i8_8i64(i8 %a0) {
;
; AVX2-LABEL: ext_i8_8i64:
; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $edi killed $edi def $rdi
; AVX2-NEXT: vmovq %rdi, %xmm0
; AVX2-NEXT: vpbroadcastq %xmm0, %ymm1
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastb %xmm0, %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8]
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpcmpeqq %ymm0, %ymm2, %ymm0
@ -670,7 +669,7 @@ define <16 x i32> @ext_i16_16i32(i16 %a0) {
; AVX2-LABEL: ext_i16_16i32:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastd %xmm0, %ymm1
; AVX2-NEXT: vpbroadcastw %xmm0, %ymm1
; AVX2-NEXT: vmovdqa {{.*#+}} ymm0 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vpcmpeqd %ymm0, %ymm2, %ymm0

2
llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
View File

@ -115,7 +115,7 @@ define <8 x i1> @bitcast_i8_8i1(i8 zeroext %a0) {
; AVX2-LABEL: bitcast_i8_8i1:
; AVX2: # %bb.0:
; AVX2-NEXT: vmovd %edi, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastb %xmm0, %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0

7
llvm/test/CodeGen/X86/vector-sext.ll
View File

@ -2039,9 +2039,7 @@ define <8 x i16> @load_sext_8i1_to_8i16(<8 x i1> *%ptr) {
;
; AVX2-LABEL: load_sext_8i1_to_8i16:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: movzwl (%rdi), %eax
; AVX2-NEXT: vmovd %eax, %xmm0
; AVX2-NEXT: vpbroadcastw %xmm0, %xmm0
; AVX2-NEXT: vpbroadcastb (%rdi), %xmm0
; AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
@ -2261,8 +2259,7 @@ define <8 x i32> @load_sext_8i1_to_8i32(<8 x i1> *%ptr) {
;
; AVX2-LABEL: load_sext_8i1_to_8i32:
; AVX2: # %bb.0: # %entry
; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX2-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-NEXT: vpbroadcastb (%rdi), %ymm0
; AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1,2,4,8,16,32,64,128]
; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
; AVX2-NEXT: vpcmpeqd %ymm1, %ymm0, %ymm0