[AMDGPU] Add ML-oriented coexec scheduler selection and queue handling (#169616)
This patch adds the initial coexec scheduler scaffold for machine learning workloads on gfx1250. It introduces function and module-level controls for selecting the AMDGPU preRA and postRA schedulers, including an `amdgpu-workload-type` module flag that maps ML workloads to coexec preRA scheduling and a nop postRA scheduler by default. It also updates the coexec scheduler to use a simplified top-down candidate selection path that considers both available and pending queues through a single flow, setting up follow-on heuristic work.
This commit is contained in:
Austin Kerbow
GitHub
parent
d69c670934
commit
3e4efe3ed4
283
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
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283
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
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@ -0,0 +1,283 @@
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//===- AMDGPUCoExecSchedStrategy.cpp - CoExec Scheduling Strategy ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Coexecution-focused scheduling strategy for AMDGPU.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUCoExecSchedStrategy.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-scheduler"
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namespace {
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// Used to disable post-RA scheduling with function level granularity.
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class GCNNoopPostScheduleDAG final : public ScheduleDAGInstrs {
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public:
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explicit GCNNoopPostScheduleDAG(MachineSchedContext *C)
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: ScheduleDAGInstrs(*C->MF, C->MLI, /*RemoveKillFlags=*/true) {}
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// Do nothing.
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void schedule() override {}
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};
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} // namespace
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static SUnit *pickOnlyChoice(SchedBoundary &Zone) {
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// pickOnlyChoice() releases pending instructions and checks for new hazards.
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SUnit *OnlyChoice = Zone.pickOnlyChoice();
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if (!Zone.Pending.empty())
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return nullptr;
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return OnlyChoice;
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}
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AMDGPUCoExecSchedStrategy::AMDGPUCoExecSchedStrategy(
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const MachineSchedContext *C)
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: GCNSchedStrategy(C) {
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SchedStages.push_back(GCNSchedStageID::ILPInitialSchedule);
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SchedStages.push_back(GCNSchedStageID::PreRARematerialize);
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// Use more accurate GCN pressure trackers.
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UseGCNTrackers = true;
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}
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void AMDGPUCoExecSchedStrategy::initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) {
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GCNSchedStrategy::initPolicy(Begin, End, NumRegionInstrs);
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assert((PreRADirection == MISched::Unspecified ||
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PreRADirection == MISched::TopDown) &&
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"coexec scheduler only supports top-down scheduling");
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RegionPolicy.OnlyTopDown = true;
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RegionPolicy.OnlyBottomUp = false;
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}
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void AMDGPUCoExecSchedStrategy::initialize(ScheduleDAGMI *DAG) {
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// Coexecution scheduling strategy is only done top-down to support new
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// resource balancing heuristics.
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RegionPolicy.OnlyTopDown = true;
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RegionPolicy.OnlyBottomUp = false;
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GCNSchedStrategy::initialize(DAG);
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}
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SUnit *AMDGPUCoExecSchedStrategy::pickNode(bool &IsTopNode) {
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assert(RegionPolicy.OnlyTopDown && !RegionPolicy.OnlyBottomUp &&
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"coexec scheduler only supports top-down scheduling");
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if (DAG->top() == DAG->bottom()) {
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assert(Top.Available.empty() && Top.Pending.empty() &&
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Bot.Available.empty() && Bot.Pending.empty() && "ReadyQ garbage");
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return nullptr;
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}
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bool PickedPending = false;
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SUnit *SU = nullptr;
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do {
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PickedPending = false;
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SU = pickOnlyChoice(Top);
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if (!SU) {
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CandPolicy NoPolicy;
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TopCand.reset(NoPolicy);
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pickNodeFromQueue(Top, NoPolicy, DAG->getTopRPTracker(), TopCand,
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PickedPending, /*IsBottomUp=*/false);
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assert(TopCand.Reason != NoCand && "failed to find a candidate");
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SU = TopCand.SU;
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}
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IsTopNode = true;
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} while (SU->isScheduled);
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if (PickedPending) {
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unsigned ReadyCycle = SU->TopReadyCycle;
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unsigned CurrentCycle = Top.getCurrCycle();
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if (ReadyCycle > CurrentCycle)
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Top.bumpCycle(ReadyCycle);
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// checkHazard() does not expose the exact cycle where the hazard clears.
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while (Top.checkHazard(SU))
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Top.bumpCycle(Top.getCurrCycle() + 1);
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Top.releasePending();
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}
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if (SU->isTopReady())
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Top.removeReady(SU);
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if (SU->isBottomReady())
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Bot.removeReady(SU);
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LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
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<< *SU->getInstr());
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assert(IsTopNode && "coexec scheduler must only schedule from top boundary");
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return SU;
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}
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void AMDGPUCoExecSchedStrategy::pickNodeFromQueue(
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SchedBoundary &Zone, const CandPolicy &ZonePolicy,
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const RegPressureTracker &RPTracker, SchedCandidate &Cand,
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bool &PickedPending, bool IsBottomUp) {
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assert(Zone.isTop() && "coexec scheduler only supports top boundary");
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assert(!IsBottomUp && "coexec scheduler only supports top-down scheduling");
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const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(TRI);
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ArrayRef<unsigned> Pressure = RPTracker.getRegSetPressureAtPos();
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unsigned SGPRPressure = 0;
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unsigned VGPRPressure = 0;
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PickedPending = false;
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if (DAG->isTrackingPressure()) {
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if (!useGCNTrackers()) {
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SGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
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VGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
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} else {
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SGPRPressure = DownwardTracker.getPressure().getSGPRNum();
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VGPRPressure = DownwardTracker.getPressure().getArchVGPRNum();
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}
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}
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auto EvaluateQueue = [&](ReadyQueue &Q, bool FromPending) {
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for (SUnit *SU : Q) {
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SchedCandidate TryCand(ZonePolicy);
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initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, SGPRPressure,
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VGPRPressure, IsBottomUp);
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SchedBoundary *ZoneArg = Cand.AtTop == TryCand.AtTop ? &Zone : nullptr;
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tryCandidate(Cand, TryCand, ZoneArg);
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if (TryCand.Reason != NoCand) {
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if (TryCand.ResDelta == SchedResourceDelta())
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TryCand.initResourceDelta(Zone.DAG, SchedModel);
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LLVM_DEBUG(printCandidateDecision(Cand, TryCand));
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PickedPending = FromPending;
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Cand.setBest(TryCand);
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} else {
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printCandidateDecision(TryCand, Cand);
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}
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}
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};
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LLVM_DEBUG(dbgs() << "Available Q:\n");
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EvaluateQueue(Zone.Available, /*FromPending=*/false);
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LLVM_DEBUG(dbgs() << "Pending Q:\n");
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EvaluateQueue(Zone.Pending, /*FromPending=*/true);
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}
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bool AMDGPUCoExecSchedStrategy::tryCandidate(SchedCandidate &Cand,
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SchedCandidate &TryCand,
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SchedBoundary *Zone) const {
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// Initialize the candidate if needed.
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if (!Cand.isValid()) {
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TryCand.Reason = FirstValid;
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return true;
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}
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// Bias PhysReg Defs and copies to their uses and defined respectively.
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if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop),
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biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg))
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return TryCand.Reason != NoCand;
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// Avoid exceeding the target's limit.
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if (DAG->isTrackingPressure() &&
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tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand,
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RegExcess, TRI, DAG->MF))
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return TryCand.Reason != NoCand;
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// We only compare a subset of features when comparing nodes between
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// Top and Bottom boundary. Some properties are simply incomparable, in many
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// other instances we should only override the other boundary if something
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// is a clear good pick on one boundary. Skip heuristics that are more
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// "tie-breaking" in nature.
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bool SameBoundary = Zone != nullptr;
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if (SameBoundary) {
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// For loops that are acyclic path limited, aggressively schedule for
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// latency. Within an single cycle, whenever CurrMOps > 0, allow normal
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// heuristics to take precedence.
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if (Rem.IsAcyclicLatencyLimited && !Zone->getCurrMOps() &&
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tryLatency(TryCand, Cand, *Zone))
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return TryCand.Reason != NoCand;
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// Prioritize instructions that read unbuffered resources by stall cycles.
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if (tryLess(Zone->getLatencyStallCycles(TryCand.SU),
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Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall))
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return TryCand.Reason != NoCand;
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}
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// Keep clustered nodes together to encourage downstream peephole
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// optimizations which may reduce resource requirements.
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//
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// This is a best effort to set things up for a post-RA pass. Optimizations
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// like generating loads of multiple registers should ideally be done within
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// the scheduler pass by combining the loads during DAG postprocessing.
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unsigned CandZoneCluster = Cand.AtTop ? TopClusterID : BotClusterID;
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unsigned TryCandZoneCluster = TryCand.AtTop ? TopClusterID : BotClusterID;
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bool CandIsClusterSucc =
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isTheSameCluster(CandZoneCluster, Cand.SU->ParentClusterIdx);
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bool TryCandIsClusterSucc =
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isTheSameCluster(TryCandZoneCluster, TryCand.SU->ParentClusterIdx);
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if (tryGreater(TryCandIsClusterSucc, CandIsClusterSucc, TryCand, Cand,
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Cluster))
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return TryCand.Reason != NoCand;
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if (SameBoundary) {
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// Weak edges are for clustering and other constraints.
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if (tryLess(getWeakLeft(TryCand.SU, TryCand.AtTop),
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getWeakLeft(Cand.SU, Cand.AtTop), TryCand, Cand, Weak))
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return TryCand.Reason != NoCand;
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}
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// Avoid increasing the max pressure of the entire region.
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if (DAG->isTrackingPressure() &&
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tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax, TryCand,
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Cand, RegMax, TRI, DAG->MF))
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return TryCand.Reason != NoCand;
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if (SameBoundary) {
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// Avoid critical resource consumption and balance the schedule.
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TryCand.initResourceDelta(DAG, SchedModel);
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if (tryLess(TryCand.ResDelta.CritResources, Cand.ResDelta.CritResources,
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TryCand, Cand, ResourceReduce))
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return TryCand.Reason != NoCand;
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if (tryGreater(TryCand.ResDelta.DemandedResources,
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Cand.ResDelta.DemandedResources, TryCand, Cand,
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ResourceDemand))
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return TryCand.Reason != NoCand;
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// Avoid serializing long latency dependence chains.
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// For acyclic path limited loops, latency was already checked above.
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if (!RegionPolicy.DisableLatencyHeuristic && TryCand.Policy.ReduceLatency &&
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!Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, *Zone))
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return TryCand.Reason != NoCand;
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// Fall through to original instruction order.
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if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) ||
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(!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) {
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TryCand.Reason = NodeOrder;
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return true;
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}
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}
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return false;
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}
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ScheduleDAGInstrs *
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llvm::createGCNCoExecMachineScheduler(MachineSchedContext *C) {
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LLVM_DEBUG(dbgs() << "AMDGPU coexec preRA scheduler selected for "
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<< C->MF->getName() << '\n');
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return new GCNScheduleDAGMILive(
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C, std::make_unique<AMDGPUCoExecSchedStrategy>(C));
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}
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ScheduleDAGInstrs *
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llvm::createGCNNoopPostMachineScheduler(MachineSchedContext *C) {
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LLVM_DEBUG(dbgs() << "AMDGPU nop postRA scheduler selected for "
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<< C->MF->getName() << '\n');
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return new GCNNoopPostScheduleDAG(C);
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}
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46
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
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46
llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.h
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@ -0,0 +1,46 @@
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//===- AMDGPUCoExecSchedStrategy.h - CoExec Scheduling Strategy -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Coexecution-focused scheduling strategy for AMDGPU.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUCOEXECSCHEDSTRATEGY_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUCOEXECSCHEDSTRATEGY_H
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#include "GCNSchedStrategy.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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class AMDGPUCoExecSchedStrategy final : public GCNSchedStrategy {
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protected:
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bool tryCandidate(SchedCandidate &Cand, SchedCandidate &TryCand,
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SchedBoundary *Zone) const override;
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void pickNodeFromQueue(SchedBoundary &Zone, const CandPolicy &ZonePolicy,
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const RegPressureTracker &RPTracker,
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SchedCandidate &Cand, bool &PickedPending,
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bool IsBottomUp);
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public:
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AMDGPUCoExecSchedStrategy(const MachineSchedContext *C);
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void initPolicy(MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) override;
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void initialize(ScheduleDAGMI *DAG) override;
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SUnit *pickNode(bool &IsTopNode) override;
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};
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ScheduleDAGInstrs *createGCNCoExecMachineScheduler(MachineSchedContext *C);
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ScheduleDAGInstrs *createGCNNoopPostMachineScheduler(MachineSchedContext *C);
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} // End namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUCOEXECSCHEDSTRATEGY_H
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@ -18,6 +18,7 @@
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#include "AMDGPU.h"
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#include "AMDGPUAliasAnalysis.h"
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#include "AMDGPUBarrierLatency.h"
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#include "AMDGPUCoExecSchedStrategy.h"
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#include "AMDGPUCtorDtorLowering.h"
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#include "AMDGPUExportClustering.h"
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#include "AMDGPUExportKernelRuntimeHandles.h"
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@ -89,6 +90,7 @@
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#include "llvm/CodeGen/PostRAHazardRecognizer.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/IntrinsicsAMDGPU.h"
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#include "llvm/IR/PassManager.h"
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#include "llvm/IR/PatternMatch.h"
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@ -574,6 +576,38 @@ static cl::opt<std::string>
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cl::desc("Select custom AMDGPU scheduling strategy."),
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cl::Hidden, cl::init(""));
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// Scheduler selection is consulted both when creating the scheduler and from
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// overrideSchedPolicy(), so keep the attribute and global command line handling
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// in one helper.
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StringRef llvm::AMDGPU::getSchedStrategy(const Function &F) {
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Attribute SchedStrategyAttr = F.getFnAttribute("amdgpu-sched-strategy");
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if (SchedStrategyAttr.isValid())
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return SchedStrategyAttr.getValueAsString();
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if (!AMDGPUSchedStrategy.empty())
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return AMDGPUSchedStrategy;
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return "";
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}
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static void
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diagnoseUnsupportedCoExecSchedulerSelection(const Function &F,
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const GCNSubtarget &ST) {
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if (ST.hasGFX1250Insts())
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return;
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F.getContext().diagnose(DiagnosticInfoUnsupported(
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F, "'amdgpu-sched-strategy'='coexec' is only supported for gfx1250",
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DiagnosticLocation(), DS_Warning));
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}
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static bool useNoopPostScheduler(const Function &F) {
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Attribute PostSchedStrategyAttr =
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F.getFnAttribute("amdgpu-post-sched-strategy");
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return PostSchedStrategyAttr.isValid() &&
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PostSchedStrategyAttr.getValueAsString() == "nop";
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}
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static cl::opt<bool> EnableRewritePartialRegUses(
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"amdgpu-enable-rewrite-partial-reg-uses",
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cl::desc("Enable rewrite partial reg uses pass"), cl::init(true),
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@ -1244,11 +1278,7 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
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if (ST.enableSIScheduler())
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return createSIMachineScheduler(C);
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Attribute SchedStrategyAttr =
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C->MF->getFunction().getFnAttribute("amdgpu-sched-strategy");
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StringRef SchedStrategy = SchedStrategyAttr.isValid()
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? SchedStrategyAttr.getValueAsString()
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: AMDGPUSchedStrategy;
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StringRef SchedStrategy = AMDGPU::getSchedStrategy(C->MF->getFunction());
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if (SchedStrategy == "max-ilp")
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return createGCNMaxILPMachineScheduler(C);
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@ -1265,11 +1295,19 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
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if (SchedStrategy == "iterative-maxocc")
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return createIterativeGCNMaxOccupancyMachineScheduler(C);
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if (SchedStrategy == "coexec") {
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diagnoseUnsupportedCoExecSchedulerSelection(C->MF->getFunction(), ST);
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return createGCNCoExecMachineScheduler(C);
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}
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return createGCNMaxOccupancyMachineScheduler(C);
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}
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ScheduleDAGInstrs *
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GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
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if (useNoopPostScheduler(C->MF->getFunction()))
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return createGCNNoopPostMachineScheduler(C);
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ScheduleDAGMI *DAG =
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new GCNPostScheduleDAGMILive(C, std::make_unique<PostGenericScheduler>(C),
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/*RemoveKillFlags=*/true);
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@ -27,6 +27,10 @@ namespace llvm {
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// AMDGPU Target Machine (R600+)
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//===----------------------------------------------------------------------===//
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namespace AMDGPU {
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StringRef getSchedStrategy(const Function &F);
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}
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class AMDGPUTargetMachine : public CodeGenTargetMachineImpl {
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protected:
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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@ -86,6 +86,7 @@ add_llvm_target(AMDGPUCodeGen
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||||
AMDGPUMacroFusion.cpp
|
||||
AMDGPUMCInstLower.cpp
|
||||
AMDGPUMemoryUtils.cpp
|
||||
AMDGPUCoExecSchedStrategy.cpp
|
||||
AMDGPUIGroupLP.cpp
|
||||
AMDGPULowerVGPREncoding.cpp
|
||||
AMDGPUMCResourceInfo.cpp
|
||||
|
||||
@ -108,6 +108,8 @@ const unsigned ScheduleMetrics::ScaleFactor = 100;
|
||||
GCNSchedStrategy::GCNSchedStrategy(const MachineSchedContext *C)
|
||||
: GenericScheduler(C), TargetOccupancy(0), MF(nullptr),
|
||||
DownwardTracker(*C->LIS), UpwardTracker(*C->LIS), HasHighPressure(false) {
|
||||
if (GCNTrackers.getNumOccurrences() > 0)
|
||||
GCNTrackersOverride = GCNTrackers;
|
||||
}
|
||||
|
||||
void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) {
|
||||
@ -196,7 +198,7 @@ static bool canUsePressureDiffs(const SUnit &SU) {
|
||||
return true;
|
||||
}
|
||||
|
||||
static void getRegisterPressures(
|
||||
void GCNSchedStrategy::getRegisterPressures(
|
||||
bool AtTop, const RegPressureTracker &RPTracker, SUnit *SU,
|
||||
std::vector<unsigned> &Pressure, std::vector<unsigned> &MaxPressure,
|
||||
GCNDownwardRPTracker &DownwardTracker, GCNUpwardRPTracker &UpwardTracker,
|
||||
@ -204,7 +206,7 @@ static void getRegisterPressures(
|
||||
// getDownwardPressure() and getUpwardPressure() make temporary changes to
|
||||
// the tracker, so we need to pass those function a non-const copy.
|
||||
RegPressureTracker &TempTracker = const_cast<RegPressureTracker &>(RPTracker);
|
||||
if (!GCNTrackers) {
|
||||
if (!useGCNTrackers()) {
|
||||
AtTop
|
||||
? TempTracker.getDownwardPressure(SU->getInstr(), Pressure, MaxPressure)
|
||||
: TempTracker.getUpwardPressure(SU->getInstr(), Pressure, MaxPressure);
|
||||
@ -256,7 +258,7 @@ void GCNSchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU,
|
||||
//
|
||||
// In EXPENSIVE_CHECKS, we always query RPTracker to verify the results of
|
||||
// PressureDiffs.
|
||||
if (AtTop || !canUsePressureDiffs(*SU) || GCNTrackers) {
|
||||
if (AtTop || !canUsePressureDiffs(*SU) || useGCNTrackers()) {
|
||||
getRegisterPressures(AtTop, RPTracker, SU, Pressure, MaxPressure,
|
||||
DownwardTracker, UpwardTracker, DAG, SRI);
|
||||
} else {
|
||||
@ -400,7 +402,7 @@ void GCNSchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
|
||||
unsigned VGPRPressure = 0;
|
||||
IsPending = false;
|
||||
if (DAG->isTrackingPressure()) {
|
||||
if (!GCNTrackers) {
|
||||
if (!useGCNTrackers()) {
|
||||
SGPRPressure = Pressure[AMDGPU::RegisterPressureSets::SReg_32];
|
||||
VGPRPressure = Pressure[AMDGPU::RegisterPressureSets::VGPR_32];
|
||||
} else {
|
||||
@ -623,7 +625,7 @@ SUnit *GCNSchedStrategy::pickNode(bool &IsTopNode) {
|
||||
}
|
||||
|
||||
void GCNSchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
|
||||
if (GCNTrackers) {
|
||||
if (useGCNTrackers()) {
|
||||
MachineInstr *MI = SU->getInstr();
|
||||
IsTopNode ? (void)DownwardTracker.advance(MI, false)
|
||||
: UpwardTracker.recede(*MI);
|
||||
@ -707,7 +709,8 @@ GCNMaxOccupancySchedStrategy::GCNMaxOccupancySchedStrategy(
|
||||
SchedStages.push_back(GCNSchedStageID::UnclusteredHighRPReschedule);
|
||||
SchedStages.push_back(GCNSchedStageID::ClusteredLowOccupancyReschedule);
|
||||
SchedStages.push_back(GCNSchedStageID::PreRARematerialize);
|
||||
GCNTrackers = GCNTrackers & !IsLegacyScheduler;
|
||||
if (IsLegacyScheduler)
|
||||
GCNTrackersOverride = std::nullopt;
|
||||
}
|
||||
|
||||
GCNMaxILPSchedStrategy::GCNMaxILPSchedStrategy(const MachineSchedContext *C)
|
||||
@ -1136,9 +1139,10 @@ void GCNScheduleDAGMILive::finalizeSchedule() {
|
||||
void GCNScheduleDAGMILive::runSchedStages() {
|
||||
LLVM_DEBUG(dbgs() << "All regions recorded, starting actual scheduling.\n");
|
||||
|
||||
GCNSchedStrategy &S = static_cast<GCNSchedStrategy &>(*SchedImpl);
|
||||
if (!Regions.empty()) {
|
||||
BBLiveInMap = getRegionLiveInMap();
|
||||
if (GCNTrackers)
|
||||
if (S.useGCNTrackers())
|
||||
RegionLiveOuts.buildLiveRegMap();
|
||||
}
|
||||
|
||||
@ -1150,7 +1154,6 @@ void GCNScheduleDAGMILive::runSchedStages() {
|
||||
}
|
||||
#endif
|
||||
|
||||
GCNSchedStrategy &S = static_cast<GCNSchedStrategy &>(*SchedImpl);
|
||||
while (S.advanceStage()) {
|
||||
auto Stage = createSchedStage(S.getCurrentStage());
|
||||
if (!Stage->initGCNSchedStage())
|
||||
@ -1166,7 +1169,7 @@ void GCNScheduleDAGMILive::runSchedStages() {
|
||||
continue;
|
||||
}
|
||||
|
||||
if (GCNTrackers) {
|
||||
if (S.useGCNTrackers()) {
|
||||
GCNDownwardRPTracker *DownwardTracker = S.getDownwardTracker();
|
||||
GCNUpwardRPTracker *UpwardTracker = S.getUpwardTracker();
|
||||
GCNRPTracker::LiveRegSet *RegionLiveIns =
|
||||
|
||||
@ -74,6 +74,13 @@ protected:
|
||||
void printCandidateDecision(const SchedCandidate &Current,
|
||||
const SchedCandidate &Preferred);
|
||||
|
||||
void getRegisterPressures(bool AtTop, const RegPressureTracker &RPTracker,
|
||||
SUnit *SU, std::vector<unsigned> &Pressure,
|
||||
std::vector<unsigned> &MaxPressure,
|
||||
GCNDownwardRPTracker &DownwardTracker,
|
||||
GCNUpwardRPTracker &UpwardTracker,
|
||||
ScheduleDAGMI *DAG, const SIRegisterInfo *SRI);
|
||||
|
||||
std::vector<unsigned> Pressure;
|
||||
|
||||
std::vector<unsigned> MaxPressure;
|
||||
@ -98,6 +105,10 @@ protected:
|
||||
// GCN RP Tracker for botttom-up scheduling
|
||||
mutable GCNUpwardRPTracker UpwardTracker;
|
||||
|
||||
bool UseGCNTrackers = false;
|
||||
|
||||
std::optional<bool> GCNTrackersOverride;
|
||||
|
||||
public:
|
||||
// schedule() have seen register pressure over the critical limits and had to
|
||||
// track register pressure for actual scheduling heuristics.
|
||||
@ -145,6 +156,10 @@ public:
|
||||
|
||||
bool hasNextStage() const;
|
||||
|
||||
bool useGCNTrackers() const {
|
||||
return GCNTrackersOverride.value_or(UseGCNTrackers);
|
||||
}
|
||||
|
||||
GCNSchedStageID getNextStage() const;
|
||||
|
||||
GCNDownwardRPTracker *getDownwardTracker() { return &DownwardTracker; }
|
||||
|
||||
@ -338,6 +338,13 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
|
||||
// SIRegisterInfo::getRegPressureSetLimit()
|
||||
Policy.ShouldTrackPressure = true;
|
||||
|
||||
const Function &F = Region.RegionBegin->getMF()->getFunction();
|
||||
if (AMDGPU::getSchedStrategy(F) == "coexec") {
|
||||
Policy.OnlyTopDown = true;
|
||||
Policy.OnlyBottomUp = false;
|
||||
return;
|
||||
}
|
||||
|
||||
// Enabling both top down and bottom up scheduling seems to give us less
|
||||
// register spills than just using one of these approaches on its own.
|
||||
Policy.OnlyTopDown = false;
|
||||
|
||||
124
llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
Normal file
124
llvm/test/CodeGen/AMDGPU/coexec-sched-effective-stall.mir
Normal file
@ -0,0 +1,124 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -verify-misched %s -o - | FileCheck -check-prefix=DEFAULT %s
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -verify-misched %s -o - | FileCheck -check-prefix=COEXEC %s
|
||||
|
||||
--- |
|
||||
; Pre-commit test for stall heuristic
|
||||
|
||||
define void @test-sched-effective-stall() #0 { ret void }
|
||||
define void @test-sched-pending-structural-stall() #0 { ret void }
|
||||
|
||||
attributes #0 = { "amdgpu-waves-per-eu"="1,1" }
|
||||
...
|
||||
|
||||
name: test-sched-effective-stall
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
; DEFAULT-LABEL: name: test-sched-effective-stall
|
||||
; DEFAULT: [[DEF:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF4:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF5:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: early-clobber %13:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF]], [[DEF1]], 0, [[DEF2]], [[DEF3]], [[DEF4]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; DEFAULT-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF5]], 0, 0, implicit $exec
|
||||
; DEFAULT-NEXT: [[DEF6:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF7:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF8:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF9:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF10:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[GLOBAL_LOAD_DWORDX2_]], 8, [[GLOBAL_LOAD_DWORDX2_]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
|
||||
; DEFAULT-NEXT: early-clobber %14:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF6]], [[DEF7]], 0, [[DEF8]], [[DEF9]], [[DEF10]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; DEFAULT-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F32_]], implicit %13, implicit %14
|
||||
;
|
||||
; COEXEC-LABEL: name: test-sched-effective-stall
|
||||
; COEXEC: [[DEF:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF1:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF2:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF3:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF4:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF5:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF6:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF7:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF8:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF9:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF10:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[GLOBAL_LOAD_DWORDX2_:%[0-9]+]]:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 [[DEF10]], 0, 0, implicit $exec
|
||||
; COEXEC-NEXT: early-clobber %13:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF]], [[DEF1]], 0, [[DEF2]], [[DEF3]], [[DEF4]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; COEXEC-NEXT: early-clobber %14:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF5]], [[DEF6]], 0, [[DEF7]], [[DEF8]], [[DEF9]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; COEXEC-NEXT: [[V_PK_ADD_F32_:%[0-9]+]]:vreg_64_align2 = V_PK_ADD_F32 8, [[GLOBAL_LOAD_DWORDX2_]], 8, [[GLOBAL_LOAD_DWORDX2_]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
|
||||
; COEXEC-NEXT: S_ENDPGM 0, implicit [[V_PK_ADD_F32_]], implicit %13, implicit %14
|
||||
%0:vreg_512_align2 = IMPLICIT_DEF
|
||||
%1:vreg_512_align2 = IMPLICIT_DEF
|
||||
%2:vreg_256_align2 = IMPLICIT_DEF
|
||||
%3:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%4:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%5:vreg_512_align2 = IMPLICIT_DEF
|
||||
%6:vreg_512_align2 = IMPLICIT_DEF
|
||||
%7:vreg_256_align2 = IMPLICIT_DEF
|
||||
%8:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%9:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%10:vreg_64_align2 = IMPLICIT_DEF
|
||||
%11:vreg_64_align2 = GLOBAL_LOAD_DWORDX2 %10, 0, 0, implicit $exec
|
||||
%12:vreg_64_align2 = V_PK_ADD_F32 8, %11, 8, %11, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
|
||||
%13:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr %0, %1, 0, %2, %3, %4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%14:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr %5, %6, 0, %7, %8, %9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
S_ENDPGM 0, implicit %12, implicit %13, implicit %14
|
||||
...
|
||||
|
||||
---
|
||||
name: test-sched-pending-structural-stall
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
; DEFAULT-LABEL: name: test-sched-pending-structural-stall
|
||||
; DEFAULT: [[DEF:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF1:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF2:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF3:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF4:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: early-clobber %10:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF]], [[DEF1]], 0, [[DEF2]], [[DEF3]], [[DEF4]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; DEFAULT-NEXT: [[DEF5:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF6:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF7:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF8:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: [[DEF9:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; DEFAULT-NEXT: S_NOP 0
|
||||
; DEFAULT-NEXT: S_NOP 0
|
||||
; DEFAULT-NEXT: early-clobber %11:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF5]], [[DEF6]], 0, [[DEF7]], [[DEF8]], [[DEF9]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; DEFAULT-NEXT: S_ENDPGM 0, implicit %10, implicit %11
|
||||
;
|
||||
; COEXEC-LABEL: name: test-sched-pending-structural-stall
|
||||
; COEXEC: [[DEF:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF1:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF2:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF3:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF4:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF5:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF6:%[0-9]+]]:vreg_512_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF7:%[0-9]+]]:vreg_256_align2 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF8:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: [[DEF9:%[0-9]+]]:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
; COEXEC-NEXT: early-clobber %10:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF]], [[DEF1]], 0, [[DEF2]], [[DEF3]], [[DEF4]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; COEXEC-NEXT: early-clobber %11:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr [[DEF5]], [[DEF6]], 0, [[DEF7]], [[DEF8]], [[DEF9]], 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
; COEXEC-NEXT: S_NOP 0
|
||||
; COEXEC-NEXT: S_NOP 0
|
||||
; COEXEC-NEXT: S_ENDPGM 0, implicit %10, implicit %11
|
||||
%0:vreg_512_align2 = IMPLICIT_DEF
|
||||
%1:vreg_512_align2 = IMPLICIT_DEF
|
||||
%2:vreg_256_align2 = IMPLICIT_DEF
|
||||
%3:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%4:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%5:vreg_512_align2 = IMPLICIT_DEF
|
||||
%6:vreg_512_align2 = IMPLICIT_DEF
|
||||
%7:vreg_256_align2 = IMPLICIT_DEF
|
||||
%8:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%9:vgpr_32_lo256 = IMPLICIT_DEF
|
||||
%10:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr %0, %1, 0, %2, %3, %4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%11:vreg_256_align2 = V_WMMA_SCALE_F32_16X16X128_F8F6F4_f8_f8_w32_threeaddr %5, %6, 0, %7, %8, %9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
S_NOP 0
|
||||
S_NOP 0
|
||||
S_ENDPGM 0, implicit %10, implicit %11
|
||||
...
|
||||
20
llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
Normal file
20
llvm/test/CodeGen/AMDGPU/coexec-sched-warning.mir
Normal file
@ -0,0 +1,20 @@
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=GFX1100
|
||||
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec %s -o /dev/null 2>&1 | FileCheck --allow-empty %s --check-prefix=GFX1250
|
||||
|
||||
# GFX1100: warning: {{.*}}'amdgpu-sched-strategy'='coexec' is only supported for gfx1250
|
||||
# GFX1250-NOT: warning:
|
||||
|
||||
--- |
|
||||
define void @coexec_sched_warning() #0 { ret void }
|
||||
|
||||
attributes #0 = { "amdgpu-waves-per-eu"="1,1" }
|
||||
...
|
||||
|
||||
---
|
||||
name: coexec_sched_warning
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
%0:vgpr_32 = IMPLICIT_DEF
|
||||
S_ENDPGM 0, implicit %0
|
||||
...
|
||||
Loading…
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Reference in New Issue
Block a user