AMDGPU: Split and convert some rcp and rsq tests to generated checks
This commit is contained in:
Matt Arsenault
parent
296e24cd2e
commit
467df9c591
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Load Diff
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Load Diff
985
llvm/test/CodeGen/AMDGPU/rsq.f32.ll
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985
llvm/test/CodeGen/AMDGPU/rsq.f32.ll
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@ -0,0 +1,985 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-UNSAFE,SI-DAZ-UNSAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-UNSAFE,SI-IEEE-UNSAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-SAFE,SI-DAZ-SAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-SAFE,SI-IEEE-SAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=hawaii -denormal-fp-math-f32=preserve-sign -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-UNSAFE,CI-DAZ-UNSAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=hawaii -denormal-fp-math-f32=ieee -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-UNSAFE,CI-IEEE-UNSAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=hawaii -denormal-fp-math-f32=preserve-sign < %s | FileCheck -check-prefixes=GCN-DAZ,GCN-DAZ-SAFE,CI-DAZ-SAFE %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=hawaii -denormal-fp-math-f32=ieee < %s | FileCheck -check-prefixes=GCN-IEEE,GCN-IEEE-SAFE,CI-IEEE-SAFE %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare float @llvm.sqrt.f32(float) nounwind readnone
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declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) nounwind readnone
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define amdgpu_kernel void @rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {
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; GCN-DAZ-LABEL: rsq_f32:
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; GCN-DAZ: ; %bb.0:
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; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf000
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; GCN-DAZ-NEXT: s_mov_b32 s6, -1
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; GCN-DAZ-NEXT: s_mov_b32 s10, s6
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; GCN-DAZ-NEXT: s_mov_b32 s11, s7
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; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-DAZ-NEXT: s_mov_b32 s8, s2
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; GCN-DAZ-NEXT: s_mov_b32 s9, s3
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; GCN-DAZ-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; GCN-DAZ-NEXT: s_mov_b32 s4, s0
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; GCN-DAZ-NEXT: s_mov_b32 s5, s1
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; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)
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; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0
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; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-DAZ-NEXT: s_endpgm
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;
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; GCN-IEEE-UNSAFE-LABEL: rsq_f32:
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; GCN-IEEE-UNSAFE: ; %bb.0:
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; GCN-IEEE-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s6, -1
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s10, s6
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s11, s7
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s8, s2
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s9, s3
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; GCN-IEEE-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s4, s0
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s5, s1
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: v_rsq_f32_e32 v0, v0
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; GCN-IEEE-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-IEEE-UNSAFE-NEXT: s_endpgm
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;
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; GCN-IEEE-SAFE-LABEL: rsq_f32:
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; GCN-IEEE-SAFE: ; %bb.0:
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; GCN-IEEE-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s6, -1
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s10, s6
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s11, s7
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; GCN-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s8, s2
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s9, s3
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; GCN-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x6f800000
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; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x2f800000
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, s0
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s5, s1
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; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
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; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s2
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; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
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; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1
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; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
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; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
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; GCN-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-IEEE-SAFE-NEXT: s_endpgm
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; GCN-UNSAFE-LABEL: rsq_f32:
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; GCN-UNSAFE: ; %bb.0:
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; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
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; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1
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; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6
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; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7
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; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2
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; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3
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; GCN-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0
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; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1
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; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-UNSAFE-NEXT: v_rsq_f32_e32 v0, v0
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; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GCN-UNSAFE-NEXT: s_endpgm
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%val = load float, ptr addrspace(1) %in, align 4
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%sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
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%div = fdiv float 1.0, %sqrt, !fpmath !0
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store float %div, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @rsq_f32_sgpr(ptr addrspace(1) noalias %out, float %val) {
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; GCN-DAZ-LABEL: rsq_f32_sgpr:
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; GCN-DAZ: ; %bb.0:
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; GCN-DAZ-NEXT: s_load_dword s2, s[0:1], 0xb
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; GCN-DAZ-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-DAZ-NEXT: s_mov_b32 s3, 0xf000
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; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, s2
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; GCN-DAZ-NEXT: s_mov_b32 s2, -1
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; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-DAZ-NEXT: s_endpgm
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;
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; GCN-IEEE-UNSAFE-LABEL: rsq_f32_sgpr:
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; GCN-IEEE-UNSAFE: ; %bb.0:
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; GCN-IEEE-UNSAFE-NEXT: s_load_dword s2, s[0:1], 0xb
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; GCN-IEEE-UNSAFE-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s3, 0xf000
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: v_rsq_f32_e32 v0, s2
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s2, -1
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; GCN-IEEE-UNSAFE-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-IEEE-UNSAFE-NEXT: s_endpgm
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;
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; GCN-IEEE-SAFE-LABEL: rsq_f32_sgpr:
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; GCN-IEEE-SAFE: ; %bb.0:
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; GCN-IEEE-SAFE-NEXT: s_load_dword s2, s[0:1], 0xb
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; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x2f800000
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; GCN-IEEE-SAFE-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s3, 0xf000
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; GCN-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, s2
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x6f800000
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; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s2
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; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
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; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1
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; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
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; GCN-IEEE-SAFE-NEXT: s_mov_b32 s2, -1
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; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
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; GCN-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-IEEE-SAFE-NEXT: s_endpgm
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; GCN-UNSAFE-LABEL: rsq_f32_sgpr:
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; GCN-UNSAFE: ; %bb.0:
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; GCN-UNSAFE-NEXT: s_load_dword s2, s[0:1], 0xb
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; GCN-UNSAFE-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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; GCN-UNSAFE-NEXT: s_mov_b32 s3, 0xf000
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; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-UNSAFE-NEXT: v_rsq_f32_e32 v0, s2
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; GCN-UNSAFE-NEXT: s_mov_b32 s2, -1
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; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-UNSAFE-NEXT: s_endpgm
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%sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
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%div = fdiv float 1.0, %sqrt, !fpmath !0
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store float %div, ptr addrspace(1) %out, align 4
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ret void
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}
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; Recognize that this is rsqrt(a) * rcp(b) * c,
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; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
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; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare.
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define amdgpu_kernel void @rsqrt_fmul(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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; GCN-UNSAFE-LABEL: rsqrt_fmul:
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; GCN-UNSAFE: ; %bb.0:
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; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
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; GCN-UNSAFE-NEXT: s_mov_b32 s6, 0
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; GCN-UNSAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-UNSAFE-NEXT: v_mov_b32_e32 v1, 0
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; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-UNSAFE-NEXT: s_mov_b64 s[8:9], s[2:3]
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; GCN-UNSAFE-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-UNSAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
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; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-UNSAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
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; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-UNSAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
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; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-UNSAFE-NEXT: s_mov_b64 s[4:5], s[0:1]
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; GCN-UNSAFE-NEXT: v_sqrt_f32_e32 v2, v2
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; GCN-UNSAFE-NEXT: v_mul_f32_e32 v2, v2, v3
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; GCN-UNSAFE-NEXT: v_rcp_f32_e32 v2, v2
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; GCN-UNSAFE-NEXT: v_mul_f32_e32 v2, v4, v2
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; GCN-UNSAFE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; GCN-UNSAFE-NEXT: s_endpgm
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; GCN-DAZ-UNSAFE-LABEL: rsqrt_fmul:
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; GCN-DAZ-UNSAFE: ; %bb.0:
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; GCN-DAZ-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-DAZ-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
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; GCN-DAZ-UNSAFE-NEXT: s_mov_b32 s6, 0
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; GCN-DAZ-UNSAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-DAZ-UNSAFE-NEXT: v_mov_b32_e32 v1, 0
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; GCN-DAZ-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-DAZ-UNSAFE-NEXT: s_mov_b64 s[8:9], s[2:3]
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; GCN-DAZ-UNSAFE-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-DAZ-UNSAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
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; GCN-DAZ-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-DAZ-UNSAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
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; GCN-DAZ-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-DAZ-UNSAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
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; GCN-DAZ-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-DAZ-UNSAFE-NEXT: s_mov_b64 s[4:5], s[0:1]
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; GCN-DAZ-UNSAFE-NEXT: v_sqrt_f32_e32 v2, v2
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; GCN-DAZ-UNSAFE-NEXT: v_mul_f32_e32 v2, v2, v3
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; GCN-DAZ-UNSAFE-NEXT: v_rcp_f32_e32 v2, v2
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; GCN-DAZ-UNSAFE-NEXT: v_mul_f32_e32 v2, v4, v2
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; GCN-DAZ-UNSAFE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; GCN-DAZ-UNSAFE-NEXT: s_endpgm
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;
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; GCN-IEEE-UNSAFE-LABEL: rsqrt_fmul:
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; GCN-IEEE-UNSAFE: ; %bb.0:
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; GCN-IEEE-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s6, 0
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; GCN-IEEE-UNSAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GCN-IEEE-UNSAFE-NEXT: v_mov_b32_e32 v1, 0
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b64 s[8:9], s[2:3]
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-IEEE-UNSAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
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; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0)
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; GCN-IEEE-UNSAFE-NEXT: s_mov_b64 s[4:5], s[0:1]
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; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v2, v2
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; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v2, v2, v3
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; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e32 v2, v2
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; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v2, v4, v2
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; GCN-IEEE-UNSAFE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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; GCN-IEEE-UNSAFE-NEXT: s_endpgm
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;
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; GCN-DAZ-SAFE-LABEL: rsqrt_fmul:
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; GCN-DAZ-SAFE: ; %bb.0:
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; GCN-DAZ-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-DAZ-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-DAZ-SAFE-NEXT: s_mov_b32 s6, 0
|
||||
; GCN-DAZ-SAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GCN-DAZ-SAFE-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GCN-DAZ-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-DAZ-SAFE-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; GCN-DAZ-SAFE-NEXT: s_mov_b64 s[10:11], s[6:7]
|
||||
; GCN-DAZ-SAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
|
||||
; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-DAZ-SAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
|
||||
; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-DAZ-SAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
|
||||
; GCN-DAZ-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-DAZ-SAFE-NEXT: s_mov_b64 s[4:5], s[0:1]
|
||||
; GCN-DAZ-SAFE-NEXT: v_sqrt_f32_e32 v2, v2
|
||||
; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v2, v2, v3
|
||||
; GCN-DAZ-SAFE-NEXT: v_div_scale_f32 v3, s[0:1], v2, v2, v4
|
||||
; GCN-DAZ-SAFE-NEXT: v_rcp_f32_e32 v5, v3
|
||||
; GCN-DAZ-SAFE-NEXT: v_div_scale_f32 v6, vcc, v4, v2, v4
|
||||
; GCN-DAZ-SAFE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
|
||||
; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
|
||||
; GCN-DAZ-SAFE-NEXT: v_fma_f32 v5, v7, v5, v5
|
||||
; GCN-DAZ-SAFE-NEXT: v_mul_f32_e32 v7, v6, v5
|
||||
; GCN-DAZ-SAFE-NEXT: v_fma_f32 v8, -v3, v7, v6
|
||||
; GCN-DAZ-SAFE-NEXT: v_fma_f32 v7, v8, v5, v7
|
||||
; GCN-DAZ-SAFE-NEXT: v_fma_f32 v3, -v3, v7, v6
|
||||
; GCN-DAZ-SAFE-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
|
||||
; GCN-DAZ-SAFE-NEXT: v_div_fmas_f32 v3, v3, v5, v7
|
||||
; GCN-DAZ-SAFE-NEXT: v_div_fixup_f32 v2, v3, v2, v4
|
||||
; GCN-DAZ-SAFE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
|
||||
; GCN-DAZ-SAFE-NEXT: s_endpgm
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: rsqrt_fmul:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s6, 0
|
||||
; GCN-IEEE-SAFE-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b64 s[8:9], s[2:3]
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b64 s[10:11], s[6:7]
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 offset:4 glc
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 offset:8 glc
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b64 s[4:5], s[0:1]
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v2, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v2, v2, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v3, s[2:3], v2, v2, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v5, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v6, vcc, v4, v2, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v7, -v3, v5, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, v7, v5, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v7, v6, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v8, -v3, v7, v6
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v7, v8, v5, v7
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v3, -v3, v7, v6
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fmas_f32 v3, v3, v5, v7
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fixup_f32 v2, v3, v2, v4
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
|
||||
; GCN-IEEE-SAFE-NEXT: s_endpgm
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
||||
%gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
|
||||
%gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
|
||||
%gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
|
||||
|
||||
%a = load volatile float, ptr addrspace(1) %gep.0
|
||||
%b = load volatile float, ptr addrspace(1) %gep.1
|
||||
%c = load volatile float, ptr addrspace(1) %gep.2
|
||||
|
||||
%x = call float @llvm.sqrt.f32(float %a)
|
||||
%y = fmul float %x, %b
|
||||
%z = fdiv float %c, %y
|
||||
store float %z, ptr addrspace(1) %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @neg_rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {
|
||||
; GCN-DAZ-LABEL: neg_rsq_f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-DAZ-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-DAZ-NEXT: s_endpgm
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: neg_rsq_f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-IEEE-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_endpgm
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: neg_rsq_f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s2
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-IEEE-SAFE-NEXT: s_endpgm
|
||||
; GCN-UNSAFE-LABEL: neg_rsq_f32:
|
||||
; GCN-UNSAFE: ; %bb.0:
|
||||
; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-UNSAFE-NEXT: s_endpgm
|
||||
%val = load float, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
store float %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @neg_rsq_neg_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) {
|
||||
; GCN-DAZ-LABEL: neg_rsq_neg_f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-DAZ-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-DAZ-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-DAZ-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-DAZ-NEXT: s_endpgm
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: neg_rsq_neg_f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-IEEE-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_endpgm
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: neg_rsq_neg_f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s2, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s2
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
|
||||
; GCN-IEEE-SAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-IEEE-SAFE-NEXT: s_endpgm
|
||||
; GCN-UNSAFE-LABEL: neg_rsq_neg_f32:
|
||||
; GCN-UNSAFE: ; %bb.0:
|
||||
; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-UNSAFE-NEXT: buffer_load_dword v0, off, s[8:11], 0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-UNSAFE-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; GCN-UNSAFE-NEXT: s_endpgm
|
||||
%val = load float, ptr addrspace(1) %in, align 4
|
||||
%val.fneg = fneg float %val
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val.fneg)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
store float %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define float @v_neg_rsq_neg_f32(float %val) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_neg_f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_neg_f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_neg_f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%val.fneg = fneg float %val
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val.fneg)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
ret float %div
|
||||
}
|
||||
|
||||
define <2 x float> @v_neg_rsq_neg_v2f32(<2 x float> %val) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_neg_v2f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v1, -v1
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_neg_v2f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v1, -v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_neg_v2f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v1, -v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v3, 1.0, v2, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v1, v1, -v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v3, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v2, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%val.fneg = fneg <2 x float> %val
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %val.fneg)
|
||||
%div = fdiv <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
|
||||
ret <2 x float> %div
|
||||
}
|
||||
|
||||
define float @v_neg_rsq_neg_f32_foldable_user(float %val0, float %val1) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_neg_f32_foldable_user:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_mul_f32_e32 v0, v0, v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_neg_f32_foldable_user:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_neg_f32_foldable_user:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v2, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%val0.neg = fneg float %val0
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val0.neg)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
%user = fmul float %div, %val1
|
||||
ret float %user
|
||||
}
|
||||
|
||||
define <2 x float> @v_neg_rsq_neg_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_neg_v2f32_foldable_user:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e64 v1, -v1
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-DAZ-NEXT: v_mul_f32_e32 v0, v0, v2
|
||||
; GCN-DAZ-NEXT: v_mul_f32_e32 v1, v1, v3
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e64 v1, -v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v0, v0, v2
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v1, v1, v3
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_neg_v2f32_foldable_user:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v0, -v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e64 v1, -v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v4, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v1, v1, -v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v5, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v4, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%val0.fneg = fneg <2 x float> %val0
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0.fneg)
|
||||
%div = fdiv <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
|
||||
%user = fmul <2 x float> %div, %val1
|
||||
ret <2 x float> %user
|
||||
}
|
||||
|
||||
define float @v_neg_rsq_f32(float %val) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v1, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v1, v0
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
ret float %div
|
||||
}
|
||||
|
||||
define <2 x float> @v_neg_rsq_v2f32(<2 x float> %val) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_v2f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v1, v1
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_v2f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v1, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_v2f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v3, 1.0, v2, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v1, v1, -v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v3, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v2, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %val)
|
||||
%div = fdiv <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
|
||||
ret <2 x float> %div
|
||||
}
|
||||
|
||||
define float @v_neg_rsq_f32_foldable_user(float %val0, float %val1) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_f32_foldable_user:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_mul_f32_e32 v0, v0, v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_f32_foldable_user:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_f32_foldable_user:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v2, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v2, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val0)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
%user = fmul float %div, %val1
|
||||
ret float %user
|
||||
}
|
||||
|
||||
define <2 x float> @v_neg_rsq_v2f32_foldable_user(<2 x float> %val0, <2 x float> %val1) {
|
||||
; GCN-DAZ-LABEL: v_neg_rsq_v2f32_foldable_user:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_sqrt_f32_e32 v1, v1
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-DAZ-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-DAZ-NEXT: v_mul_f32_e32 v0, v0, v2
|
||||
; GCN-DAZ-NEXT: v_mul_f32_e32 v1, v1, v3
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_neg_rsq_v2f32_foldable_user:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_sqrt_f32_e32 v1, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v0, -v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rcp_f32_e64 v1, -v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v0, v0, v2
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_mul_f32_e32 v1, v1, v3
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_neg_rsq_v2f32_foldable_user:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v1, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_mov_b32 s4, 0x6f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_mov_b32_e32 v4, 0x2f800000
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
|
||||
; GCN-IEEE-SAFE-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v0, v0, -v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e64 v1, v1, -v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v1, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v5, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v4, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v0, v0, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v1, v1, v3
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %val0)
|
||||
%div = fdiv <2 x float> <float -1.0, float -1.0>, %sqrt, !fpmath !0
|
||||
%user = fmul <2 x float> %div, %val1
|
||||
ret <2 x float> %user
|
||||
}
|
||||
|
||||
define float @v_rsq_f32(float %val) {
|
||||
; GCN-DAZ-LABEL: v_rsq_f32:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_rsq_f32:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_rsq_f32:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v2, v1
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v2, v4, v2, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v4, v3, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, -v1, v4, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v4, v5, v2, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v1, -v1, v4, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val), !fpmath !1
|
||||
%div = fdiv float 1.0, %sqrt, !fpmath !1
|
||||
ret float %div
|
||||
}
|
||||
|
||||
; Test that we contract into FMA for an fadd user after introducing
|
||||
; the fmul.
|
||||
define float @v_rsq_f32_contractable_user(float %val0, float %val1) {
|
||||
; GCN-DAZ-LABEL: v_rsq_f32_contractable_user:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_rsq_f32_contractable_user:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_rsq_f32_contractable_user:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v3, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v3, v5, v3, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, v4, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v6, -v2, v5, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, v6, v3, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v2, -v2, v5, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val0), !fpmath !1
|
||||
%div = fdiv contract float 1.0, %sqrt, !fpmath !1
|
||||
%add = fadd contract float %div, %val1
|
||||
ret float %add
|
||||
}
|
||||
|
||||
; Missing contract on the fdiv
|
||||
define float @v_rsq_f32_contractable_user_missing_contract0(float %val0, float %val1) {
|
||||
; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract0:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_rsq_f32_contractable_user_missing_contract0:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_rsq_f32_contractable_user_missing_contract0:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v3, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v3, v5, v3, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, v4, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v6, -v2, v5, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, v6, v3, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v2, -v2, v5, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val0), !fpmath !1
|
||||
%div = fdiv float 1.0, %sqrt, !fpmath !1
|
||||
%add = fadd contract float %div, %val1
|
||||
ret float %add
|
||||
}
|
||||
|
||||
; Missing contract on the fadd
|
||||
define float @v_rsq_f32_contractable_user_missing_contract1(float %val0, float %val1) {
|
||||
; GCN-DAZ-LABEL: v_rsq_f32_contractable_user_missing_contract1:
|
||||
; GCN-DAZ: ; %bb.0:
|
||||
; GCN-DAZ-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-DAZ-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-DAZ-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-DAZ-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-UNSAFE-LABEL: v_rsq_f32_contractable_user_missing_contract1:
|
||||
; GCN-IEEE-UNSAFE: ; %bb.0:
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_rsq_f32_e32 v0, v0
|
||||
; GCN-IEEE-UNSAFE-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-UNSAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; GCN-IEEE-SAFE-LABEL: v_rsq_f32_contractable_user_missing_contract1:
|
||||
; GCN-IEEE-SAFE: ; %bb.0:
|
||||
; GCN-IEEE-SAFE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; GCN-IEEE-SAFE-NEXT: v_sqrt_f32_e32 v0, v0
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_rcp_f32_e32 v3, v2
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v3, v5, v3, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_mul_f32_e32 v5, v4, v3
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v6, -v2, v5, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v5, v6, v3, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_fma_f32 v2, -v2, v5, v4
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
|
||||
; GCN-IEEE-SAFE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
|
||||
; GCN-IEEE-SAFE-NEXT: v_add_f32_e32 v0, v0, v1
|
||||
; GCN-IEEE-SAFE-NEXT: s_setpc_b64 s[30:31]
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val0), !fpmath !1
|
||||
%div = fdiv contract float 1.0, %sqrt, !fpmath !1
|
||||
%add = fadd float %div, %val1
|
||||
ret float %add
|
||||
}
|
||||
|
||||
!0 = !{float 2.500000e+00}
|
||||
!1 = !{float 1.000000e+00}
|
||||
|
||||
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; CI-DAZ-SAFE: {{.*}}
|
||||
; CI-DAZ-UNSAFE: {{.*}}
|
||||
; CI-IEEE-SAFE: {{.*}}
|
||||
; CI-IEEE-UNSAFE: {{.*}}
|
||||
; GCN-IEEE: {{.*}}
|
||||
; SI-DAZ-SAFE: {{.*}}
|
||||
; SI-DAZ-UNSAFE: {{.*}}
|
||||
; SI-IEEE-SAFE: {{.*}}
|
||||
; SI-IEEE-UNSAFE: {{.*}}
|
||||
302
llvm/test/CodeGen/AMDGPU/rsq.f64.ll
Normal file
302
llvm/test/CodeGen/AMDGPU/rsq.f64.ll
Normal file
@ -0,0 +1,302 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GCN,GCN-UNSAFE,SI,SI-UNSAFE %s
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GCN-SAFE,SI,SI-SAFE %s
|
||||
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=hawaii -enable-unsafe-fp-math < %s | FileCheck -check-prefixes=GCN,GCN-UNSAFE,CI,CI-UNSAFE %s
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GCN-SAFE,CI,CI-SAFE %s
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
declare double @llvm.sqrt.f64(double) nounwind readnone
|
||||
|
||||
|
||||
define amdgpu_kernel void @rsq_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
; GCN-UNSAFE-LABEL: rsq_f64:
|
||||
; GCN-UNSAFE: ; %bb.0:
|
||||
; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-UNSAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: v_sqrt_f64_e32 v[0:1], v[0:1]
|
||||
; GCN-UNSAFE-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[0:1], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; GCN-UNSAFE-NEXT: s_endpgm
|
||||
;
|
||||
; SI-SAFE-LABEL: rsq_f64:
|
||||
; SI-SAFE: ; %bb.0:
|
||||
; SI-SAFE-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; SI-SAFE-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SAFE-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SAFE-NEXT: s_mov_b32 s10, s2
|
||||
; SI-SAFE-NEXT: s_mov_b32 s11, s3
|
||||
; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SAFE-NEXT: s_mov_b32 s8, s6
|
||||
; SI-SAFE-NEXT: s_mov_b32 s9, s7
|
||||
; SI-SAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-SAFE-NEXT: v_sqrt_f64_e32 v[0:1], v[0:1]
|
||||
; SI-SAFE-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], 1.0
|
||||
; SI-SAFE-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
|
||||
; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; SI-SAFE-NEXT: v_div_scale_f64 v[6:7], s[0:1], 1.0, v[0:1], 1.0
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
|
||||
; SI-SAFE-NEXT: s_mov_b32 s0, 0x3ff00000
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
|
||||
; SI-SAFE-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, v7
|
||||
; SI-SAFE-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5]
|
||||
; SI-SAFE-NEXT: s_xor_b64 vcc, s[0:1], vcc
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
|
||||
; SI-SAFE-NEXT: s_mov_b32 s0, s4
|
||||
; SI-SAFE-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
|
||||
; SI-SAFE-NEXT: s_mov_b32 s1, s5
|
||||
; SI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
|
||||
; SI-SAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
||||
; SI-SAFE-NEXT: s_endpgm
|
||||
;
|
||||
; CI-SAFE-LABEL: rsq_f64:
|
||||
; CI-SAFE: ; %bb.0:
|
||||
; CI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; CI-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; CI-SAFE-NEXT: s_mov_b32 s6, -1
|
||||
; CI-SAFE-NEXT: s_mov_b32 s10, s6
|
||||
; CI-SAFE-NEXT: s_mov_b32 s11, s7
|
||||
; CI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-SAFE-NEXT: s_mov_b32 s8, s2
|
||||
; CI-SAFE-NEXT: s_mov_b32 s9, s3
|
||||
; CI-SAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; CI-SAFE-NEXT: s_mov_b32 s4, s0
|
||||
; CI-SAFE-NEXT: s_mov_b32 s5, s1
|
||||
; CI-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; CI-SAFE-NEXT: v_sqrt_f64_e32 v[0:1], v[0:1]
|
||||
; CI-SAFE-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], 1.0
|
||||
; CI-SAFE-NEXT: v_div_scale_f64 v[8:9], vcc, 1.0, v[0:1], 1.0
|
||||
; CI-SAFE-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; CI-SAFE-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
|
||||
; CI-SAFE-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
|
||||
; CI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
|
||||
; CI-SAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; CI-SAFE-NEXT: s_endpgm
|
||||
%val = load double, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call double @llvm.sqrt.f64(double %val) nounwind readnone
|
||||
%div = fdiv double 1.0, %sqrt
|
||||
store double %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @neg_rsq_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
; GCN-UNSAFE-LABEL: neg_rsq_f64:
|
||||
; GCN-UNSAFE: ; %bb.0:
|
||||
; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-UNSAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: v_sqrt_f64_e32 v[0:1], v[0:1]
|
||||
; GCN-UNSAFE-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
|
||||
; GCN-UNSAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; GCN-UNSAFE-NEXT: s_endpgm
|
||||
;
|
||||
; SI-SAFE-LABEL: neg_rsq_f64:
|
||||
; SI-SAFE: ; %bb.0:
|
||||
; SI-SAFE-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; SI-SAFE-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SAFE-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SAFE-NEXT: s_mov_b32 s10, s2
|
||||
; SI-SAFE-NEXT: s_mov_b32 s11, s3
|
||||
; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SAFE-NEXT: s_mov_b32 s8, s6
|
||||
; SI-SAFE-NEXT: s_mov_b32 s9, s7
|
||||
; SI-SAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-SAFE-NEXT: v_sqrt_f64_e32 v[0:1], v[0:1]
|
||||
; SI-SAFE-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], -1.0
|
||||
; SI-SAFE-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
|
||||
; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; SI-SAFE-NEXT: v_div_scale_f64 v[6:7], s[0:1], -1.0, v[0:1], -1.0
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
|
||||
; SI-SAFE-NEXT: s_mov_b32 s0, 0xbff00000
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
|
||||
; SI-SAFE-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, v7
|
||||
; SI-SAFE-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5]
|
||||
; SI-SAFE-NEXT: s_xor_b64 vcc, s[0:1], vcc
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
|
||||
; SI-SAFE-NEXT: s_mov_b32 s0, s4
|
||||
; SI-SAFE-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
|
||||
; SI-SAFE-NEXT: s_mov_b32 s1, s5
|
||||
; SI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], -1.0
|
||||
; SI-SAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
||||
; SI-SAFE-NEXT: s_endpgm
|
||||
;
|
||||
; CI-SAFE-LABEL: neg_rsq_f64:
|
||||
; CI-SAFE: ; %bb.0:
|
||||
; CI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; CI-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; CI-SAFE-NEXT: s_mov_b32 s6, -1
|
||||
; CI-SAFE-NEXT: s_mov_b32 s10, s6
|
||||
; CI-SAFE-NEXT: s_mov_b32 s11, s7
|
||||
; CI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-SAFE-NEXT: s_mov_b32 s8, s2
|
||||
; CI-SAFE-NEXT: s_mov_b32 s9, s3
|
||||
; CI-SAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; CI-SAFE-NEXT: s_mov_b32 s4, s0
|
||||
; CI-SAFE-NEXT: s_mov_b32 s5, s1
|
||||
; CI-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; CI-SAFE-NEXT: v_sqrt_f64_e32 v[0:1], v[0:1]
|
||||
; CI-SAFE-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], -1.0
|
||||
; CI-SAFE-NEXT: v_div_scale_f64 v[8:9], vcc, -1.0, v[0:1], -1.0
|
||||
; CI-SAFE-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; CI-SAFE-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
|
||||
; CI-SAFE-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
|
||||
; CI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], -1.0
|
||||
; CI-SAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; CI-SAFE-NEXT: s_endpgm
|
||||
%val = load double, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call double @llvm.sqrt.f64(double %val)
|
||||
%div = fdiv double -1.0, %sqrt
|
||||
store double %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define amdgpu_kernel void @neg_rsq_neg_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
; GCN-UNSAFE-LABEL: neg_rsq_neg_f64:
|
||||
; GCN-UNSAFE: ; %bb.0:
|
||||
; GCN-UNSAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s6, -1
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s10, s6
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s11, s7
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s8, s2
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s9, s3
|
||||
; GCN-UNSAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s4, s0
|
||||
; GCN-UNSAFE-NEXT: s_mov_b32 s5, s1
|
||||
; GCN-UNSAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-UNSAFE-NEXT: v_sqrt_f64_e64 v[0:1], -v[0:1]
|
||||
; GCN-UNSAFE-NEXT: v_rcp_f64_e32 v[2:3], v[0:1]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[4:5], -v[0:1], v[2:3], 1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[2:3], v[4:5], v[2:3], v[2:3]
|
||||
; GCN-UNSAFE-NEXT: v_mul_f64 v[4:5], v[2:3], -1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[0:1], -v[0:1], v[4:5], -1.0
|
||||
; GCN-UNSAFE-NEXT: v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
|
||||
; GCN-UNSAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; GCN-UNSAFE-NEXT: s_endpgm
|
||||
;
|
||||
; SI-SAFE-LABEL: neg_rsq_neg_f64:
|
||||
; SI-SAFE: ; %bb.0:
|
||||
; SI-SAFE-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; SI-SAFE-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-SAFE-NEXT: s_mov_b32 s2, -1
|
||||
; SI-SAFE-NEXT: s_mov_b32 s10, s2
|
||||
; SI-SAFE-NEXT: s_mov_b32 s11, s3
|
||||
; SI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-SAFE-NEXT: s_mov_b32 s8, s6
|
||||
; SI-SAFE-NEXT: s_mov_b32 s9, s7
|
||||
; SI-SAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; SI-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-SAFE-NEXT: v_sqrt_f64_e64 v[0:1], -v[0:1]
|
||||
; SI-SAFE-NEXT: v_div_scale_f64 v[2:3], s[0:1], v[0:1], v[0:1], -1.0
|
||||
; SI-SAFE-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
|
||||
; SI-SAFE-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; SI-SAFE-NEXT: v_div_scale_f64 v[6:7], s[0:1], -1.0, v[0:1], -1.0
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
|
||||
; SI-SAFE-NEXT: s_mov_b32 s0, 0xbff00000
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
|
||||
; SI-SAFE-NEXT: v_cmp_eq_u32_e64 s[0:1], s0, v7
|
||||
; SI-SAFE-NEXT: v_mul_f64 v[8:9], v[6:7], v[4:5]
|
||||
; SI-SAFE-NEXT: s_xor_b64 vcc, s[0:1], vcc
|
||||
; SI-SAFE-NEXT: v_fma_f64 v[2:3], -v[2:3], v[8:9], v[6:7]
|
||||
; SI-SAFE-NEXT: s_mov_b32 s0, s4
|
||||
; SI-SAFE-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[8:9]
|
||||
; SI-SAFE-NEXT: s_mov_b32 s1, s5
|
||||
; SI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], -1.0
|
||||
; SI-SAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
||||
; SI-SAFE-NEXT: s_endpgm
|
||||
;
|
||||
; CI-SAFE-LABEL: neg_rsq_neg_f64:
|
||||
; CI-SAFE: ; %bb.0:
|
||||
; CI-SAFE-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
||||
; CI-SAFE-NEXT: s_mov_b32 s7, 0xf000
|
||||
; CI-SAFE-NEXT: s_mov_b32 s6, -1
|
||||
; CI-SAFE-NEXT: s_mov_b32 s10, s6
|
||||
; CI-SAFE-NEXT: s_mov_b32 s11, s7
|
||||
; CI-SAFE-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-SAFE-NEXT: s_mov_b32 s8, s2
|
||||
; CI-SAFE-NEXT: s_mov_b32 s9, s3
|
||||
; CI-SAFE-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
|
||||
; CI-SAFE-NEXT: s_mov_b32 s4, s0
|
||||
; CI-SAFE-NEXT: s_mov_b32 s5, s1
|
||||
; CI-SAFE-NEXT: s_waitcnt vmcnt(0)
|
||||
; CI-SAFE-NEXT: v_sqrt_f64_e64 v[0:1], -v[0:1]
|
||||
; CI-SAFE-NEXT: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], -1.0
|
||||
; CI-SAFE-NEXT: v_div_scale_f64 v[8:9], vcc, -1.0, v[0:1], -1.0
|
||||
; CI-SAFE-NEXT: v_rcp_f64_e32 v[4:5], v[2:3]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 1.0
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
|
||||
; CI-SAFE-NEXT: v_mul_f64 v[6:7], v[8:9], v[4:5]
|
||||
; CI-SAFE-NEXT: v_fma_f64 v[2:3], -v[2:3], v[6:7], v[8:9]
|
||||
; CI-SAFE-NEXT: v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[6:7]
|
||||
; CI-SAFE-NEXT: v_div_fixup_f64 v[0:1], v[2:3], v[0:1], -1.0
|
||||
; CI-SAFE-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
||||
; CI-SAFE-NEXT: s_endpgm
|
||||
%val = load double, ptr addrspace(1) %in, align 4
|
||||
%val.fneg = fneg double %val
|
||||
%sqrt = call double @llvm.sqrt.f64(double %val.fneg)
|
||||
%div = fdiv double -1.0, %sqrt
|
||||
store double %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
|
||||
; CI: {{.*}}
|
||||
; CI-UNSAFE: {{.*}}
|
||||
; GCN: {{.*}}
|
||||
; GCN-SAFE: {{.*}}
|
||||
; SI: {{.*}}
|
||||
; SI-UNSAFE: {{.*}}
|
||||
@ -1,156 +0,0 @@
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s
|
||||
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
declare float @llvm.sqrt.f32(float) nounwind readnone
|
||||
declare double @llvm.sqrt.f64(double) nounwind readnone
|
||||
|
||||
; SI-LABEL: {{^}}rsq_f32:
|
||||
; SI: v_rsq_f32_e32
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
%val = load float, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
|
||||
%div = fdiv float 1.0, %sqrt, !fpmath !0
|
||||
store float %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}rsq_f64:
|
||||
; SI: v_sqrt_f64
|
||||
; SI: v_rcp_f64
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @rsq_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
%val = load double, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call double @llvm.sqrt.f64(double %val) nounwind readnone
|
||||
%div = fdiv double 1.0, %sqrt
|
||||
store double %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}rsq_f32_sgpr:
|
||||
; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @rsq_f32_sgpr(ptr addrspace(1) noalias %out, float %val) #0 {
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val) nounwind readnone
|
||||
%div = fdiv float 1.0, %sqrt, !fpmath !0
|
||||
store float %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Recognize that this is rsqrt(a) * rcp(b) * c,
|
||||
; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
|
||||
|
||||
; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare.
|
||||
|
||||
; SI-LABEL: @rsqrt_fmul
|
||||
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
|
||||
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
|
||||
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
|
||||
|
||||
; SI-UNSAFE-DAG: v_sqrt_f32_e32 [[SQRT:v[0-9]+]], [[A]]
|
||||
; SI-UNSAFE-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[SQRT]], [[B]]
|
||||
; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[MUL]]
|
||||
; SI-UNSAFE-DAG: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[RCP]]
|
||||
; SI-UNSAFE: buffer_store_dword [[RESULT]]
|
||||
|
||||
; SI-SAFE-NOT: v_rsq_f32
|
||||
|
||||
; SI: s_endpgm
|
||||
define amdgpu_kernel void @rsqrt_fmul(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
|
||||
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
|
||||
%out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid
|
||||
%gep.0 = getelementptr float, ptr addrspace(1) %in, i32 %tid
|
||||
%gep.1 = getelementptr float, ptr addrspace(1) %gep.0, i32 1
|
||||
%gep.2 = getelementptr float, ptr addrspace(1) %gep.0, i32 2
|
||||
|
||||
%a = load volatile float, ptr addrspace(1) %gep.0
|
||||
%b = load volatile float, ptr addrspace(1) %gep.1
|
||||
%c = load volatile float, ptr addrspace(1) %gep.2
|
||||
|
||||
%x = call float @llvm.sqrt.f32(float %a)
|
||||
%y = fmul float %x, %b
|
||||
%z = fdiv float %c, %y
|
||||
store float %z, ptr addrspace(1) %out.gep
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}neg_rsq_f32:
|
||||
; SI-SAFE: v_sqrt_f32_e32 [[SQRT:v[0-9]+]], v{{[0-9]+}}
|
||||
; SI-SAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
|
||||
; SI-SAFE: buffer_store_dword [[RSQ]]
|
||||
|
||||
; SI-UNSAFE: v_sqrt_f32_e32 [[SQRT:v[0-9]+]], v{{[0-9]+}}
|
||||
; SI-UNSAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
|
||||
; SI-UNSAFE: buffer_store_dword [[RSQ]]
|
||||
define amdgpu_kernel void @neg_rsq_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
%val = load float, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
store float %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}neg_rsq_f64:
|
||||
; SI-SAFE: v_sqrt_f64_e32
|
||||
; SI-SAFE: v_div_scale_f64
|
||||
|
||||
; SI-UNSAFE: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
|
||||
; SI-UNSAFE: v_sqrt_f64_e32 [[SQRT:v\[[0-9]+:[0-9]+\]]], [[VAL]]
|
||||
; SI-UNSAFE: v_rcp_f64_e32 [[RCP:v\[[0-9]+:[0-9]+\]]], [[VAL]]
|
||||
; SI-UNSAFE: v_fma_f64 {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]}}, [[RCP]], 1.0
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
define amdgpu_kernel void @neg_rsq_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
%val = load double, ptr addrspace(1) %in, align 4
|
||||
%sqrt = call double @llvm.sqrt.f64(double %val)
|
||||
%div = fdiv double -1.0, %sqrt
|
||||
store double %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}neg_rsq_neg_f32:
|
||||
; SI-SAFE: v_sqrt_f32_e64 [[SQRT:v[0-9]+]], -v{{[0-9]+}}
|
||||
; SI-SAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
|
||||
; SI-SAFE: buffer_store_dword [[RSQ]]
|
||||
|
||||
; SI-UNSAFE: v_sqrt_f32_e64 [[SQRT:v[0-9]+]], -v{{[0-9]+}}
|
||||
; SI-UNSAFE: v_rcp_f32_e64 [[RSQ:v[0-9]+]], -[[SQRT]]
|
||||
; SI-UNSAFE: buffer_store_dword [[RSQ]]
|
||||
define amdgpu_kernel void @neg_rsq_neg_f32(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
%val = load float, ptr addrspace(1) %in, align 4
|
||||
%val.fneg = fneg float %val
|
||||
%sqrt = call float @llvm.sqrt.f32(float %val.fneg)
|
||||
%div = fdiv float -1.0, %sqrt, !fpmath !0
|
||||
store float %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; SI-LABEL: {{^}}neg_rsq_neg_f64:
|
||||
; SI-SAFE: v_sqrt_f64_e64 v{{\[[0-9]+:[0-9]+\]}}, -v{{\[[0-9]+:[0-9]+\]}}
|
||||
; SI-SAFE: v_div_scale_f64
|
||||
|
||||
; SI-UNSAFE: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]]
|
||||
; SI-UNSAFE-DAG: v_sqrt_f64_e64 [[SQRT:v\[[0-9]+:[0-9]+\]]], -[[VAL]]
|
||||
; SI-UNSAFE: v_rcp_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], [[SQRT]]
|
||||
; SI-UNSAFE: v_fma_f64 {{v\[[0-9]+:[0-9]+\]}}, -{{v\[[0-9]+:[0-9]+\]}}, [[RSQ]], 1.0
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
; SI-UNSAFE: v_fma_f64
|
||||
define amdgpu_kernel void @neg_rsq_neg_f64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {
|
||||
%val = load double, ptr addrspace(1) %in, align 4
|
||||
%val.fneg = fneg double %val
|
||||
%sqrt = call double @llvm.sqrt.f64(double %val.fneg)
|
||||
%div = fdiv double -1.0, %sqrt
|
||||
store double %div, ptr addrspace(1) %out, align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
!0 = !{float 2.500000e+00}
|
||||
|
||||
attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
|
||||
Loading…
x
Reference in New Issue
Block a user