[RISCV] Fix a correctness issue in optimizeCondBranch. Prevent optimizing compare with x0. NFC (#145440)
We were incorrectly changing -1 to 0 for unsigned compares in case 1. The comment incorrectly said UINT64_MAX is bigger than INT64_MAX, but we were doing a signed compare and UINT64_MAX is smaller than INT64_MAX in signed space. Prevent changing 0 constants since we can use x0. The test cases for these are contrived to use addi rd, x0, 0. We're more likely to have a COPY from x0 which we already don't optimize for other reasons. Check if registers are virtual before calling hasOneUse. The use count for physical registers is meaningless.
This commit is contained in:
Craig Topper
GitHub
parent
9702d37062
commit
48a21e6915
@ -1449,11 +1449,15 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
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return Register();
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};
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if (isFromLoadImm(MRI, LHS, C0) && MRI.hasOneUse(LHS.getReg())) {
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// Might be case 1.
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// Signed integer overflow is UB. (UINT64_MAX is bigger so we don't need
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// to worry about unsigned overflow here)
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if (C0 < INT64_MAX)
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// Don't change 0 to 1 since we can use x0.
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// For unsigned cases changing -1U to 0 would be incorrect.
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// The incorrect case for signed would be INT_MAX, but isFromLoadImm can't
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// return that.
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if (isFromLoadImm(MRI, LHS, C0) && C0 != 0 && LHS.getReg().isVirtual() &&
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MRI.hasOneUse(LHS.getReg()) &&
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(CC == RISCVCC::COND_GE || CC == RISCVCC::COND_LT || C0 != -1)) {
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assert(isInt<12>(C0) && "Unexpected immediate");
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if (Register RegZ = searchConst(C0 + 1)) {
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reverseBranchCondition(Cond);
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Cond[1] = MachineOperand::CreateReg(RHS.getReg(), /*isDef=*/false);
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@ -1464,11 +1468,16 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
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modifyBranch();
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return true;
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}
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} else if (isFromLoadImm(MRI, RHS, C0) && MRI.hasOneUse(RHS.getReg())) {
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}
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// Might be case 2.
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// For unsigned cases, we don't want C1 to wrap back to UINT64_MAX
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// when C0 is zero.
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if ((CC == RISCVCC::COND_GE || CC == RISCVCC::COND_LT) || C0)
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// For signed cases we don't want to change 0 since we can use x0.
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// For unsigned cases changing 0 to -1U would be incorrect.
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// The incorrect case for signed would be INT_MIN, but isFromLoadImm can't
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// return that.
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if (isFromLoadImm(MRI, RHS, C0) && C0 != 0 && RHS.getReg().isVirtual() &&
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MRI.hasOneUse(RHS.getReg())) {
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assert(isInt<12>(C0) && "Unexpected immediate");
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if (Register RegZ = searchConst(C0 - 1)) {
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reverseBranchCondition(Cond);
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Cond[1] = MachineOperand::CreateReg(RegZ, /*isDef=*/false);
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@ -18,6 +18,74 @@
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ret void
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}
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define void @ule_negone(ptr %a, i32 signext %b, ptr %c, ptr %d) {
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store i32 0, ptr %a
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%p = icmp ule i32 %b, -1
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br i1 %p, label %block1, label %block2
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block1: ; preds = %0
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store i32 %b, ptr %c
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br label %end_block
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block2: ; preds = %0
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store i32 87, ptr %d
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br label %end_block
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end_block: ; preds = %block2, %block1
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ret void
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}
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define void @ult_zero(ptr %a, i32 signext %b, ptr %c, ptr %d) {
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store i32 -1, ptr %a
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%p = icmp ult i32 %b, 0
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br i1 %p, label %block1, label %block2
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block1: ; preds = %0
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store i32 %b, ptr %c
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br label %end_block
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block2: ; preds = %0
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store i32 87, ptr %d
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br label %end_block
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end_block: ; preds = %block2, %block1
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ret void
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}
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define void @sle_zero(ptr %a, i32 signext %b, ptr %c, ptr %d) {
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store i32 1, ptr %a
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%p = icmp sle i32 %b, 0
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br i1 %p, label %block1, label %block2
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block1: ; preds = %0
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store i32 %b, ptr %c
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br label %end_block
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block2: ; preds = %0
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store i32 87, ptr %d
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br label %end_block
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end_block: ; preds = %block2, %block1
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ret void
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}
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define void @slt_zero(ptr %a, i32 signext %b, ptr %c, ptr %d) {
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store i32 -1, ptr %a
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%p = icmp slt i32 %b, 0
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br i1 %p, label %block1, label %block2
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block1: ; preds = %0
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store i32 %b, ptr %c
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br label %end_block
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block2: ; preds = %0
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store i32 87, ptr %d
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br label %end_block
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end_block: ; preds = %block2, %block1
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ret void
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}
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declare void @bar(...)
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...
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@ -66,3 +134,243 @@ body: |
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PseudoRET
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...
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---
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name: ule_negone
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: ule_negone
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 0
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; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32))
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; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, -1
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; CHECK-NEXT: BLTU killed [[ADDI1]], [[COPY2]], %bb.2
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]]
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; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32))
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; CHECK-NEXT: PseudoBR %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87
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; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: PseudoRET
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x10, $x11, $x12, $x13
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%5:gpr = ADDI $x0, 0
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SW killed %5, %0, 0 :: (store (s32))
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%6:gpr = ADDI $x0, -1
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BLTU killed %6, %1, %bb.2
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PseudoBR %bb.1
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bb.1:
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%4:gpr = COPY %1
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SW %4, %2, 0 :: (store (s32))
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PseudoBR %bb.3
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bb.2:
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%7:gpr = ADDI $x0, 87
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SW killed %7, %3, 0 :: (store (s32))
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bb.3:
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PseudoRET
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...
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---
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name: ult_zero
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: ult_zero
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
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; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32))
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; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
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; CHECK-NEXT: BLTU [[COPY2]], killed [[ADDI1]], %bb.2
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]]
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; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32))
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; CHECK-NEXT: PseudoBR %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87
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; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: PseudoRET
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x10, $x11, $x12, $x13
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%5:gpr = ADDI $x0, -1
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SW killed %5, %0, 0 :: (store (s32))
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%6:gpr = ADDI $x0, 0
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BLTU %1, killed %6, %bb.2
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PseudoBR %bb.1
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bb.1:
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%4:gpr = COPY %1
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SW %4, %2, 0 :: (store (s32))
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PseudoBR %bb.3
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bb.2:
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%7:gpr = ADDI $x0, 87
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SW killed %7, %3, 0 :: (store (s32))
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bb.3:
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PseudoRET
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...
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---
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name: sle_zero
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: sle_zero
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
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; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32))
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; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
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; CHECK-NEXT: BLT killed [[ADDI1]], [[COPY2]], %bb.2
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]]
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; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32))
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; CHECK-NEXT: PseudoBR %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87
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; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: PseudoRET
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x10, $x11, $x12, $x13
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%5:gpr = ADDI $x0, 1
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SW killed %5, %0, 0 :: (store (s32))
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%6:gpr = ADDI $x0, 0
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BLT killed %6, %1, %bb.2
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PseudoBR %bb.1
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bb.1:
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%4:gpr = COPY %1
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SW %4, %2, 0 :: (store (s32))
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PseudoBR %bb.3
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bb.2:
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%7:gpr = ADDI $x0, 87
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SW killed %7, %3, 0 :: (store (s32))
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bb.3:
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PseudoRET
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...
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---
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name: slt_zero
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: slt_zero
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
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; CHECK-NEXT: SW killed [[ADDI]], [[COPY3]], 0 :: (store (s32))
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; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
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; CHECK-NEXT: BLT [[COPY2]], killed [[ADDI1]], %bb.2
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[COPY2]]
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; CHECK-NEXT: SW [[COPY4]], [[COPY1]], 0 :: (store (s32))
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; CHECK-NEXT: PseudoBR %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADDI2:%[0-9]+]]:gpr = ADDI $x0, 87
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; CHECK-NEXT: SW killed [[ADDI2]], [[COPY]], 0 :: (store (s32))
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: PseudoRET
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $x10, $x11, $x12, $x13
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%3:gpr = COPY $x13
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%2:gpr = COPY $x12
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%1:gpr = COPY $x11
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%0:gpr = COPY $x10
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%5:gpr = ADDI $x0, -1
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SW killed %5, %0, 0 :: (store (s32))
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%6:gpr = ADDI $x0, 0
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BLT %1, killed %6, %bb.2
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PseudoBR %bb.1
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bb.1:
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%4:gpr = COPY %1
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SW %4, %2, 0 :: (store (s32))
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PseudoBR %bb.3
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bb.2:
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%7:gpr = ADDI $x0, 87
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SW killed %7, %3, 0 :: (store (s32))
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bb.3:
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PseudoRET
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...
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