shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

[PowerPC] Remove DAG matching in ADDIStocHA (#93905)

Browse Source 
The MI is generated in `PPCDAGToDAGISel::Select` so the match pattern isn't used and can be removed.
This commit is contained in:
Kai Luo 2024-06-04 10:00:43 +08:00 committed by GitHub
parent c7b7875e1e
commit 4d20f495df
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
4 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -3343,9 +3343,7 @@ def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor
[(set i32:$rD,
(PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
"#ADDIStocHA",
[(set i32:$rD,
(PPCtoc_entry i32:$reg, tglobaladdr:$disp))]>;
"#ADDIStocHA", []>;
// TOC Data Transform on AIX
def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
"#ADDItoc",

4
llvm/test/CodeGen/PowerPC/aix-tls-gd-longlong.ll
View File

@ -117,9 +117,9 @@ define void @storesTIUninit(i64 %Val) #0 {
; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 7, 3
; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: addis 8, L..C2@u(2)
; LARGE32-NEXT: addis 3, L..C3@u(2)
; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: lwz 3, L..C3@l(3)
; LARGE32-NEXT: bla .__tls_get_mod[PR]
; LARGE32-NEXT: lwz 4, L..C2@l(8)
@ -191,9 +191,9 @@ define void @storesTIInit(i64 %Val) #0 {
; LARGE32-NEXT: stwu 1, -32(1)
; LARGE32-NEXT: stw 0, 40(1)
; LARGE32-NEXT: mr 7, 3
; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: addis 8, L..C4@u(2)
; LARGE32-NEXT: addis 3, L..C3@u(2)
; LARGE32-NEXT: mr 6, 4
; LARGE32-NEXT: lwz 3, L..C3@l(3)
; LARGE32-NEXT: bla .__tls_get_mod[PR]
; LARGE32-NEXT: lwz 4, L..C4@l(8)

2
llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll
View File

@ -308,9 +308,9 @@ entry:
; DIS-NEXT: mflr 0
; DIS-NEXT: stwu 1, -32(1)
; DIS-NEXT: stw 0, 40(1)
; DIS-NEXT: li 5, 1
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE]
; DIS-NEXT: li 5, 1
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(3)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0

6
llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
View File

@ -32,7 +32,7 @@ entry:
; RELOC-NEXT: Relocations [
; RELOC-NEXT: Section (index: 1) .text {
; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x16
; RELOC-NEXT: Virtual Address: 0x12
; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]])
; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0
@ -40,7 +40,7 @@ entry:
; RELOC-NEXT: Type: R_TOCU (0x30)
; RELOC-NEXT: }
; RELOC-NEXT: Relocation {
; RELOC-NEXT: Virtual Address: 0x1A
; RELOC-NEXT: Virtual Address: 0x16
; RELOC-NEXT: Symbol: _$TLSML ([[#NFA+21]])
; RELOC-NEXT: IsSigned: No
; RELOC-NEXT: FixupBitValue: 0
@ -558,11 +558,11 @@ entry:
; DIS-NEXT: stwu 1, -32(1)
; DIS-NEXT: stw 0, 40(1)
; DIS-NEXT: mr 7, 3
; DIS-NEXT: mr 6, 4
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 8, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) TIInit[TE]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) _$TLSML[TC]
; DIS-NEXT: mr 6, 4
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 4(3)
; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) _$TLSML[TC]
; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0x0