shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"

Browse Source 
This reverts commit 030d33409568b2f0ea61116e83fd40ca27ba33ac.

This commit is causing build failures
This commit is contained in:
Michael Maitland 2023-08-24 11:57:38 -07:00
parent 71c72a9e17
commit 4d27dffb43
80 changed files with 2595 additions and 2612 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

73
llvm/include/llvm/CodeGen/MachineScheduler.h
View File

@ -656,15 +656,15 @@ public:
///
/// Consider an instruction that uses resources X0, X1 and X2 as follows:
///
/// X0 X1 X1 X2 +--------+-------------+--------------+
/// |Resource|AcquireAtCycle|ReleaseAtCycle|
/// +--------+-------------+--------------+
/// | X0 | 0 | 1 |
/// +--------+-------------+--------------+
/// | X1 | 1 | 3 |
/// +--------+-------------+--------------+
/// | X2 | 3 | 4 |
/// +--------+-------------+--------------+
/// X0 X1 X1 X2 +--------+------------+------+
/// |Resource|StartAtCycle|Cycles|
/// +--------+------------+------+
/// | X0 | 0 | 1 |
/// +--------+------------+------+
/// | X1 | 1 | 3 |
/// +--------+------------+------+
/// | X2 | 3 | 4 |
/// +--------+------------+------+
///
/// If we can schedule the instruction at cycle C, we need to
/// compute the interval of the resource as follows:
@ -685,7 +685,7 @@ public:
/// of an instruction that can be scheduled at cycle C in top-down
/// scheduling is:
///
/// [C+AcquireAtCycle, C+ReleaseAtCycle)
/// [C+StartAtCycle, C+Cycles)
///
///
/// # BOTTOM UP SCHEDULING
@ -709,20 +709,20 @@ public:
/// of an instruction that can be scheduled at cycle C in bottom-up
/// scheduling is:
///
/// [C-ReleaseAtCycle+1, C-AcquireAtCycle+1)
/// [C-Cycle+1, C-StartAtCycle+1)
///
///
/// NOTE: In both cases, the number of cycles booked by a
/// resources is the value (ReleaseAtCycle - AcquireAtCycle).
static IntervalTy getResourceIntervalBottom(unsigned C, unsigned AcquireAtCycle,
unsigned ReleaseAtCycle) {
return std::make_pair<long, long>((long)C - (long)ReleaseAtCycle + 1L,
(long)C - (long)AcquireAtCycle + 1L);
/// resources is the value (Cycle - StartAtCycles).
static IntervalTy getResourceIntervalBottom(unsigned C, unsigned StartAtCycle,
unsigned Cycle) {
return std::make_pair<long, long>((long)C - (long)Cycle + 1L,
(long)C - (long)StartAtCycle + 1L);
}
static IntervalTy getResourceIntervalTop(unsigned C, unsigned AcquireAtCycle,
unsigned ReleaseAtCycle) {
return std::make_pair<long, long>((long)C + (long)AcquireAtCycle,
(long)C + (long)ReleaseAtCycle);
static IntervalTy getResourceIntervalTop(unsigned C, unsigned StartAtCycle,
unsigned Cycle) {
return std::make_pair<long, long>((long)C + (long)StartAtCycle,
(long)C + (long)Cycle);
}
private:
@ -730,7 +730,7 @@ private:
///
/// The function uses the \param IntervalBuider [*] to build a
/// resource interval [a, b[ out of the input parameters \param
/// CurrCycle, \param AcquireAtCycle and \param ReleaseAtCycle.
/// CurrCycle, \param StartAtCycle and \param Cycle.
///
/// The function then loops through the intervals in the ResourceSegments
/// and shifts the interval [a, b[ and the ReturnCycle to the
@ -744,7 +744,7 @@ private:
/// c 1 2 3 4 5 6 7 8 9 10 ... ---> (time
/// flow)
/// ResourceSegments... [---) [-------) [-----------)
/// c [1 3[ -> AcquireAtCycle=1, ReleaseAtCycle=3
/// c [1 3[ -> StartAtCycle=1, Cycles=3
/// ++c [1 3)
/// ++c [1 3)
/// ++c [1 3)
@ -772,25 +772,24 @@ private:
/// [*] See \ref `getResourceIntervalTop` and
/// \ref `getResourceIntervalBottom` to see how such resource intervals
/// are built.
unsigned getFirstAvailableAt(
unsigned CurrCycle, unsigned AcquireAtCycle, unsigned ReleaseAtCycle,
std::function<IntervalTy(unsigned, unsigned, unsigned)> IntervalBuilder)
const;
unsigned
getFirstAvailableAt(unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
std::function<IntervalTy(unsigned, unsigned, unsigned)>
IntervalBuilder) const;
public:
/// getFirstAvailableAtFromBottom and getFirstAvailableAtFromTop
/// should be merged in a single function in which a function that
/// creates the `NewInterval` is passed as a parameter.
unsigned getFirstAvailableAtFromBottom(unsigned CurrCycle,
unsigned AcquireAtCycle,
unsigned ReleaseAtCycle) const {
return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
unsigned StartAtCycle,
unsigned Cycle) const {
return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
getResourceIntervalBottom);
}
unsigned getFirstAvailableAtFromTop(unsigned CurrCycle,
unsigned AcquireAtCycle,
unsigned ReleaseAtCycle) const {
return getFirstAvailableAt(CurrCycle, AcquireAtCycle, ReleaseAtCycle,
unsigned getFirstAvailableAtFromTop(unsigned CurrCycle, unsigned StartAtCycle,
unsigned Cycle) const {
return getFirstAvailableAt(CurrCycle, StartAtCycle, Cycle,
getResourceIntervalTop);
}
@ -1007,13 +1006,13 @@ public:
unsigned getLatencyStallCycles(SUnit *SU);
unsigned getNextResourceCycleByInstance(unsigned InstanceIndex,
unsigned ReleaseAtCycle,
unsigned AcquireAtCycle);
unsigned Cycles,
unsigned StartAtCycle);
std::pair<unsigned, unsigned> getNextResourceCycle(const MCSchedClassDesc *SC,
unsigned PIdx,
unsigned ReleaseAtCycle,
unsigned AcquireAtCycle);
unsigned Cycles,
unsigned StartAtCycle);
bool isUnbufferedGroup(unsigned PIdx) const {
return SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin &&

6
llvm/include/llvm/CodeGen/MachineTraceMetrics.h
View File

@ -143,7 +143,7 @@ public:
/// The getResources() function above must have been called first.
///
/// These numbers have already been scaled by SchedModel.getResourceFactor().
ArrayRef<unsigned> getProcReleaseAtCycles(unsigned MBBNum) const;
ArrayRef<unsigned> getProcResourceCycles(unsigned MBBNum) const;
/// A virtual register or regunit required by a basic block or its trace
/// successors.
@ -404,9 +404,9 @@ private:
// Cycles consumed on each processor resource per block.
// The number of processor resource kinds is constant for a given subtarget,
// but it is not known at compile time. The number of cycles consumed by
// block B on processor resource R is at ProcReleaseAtCycles[B*Kinds + R]
// block B on processor resource R is at ProcResourceCycles[B*Kinds + R]
// where Kinds = SchedModel.getNumProcResourceKinds().
SmallVector<unsigned, 0> ProcReleaseAtCycles;
SmallVector<unsigned, 0> ProcResourceCycles;
// One ensemble per strategy.
Ensemble

19
llvm/include/llvm/MC/MCSchedule.h
View File

@ -60,21 +60,24 @@ struct MCProcResourceDesc {
/// Identify one of the processor resource kinds consumed by a
/// particular scheduling class for the specified number of cycles.
/// TODO: consider renaming the field `StartAtCycle` and `Cycles` to
/// `AcquireAtCycle` and `ReleaseAtCycle` respectively, to stress the
/// fact that resource allocation is now represented as an interval,
/// relatively to the issue cycle of the instruction.
struct MCWriteProcResEntry {
uint16_t ProcResourceIdx;
/// Cycle at which the resource will be released by an instruction,
/// relatively to the cycle in which the instruction is issued
/// (assuming no stalls inbetween).
uint16_t ReleaseAtCycle;
/// Cycle at which the resource will be aquired by an instruction,
uint16_t Cycles;
/// Cycle at which the resource will be grabbed by an instruction,
/// relatively to the cycle in which the instruction is issued
/// (assuming no stalls inbetween).
uint16_t AcquireAtCycle;
uint16_t StartAtCycle;
bool operator==(const MCWriteProcResEntry &Other) const {
return ProcResourceIdx == Other.ProcResourceIdx &&
ReleaseAtCycle == Other.ReleaseAtCycle &&
AcquireAtCycle == Other.AcquireAtCycle;
return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles &&
StartAtCycle == Other.StartAtCycle;
}
};
@ -223,12 +226,12 @@ struct MCExtraProcessorInfo {
/// consistent. Inaccuracies arise when instructions have different execution
/// delays relative to each other, in addition to their intrinsic latency. Those
/// special cases can be handled by TableGen constructs such as, ReadAdvance,
/// which reduces latency when reading data, and ReleaseAtCycles, which consumes
/// which reduces latency when reading data, and ResourceCycles, which consumes
/// a processor resource when writing data for a number of abstract
/// cycles.
///
/// TODO: One tool currently missing is the ability to add a delay to
/// ReleaseAtCycles. That would be easy to add and would likely cover all cases
/// ResourceCycles. That would be easy to add and would likely cover all cases
/// currently handled by the legacy itinerary tables.
///
/// A note on out-of-order execution and, more generally, instruction

2
llvm/include/llvm/MCA/HWEventListener.h
View File

@ -63,7 +63,7 @@ public:
// ResourceRef::second is a bitmask of the referenced sub-unit of the resource.
using ResourceRef = std::pair<uint64_t, uint64_t>;
using ResourceUse = std::pair<ResourceRef, ReleaseAtCycles>;
using ResourceUse = std::pair<ResourceRef, ResourceCycles>;
class HWInstructionIssuedEvent : public HWInstructionEvent {
public:

2
llvm/include/llvm/MCA/HardwareUnits/ResourceManager.h
View File

@ -430,7 +430,7 @@ public:
void issueInstruction(
const InstrDesc &Desc,
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
void cycleEvent(SmallVectorImpl<ResourceRef> &ResourcesFreed);

4
llvm/include/llvm/MCA/HardwareUnits/Scheduler.h
View File

@ -136,7 +136,7 @@ class Scheduler : public HardwareUnit {
/// Issue an instruction without updating the ready queue.
void issueInstructionImpl(
InstRef &IR,
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes);
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes);
// Identify instructions that have finished executing, and remove them from
// the IssuedSet. References to executed instructions are added to input
@ -202,7 +202,7 @@ public:
/// result of this event.
void issueInstruction(
InstRef &IR,
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Used,
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Used,
SmallVectorImpl<InstRef> &Pending,
SmallVectorImpl<InstRef> &Ready);

10
llvm/include/llvm/MCA/Support.h
View File

@ -48,12 +48,12 @@ template <typename T> char InstructionError<T>::ID;
/// number of resources, are kept separate. This is used by the
/// ResourcePressureView to calculate the average resource cycles
/// per instruction/iteration.
class ReleaseAtCycles {
class ResourceCycles {
unsigned Numerator, Denominator;
public:
ReleaseAtCycles() : Numerator(0), Denominator(1) {}
ReleaseAtCycles(unsigned Cycles, unsigned ResourceUnits = 1)
ResourceCycles() : Numerator(0), Denominator(1) {}
ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
: Numerator(Cycles), Denominator(ResourceUnits) {}
operator double() const {
@ -67,7 +67,7 @@ public:
// Add the components of RHS to this instance. Instead of calculating
// the final value here, we keep track of the numerator and denominator
// separately, to reduce floating point error.
ReleaseAtCycles &operator+=(const ReleaseAtCycles &RHS);
ResourceCycles &operator+=(const ResourceCycles &RHS);
};
/// Populates vector Masks with processor resource masks.
@ -105,7 +105,7 @@ inline unsigned getResourceStateIndex(uint64_t Mask) {
/// Compute the reciprocal block throughput from a set of processor resource
/// cycles. The reciprocal block throughput is computed as the MAX between:
/// - NumMicroOps / DispatchWidth
/// - ProcReleaseAtCycles / #ProcResourceUnits (for every consumed resource).
/// - ProcResourceCycles / #ProcResourceUnits (for every consumed resource).
double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
unsigned NumMicroOps,
ArrayRef<unsigned> ProcResourceUsage);

20
llvm/include/llvm/Target/TargetSchedule.td
View File

@ -147,7 +147,7 @@ class ProcResourceKind;
// changes this to an in-order issue/dispatch resource. In this case,
// the scheduler counts down from the cycle that the instruction
// issues in-order, forcing a stall whenever a subsequent instruction
// requires the same resource until the number of ReleaseAtCycles
// requires the same resource until the number of ResourceCycles
// specified in WriteRes expire. Setting BufferSize=1 changes this to
// an in-order latency resource. In this case, the scheduler models
// producer/consumer stalls between instructions that use the
@ -254,14 +254,8 @@ class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
// SchedModel ties these resources to a processor.
class ProcWriteResources<list<ProcResourceKind> resources> {
list<ProcResourceKind> ProcResources = resources;
/// Cycle at which the resource will be released by an instruction,
/// relatively to the cycle in which the instruction is issued
/// (assuming no stalls inbetween).
list<int> ReleaseAtCycles = [];
/// Cycle at which the resource will be aquired by an instruction,
/// relatively to the cycle in which the instruction is issued
/// (assuming no stalls inbetween).
list<int> AcquireAtCycles = [];
list<int> ResourceCycles = [];
list<int> StartAtCycles = [];
int Latency = 1;
int NumMicroOps = 1;
bit BeginGroup = false;
@ -291,12 +285,12 @@ class ProcWriteResources<list<ProcResourceKind> resources> {
// itinerary classes to the subtarget's SchedWrites.
//
// ProcResources indicates the set of resources consumed by the write.
// Optionally, ReleaseAtCycles indicates the number of cycles the
// resource is consumed. Each ReleaseAtCycles item is paired with the
// ProcResource item at the same position in its list. ReleaseAtCycles
// Optionally, ResourceCycles indicates the number of cycles the
// resource is consumed. Each ResourceCycles item is paired with the
// ProcResource item at the same position in its list. ResourceCycles
// can be `[]`: in that case, all resources are consumed for a single
// cycle, regardless of latency, which models a fully pipelined processing
// unit. A value of 0 for ReleaseAtCycles means that the resource must
// unit. A value of 0 for ResourceCycles means that the resource must
// be available but is not consumed, which is only relevant for
// unbuffered resources.
//

12
llvm/lib/CodeGen/MachinePipeliner.cpp
View File

@ -1039,7 +1039,7 @@ struct FuncUnitSorter {
for (const MCWriteProcResEntry &PRE :
make_range(STI->getWriteProcResBegin(SCDesc),
STI->getWriteProcResEnd(SCDesc))) {
if (!PRE.ReleaseAtCycle)
if (!PRE.Cycles)
continue;
const MCProcResourceDesc *ProcResource =
STI->getSchedModel().getProcResource(PRE.ProcResourceIdx);
@ -1082,7 +1082,7 @@ struct FuncUnitSorter {
for (const MCWriteProcResEntry &PRE :
make_range(STI->getWriteProcResBegin(SCDesc),
STI->getWriteProcResEnd(SCDesc))) {
if (!PRE.ReleaseAtCycle)
if (!PRE.Cycles)
continue;
Resources[PRE.ProcResourceIdx]++;
}
@ -3092,7 +3092,7 @@ void ResourceManager::reserveResources(const MCSchedClassDesc *SCDesc,
assert(!UseDFA);
for (const MCWriteProcResEntry &PRE : make_range(
STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
++MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
@ -3104,7 +3104,7 @@ void ResourceManager::unreserveResources(const MCSchedClassDesc *SCDesc,
assert(!UseDFA);
for (const MCWriteProcResEntry &PRE : make_range(
STI->getWriteProcResBegin(SCDesc), STI->getWriteProcResEnd(SCDesc)))
for (int C = Cycle; C < Cycle + PRE.ReleaseAtCycle; ++C)
for (int C = Cycle; C < Cycle + PRE.Cycles; ++C)
--MRT[positiveModulo(C, InitiationInterval)][PRE.ProcResourceIdx];
for (int C = Cycle; C < Cycle + SCDesc->NumMicroOps; ++C)
@ -3220,10 +3220,10 @@ int ResourceManager::calculateResMII() const {
if (SwpDebugResource) {
const MCProcResourceDesc *Desc =
SM.getProcResource(PRE.ProcResourceIdx);
dbgs() << Desc->Name << ": " << PRE.ReleaseAtCycle << ", ";
dbgs() << Desc->Name << ": " << PRE.Cycles << ", ";
}
});
ResourceCount[PRE.ProcResourceIdx] += PRE.ReleaseAtCycle;
ResourceCount[PRE.ProcResourceIdx] += PRE.Cycles;
}
LLVM_DEBUG(if (SwpDebugResource) dbgs() << "\n");
}

113
llvm/lib/CodeGen/MachineScheduler.cpp
View File

@ -980,8 +980,8 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceTopDown() const {
for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC),
PE = SchedModel.getWriteProcResEnd(SC);
PI != PE; ++PI) {
if (SU->TopReadyCycle + PI->ReleaseAtCycle - 1 > LastCycle)
LastCycle = SU->TopReadyCycle + PI->ReleaseAtCycle - 1;
if (SU->TopReadyCycle + PI->Cycles - 1 > LastCycle)
LastCycle = SU->TopReadyCycle + PI->Cycles - 1;
}
}
// Print the header with the cycles
@ -1017,20 +1017,19 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceTopDown() const {
llvm::stable_sort(ResourcesIt,
[](const MCWriteProcResEntry &LHS,
const MCWriteProcResEntry &RHS) -> bool {
return LHS.AcquireAtCycle < RHS.AcquireAtCycle ||
(LHS.AcquireAtCycle == RHS.AcquireAtCycle &&
LHS.ReleaseAtCycle < RHS.ReleaseAtCycle);
return LHS.StartAtCycle < RHS.StartAtCycle ||
(LHS.StartAtCycle == RHS.StartAtCycle &&
LHS.Cycles < RHS.Cycles);
});
for (const MCWriteProcResEntry &PI : ResourcesIt) {
C = FirstCycle;
const std::string ResName =
SchedModel.getResourceName(PI.ProcResourceIdx);
dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth);
for (; C < SU->TopReadyCycle + PI.AcquireAtCycle; ++C) {
for (; C < SU->TopReadyCycle + PI.StartAtCycle; ++C) {
dbgs() << llvm::left_justify("|", ColWidth);
}
for (unsigned I = 0, E = PI.ReleaseAtCycle - PI.AcquireAtCycle; I != E;
++I, ++C)
for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, ++C)
dbgs() << llvm::left_justify("| x", ColWidth);
while (C++ <= LastCycle)
dbgs() << llvm::left_justify("|", ColWidth);
@ -1062,8 +1061,8 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceBottomUp() const {
for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC),
PE = SchedModel.getWriteProcResEnd(SC);
PI != PE; ++PI) {
if ((int)SU->BotReadyCycle - PI->ReleaseAtCycle + 1 < LastCycle)
LastCycle = (int)SU->BotReadyCycle - PI->ReleaseAtCycle + 1;
if ((int)SU->BotReadyCycle - PI->Cycles + 1 < LastCycle)
LastCycle = (int)SU->BotReadyCycle - PI->Cycles + 1;
}
}
// Print the header with the cycles
@ -1098,20 +1097,19 @@ LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceBottomUp() const {
llvm::stable_sort(ResourcesIt,
[](const MCWriteProcResEntry &LHS,
const MCWriteProcResEntry &RHS) -> bool {
return LHS.AcquireAtCycle < RHS.AcquireAtCycle ||
(LHS.AcquireAtCycle == RHS.AcquireAtCycle &&
LHS.ReleaseAtCycle < RHS.ReleaseAtCycle);
return LHS.StartAtCycle < RHS.StartAtCycle ||
(LHS.StartAtCycle == RHS.StartAtCycle &&
LHS.Cycles < RHS.Cycles);
});
for (const MCWriteProcResEntry &PI : ResourcesIt) {
C = FirstCycle;
const std::string ResName =
SchedModel.getResourceName(PI.ProcResourceIdx);
dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth);
for (; C > ((int)SU->BotReadyCycle - (int)PI.AcquireAtCycle); --C) {
for (; C > ((int)SU->BotReadyCycle - (int)PI.StartAtCycle); --C) {
dbgs() << llvm::left_justify("|", ColWidth);
}
for (unsigned I = 0, E = PI.ReleaseAtCycle - PI.AcquireAtCycle; I != E;
++I, --C)
for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, --C)
dbgs() << llvm::left_justify("| x", ColWidth);
while (C-- >= LastCycle)
dbgs() << llvm::left_justify("|", ColWidth);
@ -2239,9 +2237,8 @@ init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel) {
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
unsigned PIdx = PI->ProcResourceIdx;
unsigned Factor = SchedModel->getResourceFactor(PIdx);
assert(PI->ReleaseAtCycle >= PI->AcquireAtCycle);
RemainingCounts[PIdx] +=
(Factor * (PI->ReleaseAtCycle - PI->AcquireAtCycle));
assert(PI->Cycles >= PI->StartAtCycle);
RemainingCounts[PIdx] += (Factor * (PI->Cycles - PI->StartAtCycle));
}
}
}
@ -2294,15 +2291,15 @@ unsigned SchedBoundary::getLatencyStallCycles(SUnit *SU) {
/// Compute the next cycle at which the given processor resource unit
/// can be scheduled.
unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
unsigned ReleaseAtCycle,
unsigned AcquireAtCycle) {
unsigned Cycles,
unsigned StartAtCycle) {
if (SchedModel && SchedModel->enableIntervals()) {
if (isTop())
return ReservedResourceSegments[InstanceIdx].getFirstAvailableAtFromTop(
CurrCycle, AcquireAtCycle, ReleaseAtCycle);
CurrCycle, StartAtCycle, Cycles);
return ReservedResourceSegments[InstanceIdx].getFirstAvailableAtFromBottom(
CurrCycle, AcquireAtCycle, ReleaseAtCycle);
CurrCycle, StartAtCycle, Cycles);
}
unsigned NextUnreserved = ReservedCycles[InstanceIdx];
@ -2311,7 +2308,7 @@ unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
return CurrCycle;
// For bottom-up scheduling add the cycles needed for the current operation.
if (!isTop())
NextUnreserved = std::max(CurrCycle, NextUnreserved + ReleaseAtCycle);
NextUnreserved = std::max(CurrCycle, NextUnreserved + Cycles);
return NextUnreserved;
}
@ -2320,8 +2317,7 @@ unsigned SchedBoundary::getNextResourceCycleByInstance(unsigned InstanceIdx,
/// instance in the reserved cycles vector.
std::pair<unsigned, unsigned>
SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
unsigned ReleaseAtCycle,
unsigned AcquireAtCycle) {
unsigned Cycles, unsigned StartAtCycle) {
if (MischedDetailResourceBooking) {
LLVM_DEBUG(dbgs() << " Resource booking (@" << CurrCycle << "c): \n");
LLVM_DEBUG(dumpReservedCycles());
@ -2350,15 +2346,15 @@ SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
make_range(SchedModel->getWriteProcResBegin(SC),
SchedModel->getWriteProcResEnd(SC)))
if (ResourceGroupSubUnitMasks[PIdx][PE.ProcResourceIdx])
return std::make_pair(getNextResourceCycleByInstance(
StartIndex, ReleaseAtCycle, AcquireAtCycle),
StartIndex);
return std::make_pair(
getNextResourceCycleByInstance(StartIndex, Cycles, StartAtCycle),
StartIndex);
auto SubUnits = SchedModel->getProcResource(PIdx)->SubUnitsIdxBegin;
for (unsigned I = 0, End = NumberOfInstances; I < End; ++I) {
unsigned NextUnreserved, NextInstanceIdx;
std::tie(NextUnreserved, NextInstanceIdx) =
getNextResourceCycle(SC, SubUnits[I], ReleaseAtCycle, AcquireAtCycle);
getNextResourceCycle(SC, SubUnits[I], Cycles, StartAtCycle);
if (MinNextUnreserved > NextUnreserved) {
InstanceIdx = NextInstanceIdx;
MinNextUnreserved = NextUnreserved;
@ -2370,7 +2366,7 @@ SchedBoundary::getNextResourceCycle(const MCSchedClassDesc *SC, unsigned PIdx,
for (unsigned I = StartIndex, End = StartIndex + NumberOfInstances; I < End;
++I) {
unsigned NextUnreserved =
getNextResourceCycleByInstance(I, ReleaseAtCycle, AcquireAtCycle);
getNextResourceCycleByInstance(I, Cycles, StartAtCycle);
if (MischedDetailResourceBooking)
LLVM_DEBUG(dbgs() << " Instance " << I - StartIndex << " available @"
<< NextUnreserved << "c\n");
@ -2427,14 +2423,14 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
make_range(SchedModel->getWriteProcResBegin(SC),
SchedModel->getWriteProcResEnd(SC))) {
unsigned ResIdx = PE.ProcResourceIdx;
unsigned ReleaseAtCycle = PE.ReleaseAtCycle;
unsigned AcquireAtCycle = PE.AcquireAtCycle;
unsigned Cycles = PE.Cycles;
unsigned StartAtCycle = PE.StartAtCycle;
unsigned NRCycle, InstanceIdx;
std::tie(NRCycle, InstanceIdx) =
getNextResourceCycle(SC, ResIdx, ReleaseAtCycle, AcquireAtCycle);
getNextResourceCycle(SC, ResIdx, Cycles, StartAtCycle);
if (NRCycle > CurrCycle) {
#if LLVM_ENABLE_ABI_BREAKING_CHECKS
MaxObservedStall = std::max(ReleaseAtCycle, MaxObservedStall);
MaxObservedStall = std::max(Cycles, MaxObservedStall);
#endif
LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
<< SchedModel->getResourceName(ResIdx)
@ -2576,22 +2572,18 @@ void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
/// Add the given processor resource to this scheduled zone.
///
/// \param ReleaseAtCycle indicates the number of consecutive (non-pipelined)
/// cycles during which this resource is released.
///
/// \param AcquireAtCycle indicates the number of consecutive (non-pipelined)
/// cycles at which the resource is aquired after issue (assuming no stalls).
/// \param Cycles indicates the number of consecutive (non-pipelined) cycles
/// during which this resource is consumed.
///
/// \return the next cycle at which the instruction may execute without
/// oversubscribing resources.
unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx,
unsigned ReleaseAtCycle,
unsigned NextCycle,
unsigned AcquireAtCycle) {
unsigned Cycles, unsigned NextCycle,
unsigned StartAtCycle) {
unsigned Factor = SchedModel->getResourceFactor(PIdx);
unsigned Count = Factor * (ReleaseAtCycle- AcquireAtCycle);
unsigned Count = Factor * (Cycles - StartAtCycle);
LLVM_DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx) << " +"
<< ReleaseAtCycle << "x" << Factor << "u\n");
<< Cycles << "x" << Factor << "u\n");
// Update Executed resources counts.
incExecutedResources(PIdx, Count);
@ -2610,7 +2602,7 @@ unsigned SchedBoundary::countResource(const MCSchedClassDesc *SC, unsigned PIdx,
// For reserved resources, record the highest cycle using the resource.
unsigned NextAvailable, InstanceIdx;
std::tie(NextAvailable, InstanceIdx) =
getNextResourceCycle(SC, PIdx, ReleaseAtCycle, AcquireAtCycle);
getNextResourceCycle(SC, PIdx, Cycles, StartAtCycle);
if (NextAvailable > CurrCycle) {
LLVM_DEBUG(dbgs() << " Resource conflict: "
<< SchedModel->getResourceName(PIdx)
@ -2689,9 +2681,8 @@ void SchedBoundary::bumpNode(SUnit *SU) {
for (TargetSchedModel::ProcResIter
PI = SchedModel->getWriteProcResBegin(SC),
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
unsigned RCycle =
countResource(SC, PI->ProcResourceIdx, PI->ReleaseAtCycle, NextCycle,
PI->AcquireAtCycle);
unsigned RCycle = countResource(SC, PI->ProcResourceIdx, PI->Cycles,
NextCycle, PI->StartAtCycle);
if (RCycle > NextCycle)
NextCycle = RCycle;
}
@ -2708,27 +2699,27 @@ void SchedBoundary::bumpNode(SUnit *SU) {
if (SchedModel && SchedModel->enableIntervals()) {
unsigned ReservedUntil, InstanceIdx;
std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(
SC, PIdx, PI->ReleaseAtCycle, PI->AcquireAtCycle);
std::tie(ReservedUntil, InstanceIdx) =
getNextResourceCycle(SC, PIdx, PI->Cycles, PI->StartAtCycle);
if (isTop()) {
ReservedResourceSegments[InstanceIdx].add(
ResourceSegments::getResourceIntervalTop(
NextCycle, PI->AcquireAtCycle, PI->ReleaseAtCycle),
NextCycle, PI->StartAtCycle, PI->Cycles),
MIResourceCutOff);
} else {
ReservedResourceSegments[InstanceIdx].add(
ResourceSegments::getResourceIntervalBottom(
NextCycle, PI->AcquireAtCycle, PI->ReleaseAtCycle),
NextCycle, PI->StartAtCycle, PI->Cycles),
MIResourceCutOff);
}
} else {
unsigned ReservedUntil, InstanceIdx;
std::tie(ReservedUntil, InstanceIdx) = getNextResourceCycle(
SC, PIdx, PI->ReleaseAtCycle, PI->AcquireAtCycle);
std::tie(ReservedUntil, InstanceIdx) =
getNextResourceCycle(SC, PIdx, PI->Cycles, PI->StartAtCycle);
if (isTop()) {
ReservedCycles[InstanceIdx] =
std::max(ReservedUntil, NextCycle + PI->ReleaseAtCycle);
std::max(ReservedUntil, NextCycle + PI->Cycles);
} else
ReservedCycles[InstanceIdx] = NextCycle;
}
@ -2926,9 +2917,9 @@ initResourceDelta(const ScheduleDAGMI *DAG,
PI = SchedModel->getWriteProcResBegin(SC),
PE = SchedModel->getWriteProcResEnd(SC); PI != PE; ++PI) {
if (PI->ProcResourceIdx == Policy.ReduceResIdx)
ResDelta.CritResources += PI->ReleaseAtCycle;
ResDelta.CritResources += PI->Cycles;
if (PI->ProcResourceIdx == Policy.DemandResIdx)
ResDelta.DemandedResources += PI->ReleaseAtCycle;
ResDelta.DemandedResources += PI->Cycles;
}
}
@ -4256,7 +4247,7 @@ static bool sortIntervals(const ResourceSegments::IntervalTy &A,
}
unsigned ResourceSegments::getFirstAvailableAt(
unsigned CurrCycle, unsigned AcquireAtCycle, unsigned Cycle,
unsigned CurrCycle, unsigned StartAtCycle, unsigned Cycle,
std::function<ResourceSegments::IntervalTy(unsigned, unsigned, unsigned)>
IntervalBuilder) const {
assert(std::is_sorted(std::begin(_Intervals), std::end(_Intervals),
@ -4264,7 +4255,7 @@ unsigned ResourceSegments::getFirstAvailableAt(
"Cannot execute on an un-sorted set of intervals.");
unsigned RetCycle = CurrCycle;
ResourceSegments::IntervalTy NewInterval =
IntervalBuilder(RetCycle, AcquireAtCycle, Cycle);
IntervalBuilder(RetCycle, StartAtCycle, Cycle);
for (auto &Interval : _Intervals) {
if (!intersects(NewInterval, Interval))
continue;
@ -4274,7 +4265,7 @@ unsigned ResourceSegments::getFirstAvailableAt(
assert(Interval.second > NewInterval.first &&
"Invalid intervals configuration.");
RetCycle += (unsigned)Interval.second - (unsigned)NewInterval.first;
NewInterval = IntervalBuilder(RetCycle, AcquireAtCycle, Cycle);
NewInterval = IntervalBuilder(RetCycle, StartAtCycle, Cycle);
}
return RetCycle;
}

26
llvm/lib/CodeGen/MachineTraceMetrics.cpp
View File

@ -71,7 +71,7 @@ bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) {
Loops = &getAnalysis<MachineLoopInfo>();
SchedModel.init(&ST);
BlockInfo.resize(MF->getNumBlockIDs());
ProcReleaseAtCycles.resize(MF->getNumBlockIDs() *
ProcResourceCycles.resize(MF->getNumBlockIDs() *
SchedModel.getNumProcResourceKinds());
return false;
}
@ -126,7 +126,7 @@ MachineTraceMetrics::getResources(const MachineBasicBlock *MBB) {
PI = SchedModel.getWriteProcResBegin(SC),
PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
assert(PI->ProcResourceIdx < PRKinds && "Bad processor resource kind");
PRCycles[PI->ProcResourceIdx] += PI->ReleaseAtCycle;
PRCycles[PI->ProcResourceIdx] += PI->Cycles;
}
}
FBI->InstrCount = InstrCount;
@ -134,19 +134,19 @@ MachineTraceMetrics::getResources(const MachineBasicBlock *MBB) {
// Scale the resource cycles so they are comparable.
unsigned PROffset = MBB->getNumber() * PRKinds;
for (unsigned K = 0; K != PRKinds; ++K)
ProcReleaseAtCycles[PROffset + K] =
ProcResourceCycles[PROffset + K] =
PRCycles[K] * SchedModel.getResourceFactor(K);
return FBI;
}
ArrayRef<unsigned>
MachineTraceMetrics::getProcReleaseAtCycles(unsigned MBBNum) const {
MachineTraceMetrics::getProcResourceCycles(unsigned MBBNum) const {
assert(BlockInfo[MBBNum].hasResources() &&
"getResources() must be called before getProcReleaseAtCycles()");
"getResources() must be called before getProcResourceCycles()");
unsigned PRKinds = SchedModel.getNumProcResourceKinds();
assert((MBBNum+1) * PRKinds <= ProcReleaseAtCycles.size());
return ArrayRef(ProcReleaseAtCycles.data() + MBBNum * PRKinds, PRKinds);
assert((MBBNum+1) * PRKinds <= ProcResourceCycles.size());
return ArrayRef(ProcResourceCycles.data() + MBBNum * PRKinds, PRKinds);
}
//===----------------------------------------------------------------------===//
@ -197,7 +197,7 @@ computeDepthResources(const MachineBasicBlock *MBB) {
// Compute per-resource depths.
ArrayRef<unsigned> PredPRDepths = getProcResourceDepths(PredNum);
ArrayRef<unsigned> PredPRCycles = MTM.getProcReleaseAtCycles(PredNum);
ArrayRef<unsigned> PredPRCycles = MTM.getProcResourceCycles(PredNum);
for (unsigned K = 0; K != PRKinds; ++K)
ProcResourceDepths[PROffset + K] = PredPRDepths[K] + PredPRCycles[K];
}
@ -212,7 +212,7 @@ computeHeightResources(const MachineBasicBlock *MBB) {
// Compute resources for the current block.
TBI->InstrHeight = MTM.getResources(MBB)->InstrCount;
ArrayRef<unsigned> PRCycles = MTM.getProcReleaseAtCycles(MBB->getNumber());
ArrayRef<unsigned> PRCycles = MTM.getProcResourceCycles(MBB->getNumber());
// The trace tail is done.
if (!TBI->Succ) {
@ -1204,7 +1204,7 @@ unsigned MachineTraceMetrics::Trace::getResourceDepth(bool Bottom) const {
unsigned PRMax = 0;
ArrayRef<unsigned> PRDepths = TE.getProcResourceDepths(getBlockNum());
if (Bottom) {
ArrayRef<unsigned> PRCycles = TE.MTM.getProcReleaseAtCycles(getBlockNum());
ArrayRef<unsigned> PRCycles = TE.MTM.getProcResourceCycles(getBlockNum());
for (unsigned K = 0; K != PRDepths.size(); ++K)
PRMax = std::max(PRMax, PRDepths[K] + PRCycles[K]);
} else {
@ -1248,8 +1248,8 @@ unsigned MachineTraceMetrics::Trace::getResourceLength(
PI != PE; ++PI) {
if (PI->ProcResourceIdx != ResourceIdx)
continue;
Cycles += (PI->ReleaseAtCycle *
TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
Cycles +=
(PI->Cycles * TE.MTM.SchedModel.getResourceFactor(ResourceIdx));
}
}
return Cycles;
@ -1258,7 +1258,7 @@ unsigned MachineTraceMetrics::Trace::getResourceLength(
for (unsigned K = 0; K != PRDepths.size(); ++K) {
unsigned PRCycles = PRDepths[K] + PRHeights[K];
for (const MachineBasicBlock *MBB : Extrablocks)
PRCycles += TE.MTM.getProcReleaseAtCycles(MBB->getNumber())[K];
PRCycles += TE.MTM.getProcResourceCycles(MBB->getNumber())[K];
PRCycles += extraCycles(ExtraInstrs, K);
PRCycles -= extraCycles(RemoveInstrs, K);
PRMax = std::max(PRMax, PRCycles);

4
llvm/lib/MC/MCSchedule.cpp
View File

@ -94,10 +94,10 @@ MCSchedModel::getReciprocalThroughput(const MCSubtargetInfo &STI,
const MCWriteProcResEntry *I = STI.getWriteProcResBegin(&SCDesc);
const MCWriteProcResEntry *E = STI.getWriteProcResEnd(&SCDesc);
for (; I != E; ++I) {
if (!I->ReleaseAtCycle)
if (!I->Cycles)
continue;
unsigned NumUnits = SM.getProcResource(I->ProcResourceIdx)->NumUnits;
double Temp = NumUnits * 1.0 / I->ReleaseAtCycle;
double Temp = NumUnits * 1.0 / I->Cycles;
Throughput = Throughput ? std::min(*Throughput, Temp) : Temp;
}
if (Throughput)

6
llvm/lib/MCA/HardwareUnits/ResourceManager.cpp
View File

@ -346,7 +346,7 @@ uint64_t ResourceManager::checkAvailability(const InstrDesc &Desc) const {
void ResourceManager::issueInstruction(
const InstrDesc &Desc,
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &Pipes) {
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &Pipes) {
for (const std::pair<uint64_t, ResourceUsage> &R : Desc.Resources) {
const CycleSegment &CS = R.second.CS;
if (!CS.size()) {
@ -359,8 +359,8 @@ void ResourceManager::issueInstruction(
ResourceRef Pipe = selectPipe(R.first);
use(Pipe);
BusyResources[Pipe] += CS.size();
Pipes.emplace_back(std::pair<ResourceRef, ReleaseAtCycles>(
Pipe, ReleaseAtCycles(CS.size())));
Pipes.emplace_back(std::pair<ResourceRef, ResourceCycles>(
Pipe, ResourceCycles(CS.size())));
} else {
assert((llvm::popcount(R.first) > 1) && "Expected a group!");
// Mark this group as reserved.

4
llvm/lib/MCA/HardwareUnits/Scheduler.cpp
View File

@ -69,7 +69,7 @@ Scheduler::Status Scheduler::isAvailable(const InstRef &IR) {
void Scheduler::issueInstructionImpl(
InstRef &IR,
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources) {
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources) {
Instruction *IS = IR.getInstruction();
const InstrDesc &D = IS->getDesc();
@ -98,7 +98,7 @@ void Scheduler::issueInstructionImpl(
// Release the buffered resources and issue the instruction.
void Scheduler::issueInstruction(
InstRef &IR,
SmallVectorImpl<std::pair<ResourceRef, ReleaseAtCycles>> &UsedResources,
SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedResources,
SmallVectorImpl<InstRef> &PendingInstructions,
SmallVectorImpl<InstRef> &ReadyInstructions) {
const Instruction &Inst = *IR.getInstruction();

8
llvm/lib/MCA/InstrBuilder.cpp
View File

@ -69,7 +69,7 @@ static void initializeUsedResources(InstrDesc &ID,
for (unsigned I = 0, E = SCDesc.NumWriteProcResEntries; I < E; ++I) {
const MCWriteProcResEntry *PRE = STI.getWriteProcResBegin(&SCDesc) + I;
const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx);
if (!PRE->ReleaseAtCycle) {
if (!PRE->Cycles) {
#ifndef NDEBUG
WithColor::warning()
<< "Ignoring invalid write of zero cycles on processor resource "
@ -89,11 +89,11 @@ static void initializeUsedResources(InstrDesc &ID,
AllInOrderResources &= (PR.BufferSize <= 1);
}
CycleSegment RCy(0, PRE->ReleaseAtCycle, false);
CycleSegment RCy(0, PRE->Cycles, false);
Worklist.emplace_back(ResourcePlusCycles(Mask, ResourceUsage(RCy)));
if (PR.SuperIdx) {
uint64_t Super = ProcResourceMasks[PR.SuperIdx];
SuperResources[Super] += PRE->ReleaseAtCycle;
SuperResources[Super] += PRE->Cycles;
}
}
@ -156,7 +156,7 @@ static void initializeUsedResources(InstrDesc &ID,
// is reserved. For example (on target x86; cpu Haswell):
//
// SchedWriteRes<[HWPort0, HWPort1, HWPort01]> {
// let ReleaseAtCycles = [2, 2, 3];
// let ResourceCycles = [2, 2, 3];
// }
//
// This means:

2
llvm/lib/MCA/Stages/ExecuteStage.cpp
View File

@ -196,7 +196,7 @@ Error ExecuteStage::execute(InstRef &IR) {
// Reserve a slot in each buffered resource. Also, mark units with
// BufferSize=0 as reserved. Resources with a buffer size of zero will only
// be released after MCIS is issued, and all the ReleaseAtCycles for those
// be released after MCIS is issued, and all the ResourceCycles for those
// units have been consumed.
bool IsReadyInstruction = HWS.dispatch(IR);
const Instruction &Inst = *IR.getInstruction();

5
llvm/lib/MCA/Stages/InstructionTables.cpp
View File

@ -38,7 +38,7 @@ Error InstructionTables::execute(InstRef &IR) {
for (unsigned I = 0, E = NumUnits; I < E; ++I) {
ResourceRef ResourceUnit = std::make_pair(Index, 1U << I);
UsedResources.emplace_back(
std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits)));
std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits)));
}
continue;
}
@ -53,8 +53,7 @@ Error InstructionTables::execute(InstRef &IR) {
for (unsigned I2 = 0, E2 = SubUnit.NumUnits; I2 < E2; ++I2) {
ResourceRef ResourceUnit = std::make_pair(SubUnitIdx, 1U << I2);
UsedResources.emplace_back(std::make_pair(
ResourceUnit,
ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits)));
ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits)));
}
}
}

10
llvm/lib/MCA/Support.cpp
View File

@ -21,7 +21,7 @@ namespace mca {
#define DEBUG_TYPE "llvm-mca"
ReleaseAtCycles &ReleaseAtCycles::operator+=(const ReleaseAtCycles &RHS) {
ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) {
if (Denominator == RHS.Denominator)
Numerator += RHS.Numerator;
else {
@ -92,18 +92,18 @@ double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth,
// The number of available resource units affects the resource pressure
// distribution, as well as how many blocks can be executed every cycle.
for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
unsigned ReleaseAtCycles = ProcResourceUsage[I];
if (!ReleaseAtCycles)
unsigned ResourceCycles = ProcResourceUsage[I];
if (!ResourceCycles)
continue;
const MCProcResourceDesc &MCDesc = *SM.getProcResource(I);
double Throughput = static_cast<double>(ReleaseAtCycles) / MCDesc.NumUnits;
double Throughput = static_cast<double>(ResourceCycles) / MCDesc.NumUnits;
Max = std::max(Max, Throughput);
}
// The block reciprocal throughput is computed as the MAX of:
// - (NumMicroOps / DispatchWidth)
// - (NumUnits / ReleaseAtCycles) for every consumed processor resource.
// - (NumUnits / ResourceCycles) for every consumed processor resource.
return Max;
}

42
llvm/lib/Target/AArch64/AArch64SchedA510.td
View File

@ -74,14 +74,14 @@ def : WriteRes<WriteIS, [CortexA510UnitALU]> { let Latency = 2; } // Shift/S
// MAC
def : WriteRes<WriteIM32, [CortexA510UnitMAC]> { let Latency = 3; } // 32-bit Multiply
def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ReleaseAtCycles = [2];} // 64-bit Multiply
def : WriteRes<WriteIM64, [CortexA510UnitMAC]> { let Latency = 5; let ResourceCycles = [2];} // 64-bit Multiply
// Div
def : WriteRes<WriteID32, [CortexA510UnitDiv]> {
let Latency = 8; let ReleaseAtCycles = [8];
let Latency = 8; let ResourceCycles = [8];
}
def : WriteRes<WriteID64, [CortexA510UnitDiv]> {
let Latency = 16; let ReleaseAtCycles = [16];
let Latency = 16; let ResourceCycles = [16];
}
//===----------------------------------------------------------------------===//
@ -94,7 +94,7 @@ class CortexA510Write<int n, ProcResourceKind res> : SchedWriteRes<[res]> {
class CortexA510MCWrite<int n, int m, ProcResourceKind res> : SchedWriteRes<[res]> {
let Latency = n;
let ReleaseAtCycles = [m];
let ResourceCycles = [m];
let BeginGroup = 1;
}
@ -127,15 +127,15 @@ def : WriteRes<WriteLDHi, [CortexA510UnitLd]> { let Latency = 2; }
def CortexA510WriteVLD1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
def CortexA510WriteVLD1SI : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; let SingleIssue = 1; }
def CortexA510WriteVLD2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 4;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def CortexA510WriteVLD3 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def CortexA510WriteVLD4 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def CortexA510WriteVLD6 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 5;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def CortexA510WriteVLD8 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 6;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def CortexA510WriteLDP1 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
def CortexA510WriteLDP2 : SchedWriteRes<[CortexA510UnitLd]> { let Latency = 3; }
@ -154,14 +154,14 @@ def : WriteRes<WriteSTX, [CortexA510UnitLdSt]> { let Latency = 3; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [CortexA510UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [2];}
let ResourceCycles = [2];}
def CortexA510WriteVST1 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 4; }
def CortexA510WriteVST2 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def CortexA510WriteVST3 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def CortexA510WriteVST4 : SchedWriteRes<[CortexA510UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@ -183,7 +183,7 @@ def : WriteRes<WriteFImm, [CortexA510UnitVALU]> { let Latency = 3; }
class CortexA510VSt<int n> : SchedWriteRes<[CortexA510UnitLdSt]> {
let RetireOOO = 1;
let ReleaseAtCycles = [n];
let ResourceCycles = [n];
}
def CortexA510VSt0 : SchedWriteRes<[CortexA510UnitLdSt]> {
@ -202,20 +202,20 @@ def : WriteRes<WriteFMul, [CortexA510UnitVMAC]> { let Latency = 4; }
let RetireOOO = 1 in {
def : WriteRes<WriteFDiv, [CortexA510UnitVMC]> { let Latency = 22;
let ReleaseAtCycles = [29]; }
let ResourceCycles = [29]; }
def CortexA510WriteVMAC : SchedWriteRes<[CortexA510UnitVMAC]> { let Latency = 4; }
def CortexA510WriteFDivHP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def CortexA510WriteFDivSP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 13;
let ReleaseAtCycles = [10]; }
let ResourceCycles = [10]; }
def CortexA510WriteFDivDP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 22;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
def CortexA510WriteFSqrtHP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def CortexA510WriteFSqrtSP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 12;
let ReleaseAtCycles = [9]; }
let ResourceCycles = [9]; }
def CortexA510WriteFSqrtDP : SchedWriteRes<[CortexA510UnitVMC]> { let Latency = 22;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
}
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.

26
llvm/lib/Target/AArch64/AArch64SchedA53.td
View File

@ -83,16 +83,16 @@ def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
// May model this more carefully in the future. The remaining
// A53WriteVLD# types represent the 1-5 cycle issues explicitly.
def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def A53WriteVLD1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
def A53WriteVLD2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def A53WriteVLD3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def A53WriteVLD4 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 7;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def A53WriteVLD5 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
// Pre/Post Indexing - Performed as part of address generation which is already
// accounted for in the WriteST* latencies below
@ -106,12 +106,12 @@ def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [2];}
let ResourceCycles = [2];}
def A53WriteVST1 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 4; }
def A53WriteVST2 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def A53WriteVST3 : SchedWriteRes<[A53UnitLdSt]> { let Latency = 6;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@ -134,16 +134,16 @@ def : WriteRes<WriteVq, [A53UnitFPALU]> { let Latency = 6; }
// FP Mul, Div, Sqrt
def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
let ReleaseAtCycles = [29]; }
let ResourceCycles = [29]; }
def A53WriteFMAC : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 10; }
def A53WriteFDivSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 18;
let ReleaseAtCycles = [14]; }
let ResourceCycles = [14]; }
def A53WriteFDivDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
let ReleaseAtCycles = [29]; }
let ResourceCycles = [29]; }
def A53WriteFSqrtSP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 17;
let ReleaseAtCycles = [13]; }
let ResourceCycles = [13]; }
def A53WriteFSqrtDP : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
let ReleaseAtCycles = [28]; }
let ResourceCycles = [28]; }
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.

42
llvm/lib/Target/AArch64/AArch64SchedA55.td
View File

@ -76,10 +76,10 @@ def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit M
// Div
def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
let Latency = 8; let ReleaseAtCycles = [8];
let Latency = 8; let ResourceCycles = [8];
}
def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
let Latency = 8; let ReleaseAtCycles = [8];
let Latency = 8; let ResourceCycles = [8];
}
// Load
@ -91,23 +91,23 @@ def : WriteRes<WriteLDHi, [CortexA55UnitLd]> { let Latency = 5; }
// below, choosing the median of 3 which makes the latency 6.
// An extra cycle is needed to get the swizzling right.
def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def CortexA55WriteVLD1 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; }
def CortexA55WriteVLD1SI : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; let SingleIssue = 1; }
def CortexA55WriteVLD2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def CortexA55WriteVLD3 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 6;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def CortexA55WriteVLD4 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 7;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def CortexA55WriteVLD5 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def CortexA55WriteVLD6 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 9;
let ReleaseAtCycles = [6]; }
let ResourceCycles = [6]; }
def CortexA55WriteVLD7 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 10;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11;
let ReleaseAtCycles = [8]; }
let ResourceCycles = [8]; }
def CortexA55WriteLDP1 : SchedWriteRes<[]> { let Latency = 4; }
def CortexA55WriteLDP2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5; }
@ -126,14 +126,14 @@ def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }
// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;
let ReleaseAtCycles = [2];}
let ResourceCycles = [2];}
def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; }
def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def CortexA55WriteVST3 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 6;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def CortexA55WriteVST4 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@ -189,20 +189,20 @@ def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }
let RetireOOO = 1 in {
def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;
let ReleaseAtCycles = [29]; }
let ResourceCycles = [29]; }
def CortexA55WriteFMAC : SchedWriteRes<[CortexA55UnitFPMAC]> { let Latency = 4; }
def CortexA55WriteFDivHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def CortexA55WriteFDivSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 13;
let ReleaseAtCycles = [10]; }
let ResourceCycles = [10]; }
def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
def CortexA55WriteFSqrtHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def CortexA55WriteFSqrtSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 12;
let ReleaseAtCycles = [9]; }
let ResourceCycles = [9]; }
def CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
}
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedRead types.

12
llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td
View File

@ -34,17 +34,17 @@ def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_5cyc_1W_Mul_Forward : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
let ReleaseAtCycles = [17]; }
let ResourceCycles = [17]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
let ReleaseAtCycles = [32]; }
let ResourceCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
let ReleaseAtCycles = [35]; }
let ResourceCycles = [35]; }
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
@ -63,7 +63,7 @@ def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
def A57Write_64cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
let Latency = 64;
let NumMicroOps = 2;
let ReleaseAtCycles = [32, 32];
let ResourceCycles = [32, 32];
}
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
@ -160,7 +160,7 @@ def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
def A57Write_34cyc_2W : SchedWriteRes<[A57UnitW, A57UnitW]> {
let Latency = 34;
let NumMicroOps = 2;
let ReleaseAtCycles = [17, 17];
let ResourceCycles = [17, 17];
}
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {

130
llvm/lib/Target/AArch64/AArch64SchedA64FX.td
View File

@ -672,13 +672,13 @@ def : WriteRes<WriteIS, [A64FXGI2456]> {
// Divide, W-form
def : WriteRes<WriteID32, [A64FXGI4]> {
let Latency = 39;
let ReleaseAtCycles = [39];
let ResourceCycles = [39];
}
// Divide, X-form
def : WriteRes<WriteID64, [A64FXGI4]> {
let Latency = 23;
let ReleaseAtCycles = [23];
let ResourceCycles = [23];
}
// Multiply accumulate, W-form
@ -1254,7 +1254,7 @@ def : InstRW<[A64FXWrite_STUR, ReadAdrBase],
// FP negate
def : WriteRes<WriteF, [A64FXGI03]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// FP arithmetic
@ -1265,7 +1265,7 @@ def : InstRW<[A64FXWrite_4Cyc_GI03], (instrs FSUBDrr, FSUBHrr)>;
// FP compare
def : WriteRes<WriteFCmp, [A64FXGI03]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// FP Div, Sqrt
@ -1327,21 +1327,21 @@ def : InstRW<[A64FXWrite_4Cyc_GI03], (instregex "^FCSEL")>;
// FP convert, from vec to gen reg
def : WriteRes<WriteFCvt, [A64FXGI03]> {
let Latency = 9;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// FP move, immed
// FP move, register
def : WriteRes<WriteFImm, [A64FXGI0]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// FP transfer, from gen to vec reg
// FP transfer, from vec to gen reg
def : WriteRes<WriteFCopy, [A64FXGI0]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_FMOV_GV], (instrs FMOVXDHighr)>;
@ -2113,14 +2113,14 @@ def : InstRW<[A64FXWrite_None], (instregex "^SETFFR", "^MOVPRFX")>;
def A64FXWrite_FMAIndexed : SchedWriteRes<[A64FXGI03]> {
let Latency = 15;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_FMAIndexed], (instregex "^F(MLA|MLS|MUL)_ZZZI")>;
def A64FXWrite_ADR_LSL_Z : SchedWriteRes<[A64FXGI0]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_ADR_LSL_Z], (instregex "^ADR_LSL_Z")>;
@ -2133,7 +2133,7 @@ def : InstRW<[A64FXWrite_ASRD], (instregex "^ASRD_Z")>;
def A64FXWrite_Reduction4CycB : SchedWriteRes<[A64FXGI03]> {
let Latency = 46;
let NumMicroOps = 10;
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
}
def : InstRW<[A64FXWrite_Reduction4CycB],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_B")>;
@ -2141,7 +2141,7 @@ def : InstRW<[A64FXWrite_Reduction4CycB],
def A64FXWrite_Reduction4CycH : SchedWriteRes<[A64FXGI03]> {
let Latency = 42;
let NumMicroOps = 9;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_Reduction4CycH],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_H")>;
@ -2149,7 +2149,7 @@ def : InstRW<[A64FXWrite_Reduction4CycH],
def A64FXWrite_Reduction4CycS : SchedWriteRes<[A64FXGI03]> {
let Latency = 38;
let NumMicroOps = 8;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def : InstRW<[A64FXWrite_Reduction4CycS],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_S")>;
@ -2157,7 +2157,7 @@ def : InstRW<[A64FXWrite_Reduction4CycS],
def A64FXWrite_Reduction4CycD : SchedWriteRes<[A64FXGI03]> {
let Latency = 34;
let NumMicroOps = 7;
let ReleaseAtCycles = [7];
let ResourceCycles = [7];
}
def : InstRW<[A64FXWrite_Reduction4CycD],
(instregex "^(AND|EOR|OR|SADD|SMAX|SMIN|UADD|UMAX|UMIN)V_VPZ_D")>;
@ -2184,7 +2184,7 @@ def : InstRW<[A64FXWrite_CPYScalar], (instregex "^CPY_ZPmR")>;
def A64FXWrite_CTERM : SchedWriteRes<[A64FXGI24]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_CTERM], (instregex "^CTERM")>;
@ -2202,42 +2202,42 @@ def : InstRW<[A64FXWrite_INCPVector], (instregex "^DECP_Z", "^INCP_Z")>;
def A64FXWrite_FADDVH : SchedWriteRes<[A64FXGI03]> {
let Latency = 75;
let NumMicroOps = 11;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
def : InstRW<[A64FXWrite_FADDVH], (instrs FADDV_VPZ_H)>;
def A64FXWrite_FADDVS : SchedWriteRes<[A64FXGI03]> {
let Latency = 60;
let NumMicroOps = 9;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_FADDVS], (instrs FADDV_VPZ_S)>;
def A64FXWrite_FADDVD : SchedWriteRes<[A64FXGI03]> {
let Latency = 45;
let NumMicroOps = 7;
let ReleaseAtCycles = [7];
let ResourceCycles = [7];
}
def : InstRW<[A64FXWrite_FADDVD], (instrs FADDV_VPZ_D)>;
def A64FXWrite_FADDAH : SchedWriteRes<[A64FXGI03]> {
let Latency = 468;
let NumMicroOps = 63;
let ReleaseAtCycles = [63];
let ResourceCycles = [63];
}
def : InstRW<[A64FXWrite_FADDAH], (instrs FADDA_VPZ_H)>;
def A64FXWrite_FADDAS : SchedWriteRes<[A64FXGI03]> {
let Latency = 228;
let NumMicroOps = 31;
let ReleaseAtCycles = [31];
let ResourceCycles = [31];
}
def : InstRW<[A64FXWrite_FADDAS], (instrs FADDA_VPZ_S)>;
def A64FXWrite_FADDAD : SchedWriteRes<[A64FXGI03]> {
let Latency = 108;
let NumMicroOps = 15;
let ReleaseAtCycles = [15];
let ResourceCycles = [15];
}
def : InstRW<[A64FXWrite_FADDAD], (instrs FADDA_VPZ_D)>;
@ -2250,53 +2250,53 @@ def : InstRW<[A64FXWrite_FCADDZ], (instregex "^FCADD_Z")>;
def A64FXWrite_FCMLAZ : SchedWriteRes<[A64FXGI03]> {
let Latency = 15;
let NumMicroOps = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : InstRW<[A64FXWrite_FCMLAZ], (instregex "^FCMLA_Z")>;
def A64FXWrite_FDIVH : SchedWriteRes<[A64FXGI0]> {
let Latency = 134;
let ReleaseAtCycles = [134];
let ResourceCycles = [134];
}
def : InstRW<[A64FXWrite_FDIVH], (instregex "^F(DIVR?|SQRT)_Z.*_H")>;
def A64FXWrite_FDIVS : SchedWriteRes<[A64FXGI0]> {
let Latency = 98;
let ReleaseAtCycles = [98];
let ResourceCycles = [98];
}
def : InstRW<[A64FXWrite_FDIVS], (instregex "^F(DIVR?|SQRT)_Z.*_S")>;
def A64FXWrite_FDIVD : SchedWriteRes<[A64FXGI0]> {
let Latency = 154;
let ReleaseAtCycles = [154];
let ResourceCycles = [154];
}
def : InstRW<[A64FXWrite_FDIVD], (instregex "^F(DIVR?|SQRT)_Z.*_D")>;
def A64FXWrite_FMAXVH : SchedWriteRes<[A64FXGI03]> {
let Latency = 54;
let NumMicroOps = 11;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
def : InstRW<[A64FXWrite_FMAXVH], (instregex "^F(MAX|MIN)(NM)?V_VPZ_H")>;
def A64FXWrite_FMAXVS : SchedWriteRes<[A64FXGI03]> {
let Latency = 44;
let NumMicroOps = 9;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_FMAXVS], (instregex "^F(MAX|MIN)(NM)?V_VPZ_S")>;
def A64FXWrite_FMAXVD : SchedWriteRes<[A64FXGI03]> {
let Latency = 34;
let NumMicroOps = 7;
let ReleaseAtCycles = [7];
let ResourceCycles = [7];
}
def : InstRW<[A64FXWrite_FMAXVH], (instregex "^F(MAX|MIN)(NM)?V_VPZ_D")>;
def A64FXWrite_INDEX_RI_BH : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
let Latency = 17;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 2];
let ResourceCycles = [2, 2];
}
def : InstRW<[A64FXWrite_INDEX_RI_BH], (instregex "^INDEX_(RI|IR)_[BH]")>;
@ -2309,21 +2309,21 @@ def : InstRW<[A64FXWrite_INDEX_RI_SD], (instregex "^INDEX_(RI|IR)_[SD]")>;
def A64FXWrite_INDEX_II_BH : SchedWriteRes<[A64FXGI0]> {
let Latency = 13;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_INDEX_II_BH], (instregex "^INDEX_II_[BH]")>;
def A64FXWrite_INDEX_RR_BH : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI3]> {
let Latency = 17;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 2, 1];
let ResourceCycles = [2, 2, 1];
}
def : InstRW<[A64FXWrite_INDEX_RR_BH], (instregex "^INDEX_RR_[BH]")>;
def A64FXWrite_INDEX_RR_SD : SchedWriteRes<[A64FXGI0, A64FXGI2]> {
let Latency = 17;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
}
def : InstRW<[A64FXWrite_INDEX_RR_SD], (instregex "^INDEX_RR_[SD]")>;
@ -2339,28 +2339,28 @@ def : InstRW<[A64FXWrite_CLAST_R], (instregex "^LAST[AB]_R")>;
def A64FXWrite_GLD_S_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 19;
let ReleaseAtCycles = [2, 4, 4];
let ResourceCycles = [2, 4, 4];
}
def : InstRW<[A64FXWrite_GLD_S_ZI],
(instregex "^GLD(FF)?1W_IMM", "^GLD(FF)?1S?[BHW]_S_IMM")>;
def A64FXWrite_GLD_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 16;
let ReleaseAtCycles = [1, 2, 2];
let ResourceCycles = [1, 2, 2];
}
def : InstRW<[A64FXWrite_GLD_D_ZI],
(instregex "^GLD(FF)?1D_IMM", "^GLD(FF)?1S?[BHW]_D_IMM")>;
def A64FXWrite_GLD_S_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 23;
let ReleaseAtCycles = [2, 1, 4, 4];
let ResourceCycles = [2, 1, 4, 4];
}
def : InstRW<[A64FXWrite_GLD_S_RZ],
(instregex "^GLD(FF)?1W_[^DI]", "^GLD(FF)?1S?[BHW]_S_[^I]")>;
def A64FXWrite_GLD_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 20;
let ReleaseAtCycles = [1, 1, 2, 2];
let ResourceCycles = [1, 1, 2, 2];
}
def : InstRW<[A64FXWrite_GLD_D_RZ],
(instregex "^GLD(FF)?1D_[^I]", "^GLD(FF)?1D$", "^GLD(FF)?1S?[BHW]_D_[^I]",
@ -2369,63 +2369,63 @@ def : InstRW<[A64FXWrite_GLD_D_RZ],
def A64FXWrite_LD2_BH : SchedWriteRes<[A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 3;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
def A64FXWrite_LD2_WD_IMM : SchedWriteRes<[A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_LD2_WD_IMM], (instregex "^LD2[WD]_IMM")>;
def A64FXWrite_LD2_WD : SchedWriteRes<[A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : InstRW<[A64FXWrite_LD2_WD], (instregex "^LD2[WD]$")>;
def A64FXWrite_LD3_BH : SchedWriteRes<[A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 4;
let ReleaseAtCycles = [13];
let ResourceCycles = [13];
}
def : InstRW<[A64FXWrite_LD3_BH], (instregex "^LD3[BH]")>;
def A64FXWrite_LD3_WD_IMM : SchedWriteRes<[A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : InstRW<[A64FXWrite_LD3_WD_IMM], (instregex "^LD3[WD]_IMM")>;
def A64FXWrite_LD3_WD : SchedWriteRes<[A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def : InstRW<[A64FXWrite_LD3_WD], (instregex "^LD3[WD]$")>;
def A64FXWrite_LD4_BH : SchedWriteRes<[A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 5;
let ReleaseAtCycles = [17];
let ResourceCycles = [17];
}
def : InstRW<[A64FXWrite_LD4_BH], (instregex "^LD4[BH]")>;
def A64FXWrite_LD4_WD_IMM : SchedWriteRes<[A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def : InstRW<[A64FXWrite_LD4_WD_IMM], (instregex "^LD4[WD]_IMM")>;
def A64FXWrite_LD4_WD : SchedWriteRes<[A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 5;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
}
def : InstRW<[A64FXWrite_LD4_WD], (instregex "^LD4[WD]$")>;
@ -2434,34 +2434,34 @@ def A64FXWrite_PRF : SchedWriteRes<[A64FXGI56]> {
def : InstRW<[A64FXWrite_PRF], (instregex "^PRF._PR")>;
def A64FXWrite_PRF_W_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI56]> {
let ReleaseAtCycles = [2, 1, 4];
let ResourceCycles = [2, 1, 4];
}
def : InstRW<[A64FXWrite_PRF_W_RZ], (instregex "^PRF._S_[^P]")>;
def A64FXWrite_PRF_W_ZI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let ReleaseAtCycles = [2, 4];
let ResourceCycles = [2, 4];
}
def : InstRW<[A64FXWrite_PRF_W_ZI], (instregex "^PRF._S_PZI")>;
def A64FXWrite_PRF_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI56]> {
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
}
def : InstRW<[A64FXWrite_PRF_D_RZ], (instregex "^PRF._D_[^P]")>;
def A64FXWrite_PRF_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[A64FXWrite_PRF_D_ZI], (instregex "^PRF._D_PZI")>;
def A64FXWrite_SDIV_S : SchedWriteRes<[A64FXGI0]> {
let Latency = 114;
let ReleaseAtCycles = [114];
let ResourceCycles = [114];
}
def : InstRW<[A64FXWrite_SDIV_S], (instregex "^[SU]DIVR?.*_S")>;
def A64FXWrite_SDIV_D : SchedWriteRes<[A64FXGI0]> {
let Latency = 178;
let ReleaseAtCycles = [178];
let ResourceCycles = [178];
}
def : InstRW<[A64FXWrite_SDIV_D], (instregex "^[SU]DIVR?.*_D")>;
@ -2473,14 +2473,14 @@ def : InstRW<[A64FXWrite_SDOT_I], (instregex "^[SU]DOT_ZZZI")>;
def A64FXWrite_SQINC_Scalar : SchedWriteRes<[A64FXGI24]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[A64FXWrite_SQINC_Scalar], (instregex "^[SU]Q(INC|DEC)[BHWD]_[WX]")>;
def A64FXWrite_SQINCP_X : SchedWriteRes<[A64FXGI24, A64FXGI3]> {
let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [3, 1];
let ResourceCycles = [3, 1];
}
def : InstRW<[A64FXWrite_SQINCP_X], (instregex "^[SU]Q(INC|DEC)P_[WX]")>;
@ -2497,7 +2497,7 @@ def : InstRW<[A64FXWrite_ST1], (instregex "^ST(NT)?1[BHWD]")>;
def A64FXWrite_SST1_W_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 20;
let NumMicroOps = 8;
let ReleaseAtCycles = [8, 8, 8, 8];
let ResourceCycles = [8, 8, 8, 8];
}
def : InstRW<[A64FXWrite_SST1_W_RZ],
(instregex "^SST1[BH]_S(_[^I]|$)", "^SST1W(_[^ID]|$)")>;
@ -2505,7 +2505,7 @@ def : InstRW<[A64FXWrite_SST1_W_RZ],
def A64FXWrite_SST1_D_RZ : SchedWriteRes<[A64FXGI0, A64FXGI2, A64FXGI5, A64FXGI6]> {
let Latency = 20;
let NumMicroOps = 4;
let ReleaseAtCycles = [4, 4, 4, 4];
let ResourceCycles = [4, 4, 4, 4];
}
def : InstRW<[A64FXWrite_SST1_D_RZ],
(instregex "^SST1[BHW]_D(_[^I]|$)", "^SST1D(_[^I]|$)")>;
@ -2513,7 +2513,7 @@ def : InstRW<[A64FXWrite_SST1_D_RZ],
def A64FXWrite_SST1_W_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 16;
let NumMicroOps = 8;
let ReleaseAtCycles = [12, 8, 8];
let ResourceCycles = [12, 8, 8];
}
def : InstRW<[A64FXWrite_SST1_W_ZI],
(instregex "^SST1[BH]_S_I", "^SST1W_I")>;
@ -2521,7 +2521,7 @@ def : InstRW<[A64FXWrite_SST1_W_ZI],
def A64FXWrite_SST1_D_ZI : SchedWriteRes<[A64FXGI0, A64FXGI5, A64FXGI6]> {
let Latency = 16;
let NumMicroOps = 4;
let ReleaseAtCycles = [4, 4, 4];
let ResourceCycles = [4, 4, 4];
}
def : InstRW<[A64FXWrite_SST1_D_ZI],
(instregex "^SST1[BHW]_D_I", "^SST1D_I")>;
@ -2529,63 +2529,63 @@ def : InstRW<[A64FXWrite_SST1_D_ZI],
def A64FXWrite_ST2_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 3;
let ReleaseAtCycles = [8, 9];
let ResourceCycles = [8, 9];
}
def : InstRW<[A64FXWrite_ST2_BH], (instregex "^ST2[BH]")>;
def A64FXWrite_ST2_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 2];
let ResourceCycles = [2, 2];
}
def : InstRW<[A64FXWrite_ST2_WD_RI], (instregex "^ST2[WD]$")>;
def A64FXWrite_ST2_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 3];
let ResourceCycles = [2, 3];
}
def : InstRW<[A64FXWrite_ST2_WD_RR], (instregex "^ST2[WD]_I")>;
def A64FXWrite_ST3_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 4;
let ReleaseAtCycles = [12, 13];
let ResourceCycles = [12, 13];
}
def : InstRW<[A64FXWrite_ST3_BH], (instregex "^ST3[BH]")>;
def A64FXWrite_ST3_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 3;
let ReleaseAtCycles = [3, 3];
let ResourceCycles = [3, 3];
}
def : InstRW<[A64FXWrite_ST3_WD_RI], (instregex "^ST3[WD]$")>;
def A64FXWrite_ST3_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 4;
let ReleaseAtCycles = [3, 4];
let ResourceCycles = [3, 4];
}
def : InstRW<[A64FXWrite_ST3_WD_RR], (instregex "^ST3[WD]_I")>;
def A64FXWrite_ST4_BH : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 15;
let NumMicroOps = 5;
let ReleaseAtCycles = [16, 17];
let ResourceCycles = [16, 17];
}
def : InstRW<[A64FXWrite_ST4_BH], (instregex "^ST4[BH]")>;
def A64FXWrite_ST4_WD_RI : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 11;
let NumMicroOps = 4;
let ReleaseAtCycles = [4, 4];
let ResourceCycles = [4, 4];
}
def : InstRW<[A64FXWrite_ST4_WD_RI], (instregex "^ST4[WD]$")>;
def A64FXWrite_ST4_WD_RR : SchedWriteRes<[A64FXGI0, A64FXGI56]> {
let Latency = 12;
let NumMicroOps = 5;
let ReleaseAtCycles = [4, 5];
let ResourceCycles = [4, 5];
}
def : InstRW<[A64FXWrite_ST4_WD_RR], (instregex "^ST4[WD]_I")>;

10
llvm/lib/Target/AArch64/AArch64SchedCyclone.td
View File

@ -158,7 +158,7 @@ def : WriteRes<WriteI, [CyUnitI]>;
// EXAMPLE: ADDrs Xn, Xm LSL #imm
def : WriteRes<WriteISReg, [CyUnitIS]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// ADD with extended register operand is the same as shifted reg operand.
@ -166,7 +166,7 @@ def : WriteRes<WriteISReg, [CyUnitIS]> {
// EXAMPLE: ADDXre Xn, Xm, UXTB #1
def : WriteRes<WriteIEReg, [CyUnitIS]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// Variable shift and bitfield operations.
@ -209,14 +209,14 @@ def : WriteRes<WriteIM64, [CyUnitIM]> {
// SDIVW,UDIVW
def : WriteRes<WriteID32, [CyUnitID, CyUnitIntDiv]> {
let Latency = 10;
let ReleaseAtCycles = [2, 10];
let ResourceCycles = [2, 10];
}
// 64-bit divide takes 7-21 cycles. 13 cycles covers a 32-bit quotient.
// The ID pipe is consumed for 2 cycles: issue and writeback.
// SDIVX,UDIVX
def : WriteRes<WriteID64, [CyUnitID, CyUnitIntDiv]> {
let Latency = 13;
let ReleaseAtCycles = [2, 13];
let ResourceCycles = [2, 13];
}
//---
@ -555,7 +555,7 @@ def : InstRW<[CyWritePMUL], (instregex "PMULv", "PMULLv")>;
// TODO: Specialize FSQRT for longer latency.
def : WriteRes<WriteFDiv, [CyUnitVD, CyUnitFloatDiv]> {
let Latency = 17;
let ReleaseAtCycles = [2, 17];
let ResourceCycles = [2, 17];
}
def : InstRW<[CyWriteV4], (instregex "FRECPEv","FRECPXv","URECPEv","URSQRTEv")>;

60
llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
View File

@ -115,7 +115,7 @@ def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1;
def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; }
def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M3WriteAB : SchedWriteRes<[M3UnitALU,
M3UnitC]> { let Latency = 1;
let NumMicroOps = 2; }
@ -207,13 +207,13 @@ def : SchedAlias<WriteImm, M3WriteA1>;
// Divide and multiply instructions.
def : WriteRes<WriteID32, [M3UnitC,
M3UnitD]> { let Latency = 12;
let ReleaseAtCycles = [1, 12]; }
let ResourceCycles = [1, 12]; }
def : WriteRes<WriteID64, [M3UnitC,
M3UnitD]> { let Latency = 21;
let ReleaseAtCycles = [1, 21]; }
let ResourceCycles = [1, 21]; }
def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
// Miscellaneous instructions.
def : SchedAlias<WriteExtr, M3WriteAY>;
@ -238,7 +238,7 @@ def : SchedAlias<WriteSTIdx, M3WriteSB>;
def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; }
def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; }
def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12;
let ReleaseAtCycles = [12]; }
let ResourceCycles = [12]; }
def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; }
// FP miscellaneous instructions.
@ -302,19 +302,19 @@ def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF,
def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0,
M3UnitFDIV1]> { let Latency = 7;
let NumMicroOps = 2;
let ReleaseAtCycles = [8, 8]; }
let ResourceCycles = [8, 8]; }
def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0,
M3UnitFDIV1]> { let Latency = 12;
let NumMicroOps = 2;
let ReleaseAtCycles = [13, 13]; }
let ResourceCycles = [13, 13]; }
def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR,
M3UnitFSQR]> { let Latency = 18;
let NumMicroOps = 2;
let ReleaseAtCycles = [19, 19]; }
let ResourceCycles = [19, 19]; }
def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR,
M3UnitFSQR]> { let Latency = 25;
let NumMicroOps = 2;
let ReleaseAtCycles = [26, 26]; }
let ResourceCycles = [26, 26]; }
def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC,
M3UnitNMSC]> { let Latency = 5;
let NumMicroOps = 2; }
@ -325,16 +325,16 @@ def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; }
def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; }
def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; }
def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7;
let ReleaseAtCycles = [8]; }
let ResourceCycles = [8]; }
def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12;
let ReleaseAtCycles = [13]; }
let ResourceCycles = [13]; }
def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; }
def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; }
def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; }
def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25;
let ReleaseAtCycles = [26]; }
let ResourceCycles = [26]; }
def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; }
def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; }
def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; }
@ -363,50 +363,50 @@ def M3WriteVLDC : SchedWriteRes<[M3UnitL,
def M3WriteVLDD : SchedWriteRes<[M3UnitL,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 1]; }
let ResourceCycles = [2, 1]; }
def M3WriteVLDE : SchedWriteRes<[M3UnitL,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 1]; }
let ResourceCycles = [2, 1]; }
def M3WriteVLDF : SchedWriteRes<[M3UnitL,
M3UnitL]> { let Latency = 10;
let NumMicroOps = 2;
let ReleaseAtCycles = [5, 5]; }
let ResourceCycles = [5, 5]; }
def M3WriteVLDG : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 1, 1]; }
let ResourceCycles = [2, 1, 1]; }
def M3WriteVLDH : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 1, 1]; }
let ResourceCycles = [2, 1, 1]; }
def M3WriteVLDI : SchedWriteRes<[M3UnitL,
M3UnitL,
M3UnitL]> { let Latency = 12;
let NumMicroOps = 3;
let ReleaseAtCycles = [6, 6, 6]; }
let ResourceCycles = [6, 6, 6]; }
def M3WriteVLDJ : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [2, 1, 1, 1]; }
let ResourceCycles = [2, 1, 1, 1]; }
def M3WriteVLDK : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU,
M3UnitNALU]> { let Latency = 9;
let NumMicroOps = 5;
let ReleaseAtCycles = [4, 1, 1, 1, 1]; }
let ResourceCycles = [4, 1, 1, 1, 1]; }
def M3WriteVLDL : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
M3UnitL,
M3UnitNALU]> { let Latency = 6;
let NumMicroOps = 5;
let ReleaseAtCycles = [6, 1, 1, 6, 1]; }
let ResourceCycles = [6, 1, 1, 6, 1]; }
def M3WriteVLDM : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU,
@ -414,13 +414,13 @@ def M3WriteVLDM : SchedWriteRes<[M3UnitL,
M3UnitNALU,
M3UnitNALU]> { let Latency = 7;
let NumMicroOps = 6;
let ReleaseAtCycles = [6, 1, 1, 6, 1, 1]; }
let ResourceCycles = [6, 1, 1, 6, 1, 1]; }
def M3WriteVLDN : SchedWriteRes<[M3UnitL,
M3UnitL,
M3UnitL,
M3UnitL]> { let Latency = 14;
let NumMicroOps = 4;
let ReleaseAtCycles = [6, 6, 6, 6]; }
let ResourceCycles = [6, 6, 6, 6]; }
def M3WriteVSTA : WriteSequence<[WriteVST], 2>;
def M3WriteVSTB : WriteSequence<[WriteVST], 3>;
def M3WriteVSTC : WriteSequence<[WriteVST], 4>;
@ -429,7 +429,7 @@ def M3WriteVSTD : SchedWriteRes<[M3UnitS,
M3UnitS,
M3UnitFST]> { let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [1, 3, 1, 3]; }
let ResourceCycles = [1, 3, 1, 3]; }
def M3WriteVSTE : SchedWriteRes<[M3UnitS,
M3UnitFST,
M3UnitS,
@ -437,7 +437,7 @@ def M3WriteVSTE : SchedWriteRes<[M3UnitS,
M3UnitS,
M3UnitFST]> { let Latency = 8;
let NumMicroOps = 6;
let ReleaseAtCycles = [1, 3, 1, 3, 1, 3]; }
let ResourceCycles = [1, 3, 1, 3, 1, 3]; }
def M3WriteVSTF : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@ -446,7 +446,7 @@ def M3WriteVSTF : SchedWriteRes<[M3UnitNALU,
M3UnitS,
M3UnitFST]> { let Latency = 15;
let NumMicroOps = 7;
let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3]; }
let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; }
def M3WriteVSTG : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@ -457,14 +457,14 @@ def M3WriteVSTG : SchedWriteRes<[M3UnitNALU,
M3UnitS,
M3UnitFST]> { let Latency = 16;
let NumMicroOps = 9;
let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
def M3WriteVSTH : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
M3UnitS,
M3UnitFST]> { let Latency = 14;
let NumMicroOps = 5;
let ReleaseAtCycles = [1, 3, 3, 1, 3]; }
let ResourceCycles = [1, 3, 3, 1, 3]; }
def M3WriteVSTI : SchedWriteRes<[M3UnitNALU,
M3UnitFST,
M3UnitFST,
@ -475,7 +475,7 @@ def M3WriteVSTI : SchedWriteRes<[M3UnitNALU,
M3UnitS,
M3UnitFST]> { let Latency = 17;
let NumMicroOps = 9;
let ReleaseAtCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; }
// Special cases.
def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; }

66
llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
View File

@ -142,7 +142,7 @@ def M4WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
def M4WriteA1 : SchedWriteRes<[M4UnitALU]> { let Latency = 1; }
def M4WriteA2 : SchedWriteRes<[M4UnitALU]> { let Latency = 2; }
def M4WriteAA : SchedWriteRes<[M4UnitALU]> { let Latency = 2;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M4WriteAB : SchedWriteRes<[M4UnitALU,
M4UnitC]> { let Latency = 2;
let NumMicroOps = 2; }
@ -176,12 +176,12 @@ def M4WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M4WriteAC]>
def M4WriteC1 : SchedWriteRes<[M4UnitC]> { let Latency = 1; }
def M4WriteC3 : SchedWriteRes<[M4UnitC]> { let Latency = 3; }
def M4WriteCA : SchedWriteRes<[M4UnitC]> { let Latency = 4;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M4WriteD12 : SchedWriteRes<[M4UnitD]> { let Latency = 12;
let ReleaseAtCycles = [12]; }
let ResourceCycles = [12]; }
def M4WriteD21 : SchedWriteRes<[M4UnitD]> { let Latency = 21;
let ReleaseAtCycles = [21]; }
let ResourceCycles = [21]; }
def M4WriteE2 : SchedWriteRes<[M4UnitE]> { let Latency = 2; }
@ -265,22 +265,22 @@ def M4WriteNEONR : SchedWriteRes<[M4UnitFCVT0,
let NumMicroOps = 1; }
def M4WriteNEONV : SchedWriteRes<[M4UnitFDIV,
M4UnitFDIV]> { let Latency = 7;
let ReleaseAtCycles = [6, 6]; }
let ResourceCycles = [6, 6]; }
def M4WriteNEONVH : SchedWriteRes<[M4UnitFDIVH,
M4UnitFDIVH]> { let Latency = 7;
let ReleaseAtCycles = [6, 6]; }
let ResourceCycles = [6, 6]; }
def M4WriteNEONW : SchedWriteRes<[M4UnitFDIV,
M4UnitFDIV]> { let Latency = 12;
let ReleaseAtCycles = [9, 9]; }
let ResourceCycles = [9, 9]; }
def M4WriteNEONX : SchedWriteRes<[M4UnitFSQR,
M4UnitFSQR]> { let Latency = 8;
let ReleaseAtCycles = [7, 7]; }
let ResourceCycles = [7, 7]; }
def M4WriteNEONXH : SchedWriteRes<[M4UnitFSQRH,
M4UnitFSQRH]> { let Latency = 7;
let ReleaseAtCycles = [6, 6]; }
let ResourceCycles = [6, 6]; }
def M4WriteNEONY : SchedWriteRes<[M4UnitFSQR,
M4UnitFSQR]> { let Latency = 12;
let ReleaseAtCycles = [9, 9]; }
let ResourceCycles = [9, 9]; }
def M4WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M4WriteNEONO]>,
SchedVar<NoSchedPred, [M4WriteNEONN]>]>;
@ -298,11 +298,11 @@ def M4WriteFCVT4A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 4; }
def M4WriteFCVT6A : SchedWriteRes<[M4UnitFCVT0]> { let Latency = 6; }
def M4WriteFDIV7 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 7;
let ReleaseAtCycles = [6]; }
let ResourceCycles = [6]; }
def M4WriteFDIV7H : SchedWriteRes<[M4UnitFDIVH]> { let Latency = 7;
let ReleaseAtCycles = [6]; }
let ResourceCycles = [6]; }
def M4WriteFDIV12 : SchedWriteRes<[M4UnitFDIV]> { let Latency = 12;
let ReleaseAtCycles = [9]; }
let ResourceCycles = [9]; }
def M4WriteFMAC2H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 2; }
def M4WriteFMAC3H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 3; }
@ -312,11 +312,11 @@ def M4WriteFMAC4H : SchedWriteRes<[M4UnitFMACH]> { let Latency = 4; }
def M4WriteFMAC5 : SchedWriteRes<[M4UnitFMAC]> { let Latency = 5; }
def M4WriteFSQR7H : SchedWriteRes<[M4UnitFSQRH]> { let Latency = 7;
let ReleaseAtCycles = [6]; }
let ResourceCycles = [6]; }
def M4WriteFSQR8 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 8;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def M4WriteFSQR12 : SchedWriteRes<[M4UnitFSQR]> { let Latency = 12;
let ReleaseAtCycles = [9]; }
let ResourceCycles = [9]; }
def M4WriteNALU1 : SchedWriteRes<[M4UnitNALU]> { let Latency = 1; }
def M4WriteNALU1H : SchedWriteRes<[M4UnitNALUH]> { let Latency = 1; }
@ -339,16 +339,16 @@ def M4WriteNSHF1 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1; }
def M4WriteNSHF1H : SchedWriteRes<[M4UnitNSHFH]> { let Latency = 1; }
def M4WriteNSHF3 : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3; }
def M4WriteNSHFA : SchedWriteRes<[M4UnitNSHF]> { let Latency = 1;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M4WriteNSHFB : SchedWriteRes<[M4UnitNSHF]> { let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M4WriteNSHFC : SchedWriteRes<[M4UnitNSHF]> { let Latency = 3;
let NumMicroOps = 3;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def M4WriteNSHFD : SchedWriteRes<[M4UnitNSHF]> { let Latency = 4;
let NumMicroOps = 4;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def M4WriteNSHT1 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 1; }
def M4WriteNSHT2 : SchedWriteRes<[M4UnitNSHT]> { let Latency = 2; }
@ -370,41 +370,41 @@ def M4WriteVLDC : SchedWriteRes<[M4UnitL,
def M4WriteVLDD : SchedWriteRes<[M4UnitL,
M4UnitNSHF]> { let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 1]; }
let ResourceCycles = [2, 1]; }
def M4WriteVLDF : SchedWriteRes<[M4UnitL,
M4UnitL]> { let Latency = 10;
let NumMicroOps = 2;
let ReleaseAtCycles = [3, 3]; }
let ResourceCycles = [3, 3]; }
def M4WriteVLDG : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 6;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 1, 1]; }
let ResourceCycles = [2, 1, 1]; }
def M4WriteVLDI : SchedWriteRes<[M4UnitL,
M4UnitL,
M4UnitL]> { let Latency = 12;
let NumMicroOps = 3;
let ReleaseAtCycles = [3, 3, 3]; }
let ResourceCycles = [3, 3, 3]; }
def M4WriteVLDJ : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [3, 1, 1, 1]; }
let ResourceCycles = [3, 1, 1, 1]; }
def M4WriteVLDK : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 5;
let ReleaseAtCycles = [3, 1, 1, 1, 1]; }
let ResourceCycles = [3, 1, 1, 1, 1]; }
def M4WriteVLDL : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
M4UnitL,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 5;
let ReleaseAtCycles = [3, 1, 1, 6, 1]; }
let ResourceCycles = [3, 1, 1, 6, 1]; }
def M4WriteVLDM : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF,
@ -412,13 +412,13 @@ def M4WriteVLDM : SchedWriteRes<[M4UnitL,
M4UnitNSHF,
M4UnitNSHF]> { let Latency = 7;
let NumMicroOps = 6;
let ReleaseAtCycles = [3, 1, 1, 3, 1, 1]; }
let ResourceCycles = [3, 1, 1, 3, 1, 1]; }
def M4WriteVLDN : SchedWriteRes<[M4UnitL,
M4UnitL,
M4UnitL,
M4UnitL]> { let Latency = 14;
let NumMicroOps = 4;
let ReleaseAtCycles = [3, 3, 3, 3]; }
let ResourceCycles = [3, 3, 3, 3]; }
def M4WriteVST1 : SchedWriteRes<[M4UnitS,
M4UnitFST]> { let Latency = 1;
@ -439,7 +439,7 @@ def M4WriteVSTF : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 4;
let NumMicroOps = 4;
let ReleaseAtCycles = [1, 2, 1, 2, 1]; }
let ResourceCycles = [1, 2, 1, 2, 1]; }
def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF,
@ -450,7 +450,7 @@ def M4WriteVSTG : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 5;
let NumMicroOps = 6;
let ReleaseAtCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
let ResourceCycles = [1, 1, 1, 2, 1, 2, 1, 2, 1]; }
def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF,
M4UnitNSHF,
M4UnitNSHF,
@ -464,7 +464,7 @@ def M4WriteVSTI : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
def M4WriteVSTJ : SchedWriteRes<[M4UnitA,
M4UnitS,
M4UnitFST,
@ -482,7 +482,7 @@ def M4WriteVSTL : SchedWriteRes<[M4UnitNSHF,
M4UnitS,
M4UnitFST]> { let Latency = 4;
let NumMicroOps = 4;
let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
def M4WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M4WriteVSTK]>,
SchedVar<NoSchedPred, [WriteVST]>]>;

58
llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
View File

@ -142,9 +142,9 @@ def M5WriteZ4 : SchedWriteRes<[]> { let Latency = 4;
def M5WriteA1W : SchedWriteRes<[M5UnitAW]> { let Latency = 1; }
def M5WriteA1X : SchedWriteRes<[M5UnitAX]> { let Latency = 1; }
def M5WriteAAW : SchedWriteRes<[M5UnitAW]> { let Latency = 2;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M5WriteAAX : SchedWriteRes<[M5UnitAX]> { let Latency = 2;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M5WriteAB : SchedWriteRes<[M5UnitAX,
M5UnitC,
M5UnitE]> { let Latency = 2;
@ -194,12 +194,12 @@ def M5WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M5WriteAC]>
def M5WriteC1 : SchedWriteRes<[M5UnitC]> { let Latency = 1; }
def M5WriteC2 : SchedWriteRes<[M5UnitC]> { let Latency = 2; }
def M5WriteCA : SchedWriteRes<[M5UnitC]> { let Latency = 3;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M5WriteD10 : SchedWriteRes<[M5UnitD]> { let Latency = 10;
let ReleaseAtCycles = [10]; }
let ResourceCycles = [10]; }
def M5WriteD16 : SchedWriteRes<[M5UnitD]> { let Latency = 16;
let ReleaseAtCycles = [16]; }
let ResourceCycles = [16]; }
def M5WriteF2 : SchedWriteRes<[M5UnitF]> { let Latency = 2; }
@ -228,22 +228,22 @@ def M5WriteLFW : SchedWriteRes<[M5UnitAW,
M5UnitAW,
M5UnitL]> { let Latency = 15;
let NumMicroOps = 6;
let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
let ResourceCycles = [1, 1, 1, 1, 15]; }
def M5WriteLFX : SchedWriteRes<[M5UnitAX,
M5UnitAX,
M5UnitAX,
M5UnitAX,
M5UnitL]> { let Latency = 15;
let NumMicroOps = 6;
let ReleaseAtCycles = [1, 1, 1, 1, 15]; }
let ResourceCycles = [1, 1, 1, 1, 15]; }
def M5WriteLGW : SchedWriteRes<[M5UnitAW,
M5UnitL]> { let Latency = 13;
let NumMicroOps = 1;
let ReleaseAtCycles = [1, 13]; }
let ResourceCycles = [1, 13]; }
def M5WriteLGX : SchedWriteRes<[M5UnitAX,
M5UnitL]> { let Latency = 13;
let NumMicroOps = 1;
let ReleaseAtCycles = [1, 13]; }
let ResourceCycles = [1, 13]; }
def M5WriteLH : SchedWriteRes<[]> { let Latency = 6;
let NumMicroOps = 0; }
def M5WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteL5]>,
@ -282,12 +282,12 @@ def M5WriteNEONK : SchedWriteRes<[M5UnitNSHF,
def M5WriteNEONN : SchedWriteRes<[M5UnitNMSC,
M5UnitNMSC]> { let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [7, 7]; }
let ResourceCycles = [7, 7]; }
def M5WriteNEONO : SchedWriteRes<[M5UnitNMSC,
M5UnitNMSC,
M5UnitNMSC]> { let Latency = 8;
let NumMicroOps = 3;
let ReleaseAtCycles = [10, 10, 10]; }
let ResourceCycles = [10, 10, 10]; }
def M5WriteNEONP : SchedWriteRes<[M5UnitNSHF,
M5UnitS0,
M5UnitFCVT]> { let Latency = 7;
@ -297,19 +297,19 @@ def M5WriteNEONQ : SchedWriteRes<[M5UnitNMSC,
let NumMicroOps = 1; }
def M5WriteNEONU : SchedWriteRes<[M5UnitFSQR,
M5UnitFSQR]> { let Latency = 7;
let ReleaseAtCycles = [4, 4]; }
let ResourceCycles = [4, 4]; }
def M5WriteNEONV : SchedWriteRes<[M5UnitFDIV,
M5UnitFDIV]> { let Latency = 7;
let ReleaseAtCycles = [6, 6]; }
let ResourceCycles = [6, 6]; }
def M5WriteNEONW : SchedWriteRes<[M5UnitFDIV,
M5UnitFDIV]> { let Latency = 12;
let ReleaseAtCycles = [9, 9]; }
let ResourceCycles = [9, 9]; }
def M5WriteNEONX : SchedWriteRes<[M5UnitFSQR,
M5UnitFSQR]> { let Latency = 8;
let ReleaseAtCycles = [5, 5]; }
let ResourceCycles = [5, 5]; }
def M5WriteNEONY : SchedWriteRes<[M5UnitFSQR,
M5UnitFSQR]> { let Latency = 12;
let ReleaseAtCycles = [9, 9]; }
let ResourceCycles = [9, 9]; }
def M5WriteNEONZ : SchedWriteVariant<[SchedVar<ExynosQFormPred, [M5WriteNEONO]>,
SchedVar<NoSchedPred, [M5WriteNEONN]>]>;
@ -330,24 +330,24 @@ def M5WriteFCVTC : SchedWriteRes<[M5UnitFCVT,
let NumMicroOps = 1; }
def M5WriteFDIV5 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M5WriteFDIV7 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 7;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def M5WriteFDIV12 : SchedWriteRes<[M5UnitFDIV]> { let Latency = 12;
let ReleaseAtCycles = [9]; }
let ResourceCycles = [9]; }
def M5WriteFMAC3 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 3; }
def M5WriteFMAC4 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 4; }
def M5WriteFMAC5 : SchedWriteRes<[M5UnitFMAC]> { let Latency = 5; }
def M5WriteFSQR5 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 5;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def M5WriteFSQR7 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 7;
let ReleaseAtCycles = [4]; }
let ResourceCycles = [4]; }
def M5WriteFSQR8 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 8;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def M5WriteFSQR12 : SchedWriteRes<[M5UnitFSQR]> { let Latency = 12;
let ReleaseAtCycles = [9]; }
let ResourceCycles = [9]; }
def M5WriteNALU1 : SchedWriteRes<[M5UnitNALU]> { let Latency = 1; }
def M5WriteNALU2 : SchedWriteRes<[M5UnitNALU]> { let Latency = 2; }
@ -396,16 +396,16 @@ def M5WriteVLDC : SchedWriteRes<[M5UnitL,
def M5WriteVLDD : SchedWriteRes<[M5UnitL,
M5UnitNSHF]> { let Latency = 7;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 1]; }
let ResourceCycles = [2, 1]; }
def M5WriteVLDF : SchedWriteRes<[M5UnitL,
M5UnitL]> { let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [6, 5]; }
let ResourceCycles = [6, 5]; }
def M5WriteVLDG : SchedWriteRes<[M5UnitL,
M5UnitNSHF,
M5UnitNSHF]> { let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 1, 1]; }
let ResourceCycles = [2, 1, 1]; }
def M5WriteVLDI : SchedWriteRes<[M5UnitL,
M5UnitL,
M5UnitL]> { let Latency = 13;
@ -439,7 +439,7 @@ def M5WriteVLDN : SchedWriteRes<[M5UnitL,
M5UnitL,
M5UnitL]> { let Latency = 15;
let NumMicroOps = 4;
let ReleaseAtCycles = [2, 2, 2, 2]; }
let ResourceCycles = [2, 2, 2, 2]; }
def M5WriteVST1 : SchedWriteRes<[M5UnitS,
M5UnitFST]> { let Latency = 1;
@ -501,7 +501,7 @@ def M5WriteVSTI : SchedWriteRes<[M5UnitNSHF,
M5UnitS,
M5UnitFST]> { let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
let ResourceCycles = [1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1]; }
def M5WriteVSTJ : SchedWriteRes<[M5UnitA,
M5UnitS0,
M5UnitFST]> { let Latency = 1;
@ -517,7 +517,7 @@ def M5WriteVSTL : SchedWriteRes<[M5UnitNSHF,
M5UnitS,
M5UnitFST]> { let Latency = 4;
let NumMicroOps = 4;
let ReleaseAtCycles = [1, 1, 2, 1, 2, 1]; }
let ResourceCycles = [1, 1, 2, 1, 2, 1]; }
def M5WriteVSTY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M5WriteVSTK]>,
SchedVar<NoSchedPred, [WriteVST]>]>;

4
llvm/lib/Target/AArch64/AArch64SchedFalkorDetails.td
View File

@ -210,13 +210,13 @@ def FalkorWr_1Z_1XY_0cyc : SchedWriteRes<[FalkorUnitZ, FalkorUnitXY]> {
def FalkorWr_1X_1Z_8cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 8];
let ResourceCycles = [2, 8];
}
def FalkorWr_1X_1Z_11cyc : SchedWriteRes<[FalkorUnitX, FalkorUnitZ]> {
let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [2, 11];
let ResourceCycles = [2, 11];
}
def FalkorWr_1LD_1Z_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitZ]> {

18
llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
View File

@ -84,13 +84,13 @@ def N1Write_1c_1I : SchedWriteRes<[N1UnitI]> { let Latency = 1; }
def N1Write_2c_1M : SchedWriteRes<[N1UnitM]> { let Latency = 2; }
def N1Write_3c_1M : SchedWriteRes<[N1UnitM]> { let Latency = 3; }
def N1Write_4c3_1M : SchedWriteRes<[N1UnitM]> { let Latency = 4;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def N1Write_5c3_1M : SchedWriteRes<[N1UnitM]> { let Latency = 5;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def N1Write_12c5_1M : SchedWriteRes<[N1UnitM]> { let Latency = 12;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def N1Write_20c5_1M : SchedWriteRes<[N1UnitM]> { let Latency = 20;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def N1Write_4c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 4; }
def N1Write_5c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 5; }
def N1Write_7c_1L : SchedWriteRes<[N1UnitL]> { let Latency = 7; }
@ -102,15 +102,15 @@ def N1Write_2c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 2; }
def N1Write_3c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 3; }
def N1Write_4c_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 4; }
def N1Write_7c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 7;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def N1Write_10c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 10;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def N1Write_13c10_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 13;
let ReleaseAtCycles = [10]; }
let ResourceCycles = [10]; }
def N1Write_15c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 15;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def N1Write_17c7_1V0 : SchedWriteRes<[N1UnitV0]> { let Latency = 17;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def N1Write_2c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 2; }
def N1Write_3c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 3; }
def N1Write_4c_1V1 : SchedWriteRes<[N1UnitV1]> { let Latency = 4; }

20
llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
View File

@ -82,15 +82,15 @@ def N2Write_1cyc_1L01 : SchedWriteRes<[N2UnitL01]> { let Latency = 1; }
def N2Write_2cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 2; }
def N2Write_3cyc_1M : SchedWriteRes<[N2UnitM]> { let Latency = 3; }
def N2Write_2cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 2;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def N2Write_3cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 3;
let ReleaseAtCycles = [3]; }
let ResourceCycles = [3]; }
def N2Write_5cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 5;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def N2Write_12cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 12;
let ReleaseAtCycles = [12]; }
let ResourceCycles = [12]; }
def N2Write_20cyc_1M0 : SchedWriteRes<[N2UnitM0]> { let Latency = 20;
let ReleaseAtCycles = [20]; }
let ResourceCycles = [20]; }
def N2Write_4cyc_1L : SchedWriteRes<[N2UnitL]> { let Latency = 4; }
def N2Write_6cyc_1L : SchedWriteRes<[N2UnitL]> { let Latency = 6; }
def N2Write_2cyc_1V : SchedWriteRes<[N2UnitV]> { let Latency = 2; }
@ -102,7 +102,7 @@ def N2Write_2cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 2; }
def N2Write_3cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 3; }
def N2Write_4cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 4; }
def N2Write_7cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 7;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def N2Write_9cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 9; }
def N2Write_10cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 10; }
def N2Write_12cyc_1V0 : SchedWriteRes<[N2UnitV0]> { let Latency = 12; }
@ -188,25 +188,25 @@ def N2Write_4cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
def N2Write_10cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 10;
let NumMicroOps = 2;
let ReleaseAtCycles = [5, 5];
let ResourceCycles = [5, 5];
}
def N2Write_13cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 13;
let NumMicroOps = 2;
let ReleaseAtCycles = [6, 7];
let ResourceCycles = [6, 7];
}
def N2Write_15cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 15;
let NumMicroOps = 2;
let ReleaseAtCycles = [7, 8];
let ResourceCycles = [7, 8];
}
def N2Write_16cyc_2V0 : SchedWriteRes<[N2UnitV0, N2UnitV0]> {
let Latency = 16;
let NumMicroOps = 2;
let ReleaseAtCycles = [8, 8];
let ResourceCycles = [8, 8];
}
def N2Write_4cyc_2V : SchedWriteRes<[N2UnitV, N2UnitV]> {

28
llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
View File

@ -111,9 +111,9 @@ def V1Write_2c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 2; }
def V1Write_3c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 3; }
def V1Write_5c_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 5; }
def V1Write_12c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 12;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def V1Write_20c5_1M0 : SchedWriteRes<[V1UnitM0]> { let Latency = 20;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def V1Write_2c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 2; }
def V1Write_3c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 3; }
def V1Write_4c_1V : SchedWriteRes<[V1UnitV]> { let Latency = 4; }
@ -123,17 +123,17 @@ def V1Write_3c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 3; }
def V1Write_4c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 4; }
def V1Write_6c_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 6; }
def V1Write_10c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 10;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_12c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 12;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_13c10_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 13;
let ReleaseAtCycles = [10]; }
let ResourceCycles = [10]; }
def V1Write_15c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 15;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_16c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 16;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_20c7_1V0 : SchedWriteRes<[V1UnitV0]> { let Latency = 20;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_2c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 2; }
def V1Write_3c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 3; }
def V1Write_4c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 4; }
@ -141,17 +141,17 @@ def V1Write_5c_1V01 : SchedWriteRes<[V1UnitV01]> { let Latency = 5; }
def V1Write_3c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 3; }
def V1Write_4c_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 4; }
def V1Write_7c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 7;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_10c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 10;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_13c5_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;
let ReleaseAtCycles = [5]; }
let ResourceCycles = [5]; }
def V1Write_13c11_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 13;
let ReleaseAtCycles = [11]; }
let ResourceCycles = [11]; }
def V1Write_15c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 15;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_16c7_1V02 : SchedWriteRes<[V1UnitV02]> { let Latency = 16;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V1Write_2c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 2; }
def V1Write_3c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 3; }
def V1Write_4c_1V1 : SchedWriteRes<[V1UnitV1]> { let Latency = 4; }

48
llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
View File

@ -102,9 +102,9 @@ def V2Write_2cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 2; }
def V2Write_3cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 3; }
def V2Write_5cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 5; }
def V2Write_12cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 12;
let ReleaseAtCycles = [12]; }
let ResourceCycles = [12]; }
def V2Write_20cyc_1M0 : SchedWriteRes<[V2UnitM0]> { let Latency = 20;
let ReleaseAtCycles = [20]; }
let ResourceCycles = [20]; }
def V2Write_4cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 4; }
def V2Write_6cyc_1L : SchedWriteRes<[V2UnitL]> { let Latency = 6; }
def V2Write_2cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 2; }
@ -113,7 +113,7 @@ def V2Write_2cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 2; }
def V2Write_2cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 2; }
def V2Write_3cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 3; }
def V2Write_3cyc_1V01 : SchedWriteRes<[V2UnitV01]> { let Latency = 3;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def V2Write_3cyc_1V23 : SchedWriteRes<[V2UnitV23]> { let Latency = 3; }
def V2Write_4cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 4; }
def V2Write_5cyc_1V : SchedWriteRes<[V2UnitV]> { let Latency = 5; }
@ -124,26 +124,26 @@ def V2Write_3cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 3; }
def V2Write_4cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 4; }
def V2Write_4cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 4; }
def V2Write_7cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 7;
let ReleaseAtCycles = [7]; }
let ResourceCycles = [7]; }
def V2Write_7cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 7;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def V2Write_9cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 9; }
def V2Write_9cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 9;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def V2Write_10cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 10; }
def V2Write_10cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 10;
let ReleaseAtCycles = [2]; }
let ResourceCycles = [2]; }
def V2Write_12cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 12;
let ReleaseAtCycles = [11]; }
let ResourceCycles = [11]; }
def V2Write_13cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 13; }
def V2Write_15cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 15; }
def V2Write_15cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 15;
let ReleaseAtCycles = [8]; }
let ResourceCycles = [8]; }
def V2Write_16cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 16; }
def V2Write_16cyc_1V02 : SchedWriteRes<[V2UnitV02]> { let Latency = 16;
let ReleaseAtCycles = [8]; }
let ResourceCycles = [8]; }
def V2Write_20cyc_1V0 : SchedWriteRes<[V2UnitV0]> { let Latency = 20;
let ReleaseAtCycles = [20]; }
let ResourceCycles = [20]; }
def V2Write_2cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 2; }
def V2Write_2cyc_1V13 : SchedWriteRes<[V2UnitV13]> { let Latency = 2; }
def V2Write_3cyc_1V1 : SchedWriteRes<[V2UnitV1]> { let Latency = 3; }
@ -1054,19 +1054,19 @@ def V2Rd_ZBFMAL : SchedReadAdvance<3, [V2Wr_ZBFMAL]>;
//===----------------------------------------------------------------------===//
// Define types with long resource cycles (rc)
def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ReleaseAtCycles = [ 5]; }
def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ReleaseAtCycles = [ 7]; }
def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 5]; }
def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ReleaseAtCycles = [10]; }
def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ReleaseAtCycles = [ 9]; }
def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ReleaseAtCycles = [12]; }
def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [12]; }
def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ReleaseAtCycles = [13]; }
def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ReleaseAtCycles = [14]; }
def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ReleaseAtCycles = [15]; }
def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ReleaseAtCycles = [14]; }
def V2Write_6cyc_1V1_5rc : SchedWriteRes<[V2UnitV1]> { let Latency = 6; let ResourceCycles = [ 5]; }
def V2Write_7cyc_1V02_7rc : SchedWriteRes<[V2UnitV02]> { let Latency = 7; let ResourceCycles = [ 7]; }
def V2Write_10cyc_1V02_5rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 5]; }
def V2Write_10cyc_1V02_9rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [ 9]; }
def V2Write_10cyc_1V02_10rc : SchedWriteRes<[V2UnitV02]> { let Latency = 10; let ResourceCycles = [10]; }
def V2Write_10cyc_1V0_9rc : SchedWriteRes<[V2UnitV0]> { let Latency = 10; let ResourceCycles = [ 9]; }
def V2Write_10cyc_1V1_9rc : SchedWriteRes<[V2UnitV1]> { let Latency = 10; let ResourceCycles = [ 9]; }
def V2Write_13cyc_1V0_12rc : SchedWriteRes<[V2UnitV0]> { let Latency = 13; let ResourceCycles = [12]; }
def V2Write_13cyc_1V02_12rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [12]; }
def V2Write_13cyc_1V02_13rc : SchedWriteRes<[V2UnitV02]> { let Latency = 13; let ResourceCycles = [13]; }
def V2Write_15cyc_1V02_14rc : SchedWriteRes<[V2UnitV02]> { let Latency = 15; let ResourceCycles = [14]; }
def V2Write_16cyc_1V02_15rc : SchedWriteRes<[V2UnitV02]> { let Latency = 16; let ResourceCycles = [15]; }
def V2Write_16cyc_1V0_14rc : SchedWriteRes<[V2UnitV0]> { let Latency = 16; let ResourceCycles = [14]; }
// Miscellaneous
// -----------------------------------------------------------------------------

28
llvm/lib/Target/AArch64/AArch64SchedTSV110.td
View File

@ -66,9 +66,9 @@ def : WriteRes<WriteIS, [TSV110UnitALUAB]> { let Latency = 1; }
// Integer Mul/MAC/Div
def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
let ReleaseAtCycles = [12]; }
let ResourceCycles = [12]; }
def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
let ReleaseAtCycles = [20]; }
let ResourceCycles = [20]; }
def : WriteRes<WriteIM32, [TSV110UnitMDU]> { let Latency = 3; }
def : WriteRes<WriteIM64, [TSV110UnitMDU]> { let Latency = 4; }
@ -94,7 +94,7 @@ def : WriteRes<WriteFImm, [TSV110UnitF]> { let Latency = 2; }
def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }
// FP Div, Sqrt
def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
def : WriteRes<WriteFDiv, [TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
def : WriteRes<WriteVd, [TSV110UnitF]> { let Latency = 4; }
def : WriteRes<WriteVq, [TSV110UnitF]> { let Latency = 4; }
@ -146,7 +146,7 @@ def TSV110Wr_1cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 1; }
def TSV110Wr_1cyc_1ALUAB : SchedWriteRes<[TSV110UnitALUAB]> { let Latency = 1; }
def TSV110Wr_1cyc_1LdSt : SchedWriteRes<[TSV110UnitLd0St]> { let Latency = 1; }
def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ReleaseAtCycles = [2]; }
def TSV110Wr_2cyc_1AB : SchedWriteRes<[TSV110UnitAB]> { let Latency = 2; let ResourceCycles = [2]; }
def TSV110Wr_2cyc_1ALU : SchedWriteRes<[TSV110UnitALU]> { let Latency = 2; }
def TSV110Wr_2cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 2; }
def TSV110Wr_2cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 2; }
@ -172,25 +172,25 @@ def TSV110Wr_7cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 7; }
def TSV110Wr_8cyc_1F : SchedWriteRes<[TSV110UnitF]> { let Latency = 8; }
def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ReleaseAtCycles = [11]; }
def TSV110Wr_11cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 11; let ResourceCycles = [11]; }
def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ReleaseAtCycles = [12]; }
def TSV110Wr_12cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 12; let ResourceCycles = [12]; }
def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ReleaseAtCycles = [17]; }
def TSV110Wr_17cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 17; let ResourceCycles = [17]; }
def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ReleaseAtCycles = [18]; }
def TSV110Wr_18cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 18; let ResourceCycles = [18]; }
def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ReleaseAtCycles = [20]; }
def TSV110Wr_20cyc_1MDU : SchedWriteRes<[TSV110UnitMDU]> { let Latency = 20; let ResourceCycles = [20]; }
def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ReleaseAtCycles = [24]; }
def TSV110Wr_24cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 24; let ResourceCycles = [24]; }
def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ReleaseAtCycles = [31]; }
def TSV110Wr_31cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 31; let ResourceCycles = [31]; }
def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ReleaseAtCycles = [36]; }
def TSV110Wr_36cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 36; let ResourceCycles = [36]; }
def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ReleaseAtCycles = [38]; }
def TSV110Wr_38cyc_1FSU1 : SchedWriteRes<[TSV110UnitFSU1]> { let Latency = 38; let ResourceCycles = [38]; }
def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ReleaseAtCycles = [64]; }
def TSV110Wr_64cyc_1FSU2 : SchedWriteRes<[TSV110UnitFSU2]> { let Latency = 64; let ResourceCycles = [64]; }
//===----------------------------------------------------------------------===//
// Define Generic 2 micro-op types

34
llvm/lib/Target/AArch64/AArch64SchedThunderX.td
View File

@ -59,23 +59,23 @@ def : WriteRes<WriteExtr, [THXT8XUnitALU]> { let Latency = 2; }
// MAC
def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
// Div
def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
let Latency = 12;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
}
def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
let Latency = 14;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
// Load
@ -86,32 +86,32 @@ def : WriteRes<WriteLDHi, [THXT8XUnitLdSt]> { let Latency = 3; }
// Vector Load
def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
let Latency = 8;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def THXT8XWriteVLD1 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 6;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def THXT8XWriteVLD2 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 11;
let ReleaseAtCycles = [7];
let ResourceCycles = [7];
}
def THXT8XWriteVLD3 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 12;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def THXT8XWriteVLD4 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 13;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def THXT8XWriteVLD5 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 13;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
// Pre/Post Indexing
@ -129,12 +129,12 @@ def THXT8XWriteVST1 : SchedWriteRes<[THXT8XUnitLdSt]>;
def THXT8XWriteVST2 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 10;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def THXT8XWriteVST3 : SchedWriteRes<[THXT8XUnitLdSt]> {
let Latency = 11;
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
}
def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
@ -162,29 +162,29 @@ def : WriteRes<WriteVq, [THXT8XUnitFPALU]> { let Latency = 6; }
def : WriteRes<WriteFMul, [THXT8XUnitFPMDS]> { let Latency = 6; }
def : WriteRes<WriteFDiv, [THXT8XUnitFPMDS]> {
let Latency = 22;
let ReleaseAtCycles = [19];
let ResourceCycles = [19];
}
def THXT8XWriteFMAC : SchedWriteRes<[THXT8XUnitFPMDS]> { let Latency = 10; }
def THXT8XWriteFDivSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 12;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def THXT8XWriteFDivDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 22;
let ReleaseAtCycles = [19];
let ResourceCycles = [19];
}
def THXT8XWriteFSqrtSP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 17;
let ReleaseAtCycles = [14];
let ResourceCycles = [14];
}
def THXT8XWriteFSqrtDP : SchedWriteRes<[THXT8XUnitFPMDS]> {
let Latency = 31;
let ReleaseAtCycles = [28];
let ResourceCycles = [28];
}
//===----------------------------------------------------------------------===//

40
llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
View File

@ -113,14 +113,14 @@ def THX2T99Write_4Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
// 23 cycles on I1.
def THX2T99Write_23Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
let Latency = 23;
let ReleaseAtCycles = [13, 23];
let ResourceCycles = [13, 23];
let NumMicroOps = 4;
}
// 39 cycles on I1.
def THX2T99Write_39Cyc_I1 : SchedWriteRes<[THX2T99I1]> {
let Latency = 39;
let ReleaseAtCycles = [13, 39];
let ResourceCycles = [13, 39];
let NumMicroOps = 4;
}
@ -200,14 +200,14 @@ def THX2T99Write_10Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
def THX2T99Write_16Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let NumMicroOps = 3;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
// 23 cycles on F0 or F1.
def THX2T99Write_23Cyc_F01 : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let NumMicroOps = 3;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
// 1 cycles on LS0 or LS1.
@ -418,7 +418,7 @@ def : InstRW<[THX2T99Write_1Cyc_I2],
// Address generation
def : WriteRes<WriteI, [THX2T99I012]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -440,7 +440,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX2T99I012]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
@ -459,7 +459,7 @@ def : InstRW<[WriteISReg],
def : WriteRes<WriteIEReg, [THX2T99I012]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -502,14 +502,14 @@ def : WriteRes<WriteIS, [THX2T99I012]> {
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX2T99I1]> {
let Latency = 39;
let ReleaseAtCycles = [39];
let ResourceCycles = [39];
let NumMicroOps = 4;
}
// Divide, X-form
def : WriteRes<WriteID64, [THX2T99I1]> {
let Latency = 23;
let ReleaseAtCycles = [23];
let ResourceCycles = [23];
let NumMicroOps = 4;
}
@ -1110,36 +1110,36 @@ def : WriteRes<WriteFCmp, [THX2T99F01]> {
// FP Mul, Div, Sqrt
def : WriteRes<WriteFDiv, [THX2T99F01]> {
let Latency = 22;
let ReleaseAtCycles = [19];
let ResourceCycles = [19];
}
def THX2T99XWriteFDiv : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX2T99XWriteFDivSP : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX2T99XWriteFDivDP : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 4;
}
def THX2T99XWriteFSqrtSP : SchedWriteRes<[THX2T99F01]> {
let Latency = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX2T99XWriteFSqrtDP : SchedWriteRes<[THX2T99F01]> {
let Latency = 23;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 4;
}
@ -1163,19 +1163,19 @@ def : InstRW<[THX2T99Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply accumulate
def : WriteRes<WriteFMul, [THX2T99F01]> {
let Latency = 6;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX2T99XWriteFMul : SchedWriteRes<[THX2T99F01]> {
let Latency = 6;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX2T99XWriteFMulAcc : SchedWriteRes<[THX2T99F01]> {
let Latency = 6;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 3;
}
@ -1254,12 +1254,12 @@ def : InstRW<[THX2T99Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
def : WriteRes<WriteVd, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def : WriteRes<WriteVq, [THX2T99F01]> {
let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
// ASIMD arith, reduce, 4H/4S

48
llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
View File

@ -143,14 +143,14 @@ def THX3T110Write_7Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
// 23 cycles on I1.
def THX3T110Write_23Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
let Latency = 23;
let ReleaseAtCycles = [13, 23];
let ResourceCycles = [13, 23];
let NumMicroOps = 4;
}
// 39 cycles on I1.
def THX3T110Write_39Cyc_I1 : SchedWriteRes<[THX3T110I1]> {
let Latency = 39;
let ReleaseAtCycles = [13, 39];
let ResourceCycles = [13, 39];
let NumMicroOps = 4;
}
@ -278,14 +278,14 @@ def THX3T110Write_10Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
def THX3T110Write_16Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let NumMicroOps = 3;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
// 23 cycles on F0/F1/F2/F3.
def THX3T110Write_23Cyc_F01 : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let NumMicroOps = 3;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
// 1 cycle on LS0/LS1.
@ -304,7 +304,7 @@ def THX3T110Write_2Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// 5 cycles on LS0/LS1.
@ -326,7 +326,7 @@ def THX3T110Write_6Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
let ReleaseAtCycles = [4, 5];
let ResourceCycles = [4, 5];
}
// 4 + 8 cycles on LS0/LS1.
@ -336,7 +336,7 @@ def THX3T110Write_4_5Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
def THX3T110Write_4_8Cyc_LS01 : SchedWriteRes<[THX3T110LS]> {
let Latency = 4;
let NumMicroOps = 2;
let ReleaseAtCycles = [4, 8];
let ResourceCycles = [4, 8];
}
// 11 cycles on LS0/LS1 and I1.
@ -607,7 +607,7 @@ def THX3T110Write_3_4Cyc_F23_F0123 :
SchedWriteRes<[THX3T110FP23, THX3T110FP0123]> {
let Latency = 3;
let NumMicroOps = 2;
let ReleaseAtCycles = [3, 4];
let ResourceCycles = [3, 4];
}
@ -678,7 +678,7 @@ def : InstRW<[THX3T110Write_1Cyc_I23],
// Address generation
def : WriteRes<WriteI, [THX3T110I0123]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -700,7 +700,7 @@ def : InstRW<[WriteI], (instrs COPY)>;
// ALU, extend and/or shift
def : WriteRes<WriteISReg, [THX3T110I0123]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
@ -719,7 +719,7 @@ def : InstRW<[WriteISReg],
def : WriteRes<WriteIEReg, [THX3T110I0123]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -762,14 +762,14 @@ def : WriteRes<WriteIS, [THX3T110I0123]> {
// Latency range of 13-23/13-39.
def : WriteRes<WriteID32, [THX3T110I1]> {
let Latency = 39;
let ReleaseAtCycles = [39];
let ResourceCycles = [39];
let NumMicroOps = 4;
}
// Divide, X-form
def : WriteRes<WriteID64, [THX3T110I1]> {
let Latency = 23;
let ReleaseAtCycles = [23];
let ResourceCycles = [23];
let NumMicroOps = 4;
}
@ -1218,36 +1218,36 @@ def : WriteRes<WriteFCmp, [THX3T110FP0123]> {
// FP Mul, Div, Sqrt
def : WriteRes<WriteFDiv, [THX3T110FP0123]> {
let Latency = 22;
let ReleaseAtCycles = [19];
let ResourceCycles = [19];
}
def THX3T110XWriteFDiv : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX3T110XWriteFDivSP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX3T110XWriteFDivDP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 4;
}
def THX3T110XWriteFSqrtSP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def THX3T110XWriteFSqrtDP : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 23;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 4;
}
@ -1271,19 +1271,19 @@ def : InstRW<[THX3T110Write_23Cyc_F01], (instregex "^FDIVDrr", "^FSQRTDr")>;
// FP multiply accumulate
def : WriteRes<WriteFMul, [THX3T110FP0123]> {
let Latency = 6;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX3T110XWriteFMul : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 6;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 3;
}
def THX3T110XWriteFMulAcc : SchedWriteRes<[THX3T110FP0123]> {
let Latency = 6;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 3;
}
@ -1362,12 +1362,12 @@ def : InstRW<[THX3T110Write_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
def : WriteRes<WriteVd, [THX3T110FP0123]> {
let Latency = 5;
let NumMicroOps = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def : WriteRes<WriteVq, [THX3T110FP0123]> {
let Latency = 5;
let NumMicroOps = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
// ASIMD arith, reduce, 4H/4S

8
llvm/lib/Target/AMDGPU/SISchedule.td
View File

@ -157,13 +157,13 @@ multiclass SICommonWriteRes {
def : HWVALUWriteRes<Write4PassDGEMM, 4>;
def : HWVALUWriteRes<Write8PassDGEMM, 16>;
let ReleaseAtCycles = [2] in
let ResourceCycles = [2] in
def : HWWriteRes<Write2PassMAI, [HWXDL], 2>;
let ReleaseAtCycles = [4] in
let ResourceCycles = [4] in
def : HWWriteRes<Write4PassMAI, [HWXDL], 4>;
let ReleaseAtCycles = [8] in
let ResourceCycles = [8] in
def : HWWriteRes<Write8PassMAI, [HWXDL], 8>;
let ReleaseAtCycles = [16] in
let ResourceCycles = [16] in
def : HWWriteRes<Write16PassMAI, [HWXDL], 16>;
} // End RetireOOO = 1

4
llvm/lib/Target/ARM/ARMSchedule.td
View File

@ -49,7 +49,7 @@
// NumMicroOps = 2; // Dispatch 2 micro-ops.
// // The two instances of resource P01 are occupied for one cycle. It is one
// // cycle because these resources happen to be pipelined.
// ReleaseAtCycles = [1, 1];
// ResourceCycles = [1, 1];
// }
// def : ReadAdvance<ReadAdvanceALUsr, 3>;
@ -195,7 +195,7 @@ class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
list<int> rcl, SchedWriteRes wr> :
SchedWriteRes<!listconcat(wr.ProcResources, resl)> {
let Latency = !add(wr.Latency, lat);
let ReleaseAtCycles = !listconcat(wr.ReleaseAtCycles, rcl);
let ResourceCycles = !listconcat(wr.ResourceCycles, rcl);
let NumMicroOps = !add(wr.NumMicroOps, uops);
SchedWriteRes BaseWr = wr;
}

24
llvm/lib/Target/ARM/ARMScheduleA57WriteRes.td
View File

@ -28,30 +28,30 @@ def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
let ReleaseAtCycles = [17]; }
let ResourceCycles = [17]; }
def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
let ReleaseAtCycles = [18]; }
let ResourceCycles = [18]; }
def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
let ReleaseAtCycles = [19]; }
let ResourceCycles = [19]; }
def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
let ReleaseAtCycles = [20]; }
let ResourceCycles = [20]; }
def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1;
let ReleaseAtCycles = [1]; }
let ResourceCycles = [1]; }
def A57Write_2cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 2;
let ReleaseAtCycles = [1]; }
let ResourceCycles = [1]; }
def A57Write_3cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 3; }
def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
def A57Write_2cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 2; }
def A57Write_3cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 3; }
def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2;
let ReleaseAtCycles = [1]; }
let ResourceCycles = [1]; }
def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
let ReleaseAtCycles = [32]; }
let ResourceCycles = [32]; }
def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
let ReleaseAtCycles = [32]; }
let ResourceCycles = [32]; }
def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
let ReleaseAtCycles = [35]; }
let ResourceCycles = [35]; }
def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
@ -89,7 +89,7 @@ def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 64;
let NumMicroOps = 2;
let ReleaseAtCycles = [32, 32];
let ResourceCycles = [32, 32];
}
def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
A57UnitL]> {
@ -224,7 +224,7 @@ def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
let Latency = 36;
let NumMicroOps = 2;
let ReleaseAtCycles = [18, 18];
let ResourceCycles = [18, 18];
}
def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
A57UnitM]> {

6
llvm/lib/Target/ARM/ARMScheduleA9.td
View File

@ -1995,15 +1995,15 @@ def : WriteRes<WriteVST4, []>;
// Reserve A9UnitFP for 2 consecutive cycles.
def A9Write2V4 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 4;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
}
def A9Write2V7 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 7;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
}
def A9Write2V9 : SchedWriteRes<[A9UnitFP, A9UnitAGU]> {
let Latency = 9;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
}
// Branches don't have a def operand but still consume resources.

26
llvm/lib/Target/ARM/ARMScheduleM55.td
View File

@ -46,7 +46,7 @@
//
// For this schedule, we currently model latencies and pipelines well for each
// instruction. MVE instruction take two beats, modelled using
// ReleaseAtCycles=[2].
// ResourceCycles=[2].
//
//
// Dual Issue
@ -245,7 +245,7 @@ def : ReadAdvance<ReadMAC, 0>;
// MVE and VFP //
//=============//
// The Writes that take ReleaseAtCycles=[2] are MVE instruction, the others VFP.
// The Writes that take ResourceCycles=[2] are MVE instruction, the others VFP.
let SingleIssue = 1, Latency = 1 in {
def M55WriteLSE2 : SchedWriteRes<[M55UnitLoadStore]>;
@ -253,10 +253,10 @@ let SingleIssue = 1, Latency = 1 in {
def M55WriteFloatE2 : SchedWriteRes<[M55UnitVecFPALU]>;
def M55WriteSysE2 : SchedWriteRes<[M55UnitVecSys]>;
def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ReleaseAtCycles=[2]; }
def M55Write2LSE2 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
def M55Write2IntE2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2FloatE2 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
def M55Write2IntFPE2 : SchedWriteRes<[M55UnitVecIntFP]> { let ResourceCycles=[2]; }
}
let SingleIssue = 1, Latency = 2 in {
@ -264,20 +264,20 @@ let SingleIssue = 1, Latency = 2 in {
def M55WriteIntE3 : SchedWriteRes<[M55UnitVecALU]>;
def M55WriteFloatE3 : SchedWriteRes<[M55UnitVecFPALU]>;
def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
def M55Write2LSE3 : SchedWriteRes<[M55UnitLoadStore]> { let ResourceCycles=[2]; }
def M55Write2IntE3 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2FloatE3 : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
}
let SingleIssue = 1, Latency = 3 in {
def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE3Plus1 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
// Same as M55Write2IntE3/M55Write2FloatE3 above, but longer latency and no forwarding into stores
def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE4NoFwd : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55Write2FloatE4NoFwd : SchedWriteRes<[M55UnitVecFPALU]> { let ResourceCycles=[2]; }
}
let SingleIssue = 1, Latency = 4 in {
def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ReleaseAtCycles=[2]; }
def M55Write2IntE3Plus2 : SchedWriteRes<[M55UnitVecALU]> { let ResourceCycles=[2]; }
def M55WriteFloatE3Plus2 : SchedWriteRes<[M55UnitVecFPALU]>;
}
let SingleIssue = 1, Latency = 9 in {

48
llvm/lib/Target/ARM/ARMScheduleR52.td
View File

@ -72,7 +72,7 @@ def : WriteRes<WriteCMPsr, [R52UnitALU]> { let Latency = 0; }
// Div - may stall 0-9 cycles depending on input (i.e. WRI+(0-9)/2)
def : WriteRes<WriteDIV, [R52UnitDiv]> {
let Latency = 8; let ReleaseAtCycles = [8]; // non-pipelined
let Latency = 8; let ResourceCycles = [8]; // non-pipelined
}
// Branches - LR written in Late EX2
@ -107,12 +107,12 @@ def : WriteRes<WriteFPMAC64, [R52UnitFPMUL, R52UnitFPMUL,
def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
let Latency = 7; // FP div takes fixed #cycles
let ReleaseAtCycles = [7]; // is not pipelined
let ResourceCycles = [7]; // is not pipelined
}
def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
let Latency = 17;
let ReleaseAtCycles = [17];
let ResourceCycles = [17];
}
def : WriteRes<WriteFPSQRT32, [R52UnitDiv]> { let Latency = 7; }
@ -145,7 +145,7 @@ def R52WriteMACHi : SchedWriteRes<[R52UnitMAC]> {
let Latency = 4; let NumMicroOps = 0;
}
def R52WriteDIV : SchedWriteRes<[R52UnitDiv]> {
let Latency = 8; let ReleaseAtCycles = [8]; // not pipelined
let Latency = 8; let ResourceCycles = [8]; // not pipelined
}
def R52WriteLd : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
def R52WriteST : SchedWriteRes<[R52UnitLd]> { let Latency = 4; }
@ -552,7 +552,7 @@ foreach Num = 1-32 in { // reserve LdSt resource, no dual-issue
def R52ReserveLd#Num#Cy : SchedWriteRes<[R52UnitLd]> {
let Latency = 0;
let NumMicroOps = Num;
let ReleaseAtCycles = [Num];
let ResourceCycles = [Num];
}
}
def R52WriteVLDM : SchedWriteVariant<[
@ -639,57 +639,57 @@ def R52WriteVLDM : SchedWriteVariant<[
def R52WriteSTM5 : SchedWriteRes<[R52UnitLd]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def R52WriteSTM6 : SchedWriteRes<[R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def R52WriteSTM7 : SchedWriteRes<[R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 6;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def R52WriteSTM8 : SchedWriteRes<[R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 8;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def R52WriteSTM9 : SchedWriteRes<[R52UnitLd]> {
let Latency = 9;
let NumMicroOps = 10;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
}
def R52WriteSTM10 : SchedWriteRes<[R52UnitLd]> {
let Latency = 10;
let NumMicroOps = 12;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
}
def R52WriteSTM11 : SchedWriteRes<[R52UnitLd]> {
let Latency = 11;
let NumMicroOps = 14;
let ReleaseAtCycles = [7];
let ResourceCycles = [7];
}
def R52WriteSTM12 : SchedWriteRes<[R52UnitLd]> {
let Latency = 12;
let NumMicroOps = 16;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def R52WriteSTM13 : SchedWriteRes<[R52UnitLd]> {
let Latency = 13;
let NumMicroOps = 18;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def R52WriteSTM14 : SchedWriteRes<[R52UnitLd]> {
let Latency = 14;
let NumMicroOps = 20;
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
}
def R52WriteSTM15 : SchedWriteRes<[R52UnitLd]> {
let Latency = 15;
let NumMicroOps = 22;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
def R52WriteSTM : SchedWriteVariant<[
@ -719,45 +719,45 @@ def : WriteRes<WriteVLD1, [R52UnitLd]> { let Latency = 5;}
def : WriteRes<WriteVLD2, [R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 3;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let SingleIssue = 1;
}
def : WriteRes<WriteVLD3, [R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 5;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let SingleIssue = 1;
}
def : WriteRes<WriteVLD4, [R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 7;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let SingleIssue = 1;
}
def R52WriteVST1Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 5;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def R52WriteVST2Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 6;
let NumMicroOps = 3;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def R52WriteVST3Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 7;
let NumMicroOps = 5;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def R52WriteVST4Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 8;
let NumMicroOps = 7;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def R52WriteVST5Mem : SchedWriteRes<[R52UnitLd]> {
let Latency = 9;
let NumMicroOps = 9;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
}

28
llvm/lib/Target/ARM/ARMScheduleSwift.td
View File

@ -88,7 +88,7 @@ let SchedModel = SwiftModel in {
def SwiftWriteP0ThreeCycleThreeUops : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 3;
let NumMicroOps = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
// Plain load without writeback.
def SwiftWriteP2ThreeCycle : SchedWriteRes<[SwiftUnitP2]> {
@ -261,7 +261,7 @@ let SchedModel = SwiftModel in {
def SwiftP0P0P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
let Latency = 5;
let NumMicroOps = 3;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
}
def SwiftWrite1Cycle : SchedWriteRes<[]> {
let Latency = 1;
@ -283,7 +283,7 @@ let SchedModel = SwiftModel in {
def Swift2P03P01FiveCycle : SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]> {
let Latency = 7;
let NumMicroOps = 5;
let ReleaseAtCycles = [2, 3];
let ResourceCycles = [2, 3];
}
// Aliasing sub-target specific WriteRes to generic ones
@ -313,7 +313,7 @@ let SchedModel = SwiftModel in {
def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 14;
let ReleaseAtCycles = [1, 14];
let ResourceCycles = [1, 14];
}
// 4.2.18 Integer Divide
def : WriteRes<WriteDIV, [SwiftUnitDiv]>; // Workaround.
@ -653,15 +653,15 @@ let SchedModel = SwiftModel in {
// Serializing instructions.
def SwiftWaitP0For15Cy : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 15;
let ReleaseAtCycles = [15];
let ResourceCycles = [15];
}
def SwiftWaitP1For15Cy : SchedWriteRes<[SwiftUnitP1]> {
let Latency = 15;
let ReleaseAtCycles = [15];
let ResourceCycles = [15];
}
def SwiftWaitP2For15Cy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 15;
let ReleaseAtCycles = [15];
let ResourceCycles = [15];
}
def : InstRW<[SwiftWaitP0For15Cy, SwiftWaitP1For15Cy, SwiftWaitP2For15Cy],
(instregex "VMRS")>;
@ -684,7 +684,7 @@ let SchedModel = SwiftModel in {
def SwiftVLDMPerm#Num : SchedWriteRes<[SwiftUnitP1]> {
let Latency = 0;
let NumMicroOps = Num;
let ReleaseAtCycles = [Num];
let ResourceCycles = [Num];
}
}
@ -860,17 +860,17 @@ let SchedModel = SwiftModel in {
// 4.2.43 Advanced SIMD, Element or Structure Load and Store
def SwiftWrite2xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def SwiftWrite3xP2FourCy : SchedWriteRes<[SwiftUnitP2]> {
let Latency = 4;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
foreach Num = 1-2 in {
def SwiftExt#Num#xP0 : SchedWriteRes<[SwiftUnitP0]> {
let Latency = 0;
let NumMicroOps = Num;
let ReleaseAtCycles = [Num];
let ResourceCycles = [Num];
}
}
// VLDx
@ -1038,12 +1038,12 @@ let SchedModel = SwiftModel in {
def SwiftDiv17 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 17;
let ReleaseAtCycles = [1, 15];
let ResourceCycles = [1, 15];
}
def SwiftDiv32 : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
let NumMicroOps = 1;
let Latency = 32;
let ReleaseAtCycles = [1, 30];
let ResourceCycles = [1, 30];
}
def : InstRW<[SwiftDiv17], (instregex "VDIVS", "VSQRTS")>;
def : InstRW<[SwiftDiv32], (instregex "VDIVD", "VSQRTD")>;
@ -1086,7 +1086,7 @@ let SchedModel = SwiftModel in {
def : InstRW<[SwiftWriteP01OneCycle2x], (instregex "ABS")>;
// Preload.
def : WriteRes<WritePreLd, [SwiftUnitP2]> { let Latency = 0;
let ReleaseAtCycles = [0];
let ResourceCycles = [0];
}
}

22
llvm/lib/Target/Mips/MipsScheduleGeneric.td
View File

@ -160,12 +160,12 @@ def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> {
def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 33;
let ReleaseAtCycles = [33];
let ResourceCycles = [33];
}
def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> {
// Estimated worst case
let Latency = 31;
let ReleaseAtCycles = [31];
let ResourceCycles = [31];
}
// mul
@ -761,35 +761,35 @@ def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> {
}
def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
let ReleaseAtCycles = [ 14 ];
let ResourceCycles = [ 14 ];
}
def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 32;
let ReleaseAtCycles = [ 29 ];
let ResourceCycles = [ 29 ];
}
def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 13;
let ReleaseAtCycles = [ 10 ];
let ResourceCycles = [ 10 ];
}
def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 25;
let ReleaseAtCycles = [ 21 ];
let ResourceCycles = [ 21 ];
}
def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
let ReleaseAtCycles = [ 14 ];
let ResourceCycles = [ 14 ];
}
def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 32;
let ReleaseAtCycles = [ 29 ];
let ResourceCycles = [ 29 ];
}
def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 17;
let ReleaseAtCycles = [ 14 ];
let ResourceCycles = [ 14 ];
}
def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> {
let Latency = 29;
let ReleaseAtCycles = [ 29 ];
let ResourceCycles = [ 29 ];
}
// Floating point compare and branch
@ -1405,7 +1405,7 @@ let Latency = 5;
}
def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> {
let Latency = 33;
let ReleaseAtCycles = [ 33 ];
let ResourceCycles = [ 33 ];
}
// FPUS is also used in moves from floating point and MSA registers to general

24
llvm/lib/Target/Mips/MipsScheduleP5600.td
View File

@ -119,7 +119,7 @@ def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>;
def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> {
// FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2
// not during 0, 1, and 2.
let ReleaseAtCycles = [ 1, 3 ];
let ResourceCycles = [ 1, 3 ];
}
def P5600WriteGPRFromBypass : SchedWriteRes<[P5600IssueLDST]> {
@ -165,12 +165,12 @@ def P5600WriteAL2CondMov : SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> {
def P5600WriteAL2Div : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
// Estimated worst case
let Latency = 34;
let ReleaseAtCycles = [1, 34];
let ResourceCycles = [1, 34];
}
def P5600WriteAL2DivU : SchedWriteRes<[P5600IssueAL2, P5600AL2Div]> {
// Estimated worst case
let Latency = 34;
let ReleaseAtCycles = [1, 34];
let ResourceCycles = [1, 34];
}
def P5600WriteAL2Mul : SchedWriteRes<[P5600IssueAL2]> { let Latency = 3; }
def P5600WriteAL2Mult: SchedWriteRes<[P5600IssueAL2]> { let Latency = 5; }
@ -241,47 +241,47 @@ def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6;
def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 23 / 27
let Latency = 23; // Using common case
let ReleaseAtCycles = [ 1, 23 ];
let ResourceCycles = [ 1, 23 ];
}
def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 23 / 27
let Latency = 23; // Using common case
let ReleaseAtCycles = [ 1, 23 ];
let ResourceCycles = [ 1, 23 ];
}
def P5600WriteFPUDivD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 31 / 35
let Latency = 31; // Using common case
let ReleaseAtCycles = [ 1, 31 ];
let ResourceCycles = [ 1, 31 ];
}
def P5600WriteFPURcpS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 19 / 23
let Latency = 19; // Using common case
let ReleaseAtCycles = [ 1, 19 ];
let ResourceCycles = [ 1, 19 ];
}
def P5600WriteFPURcpD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
let ReleaseAtCycles = [ 1, 27 ];
let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPURsqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 27
let Latency = 27; // Using common case
let ReleaseAtCycles = [ 1, 27 ];
let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPURsqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
let ReleaseAtCycles = [ 1, 27 ];
let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPUSqrtS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 27 / 31
let Latency = 27; // Using common case
let ReleaseAtCycles = [ 1, 27 ];
let ResourceCycles = [ 1, 27 ];
}
def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> {
// Best/Common/Worst case = 7 / 35 / 39
let Latency = 35; // Using common case
let ReleaseAtCycles = [ 1, 35 ];
let ResourceCycles = [ 1, 35 ];
}
def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>;
def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; }

62
llvm/lib/Target/PowerPC/PPCScheduleP10.td
View File

@ -87,27 +87,27 @@ let SchedModel = P10Model in {
}
def P10W_BF_22C : SchedWriteRes<[P10_BF]> {
let ReleaseAtCycles = [ 5 ];
let ResourceCycles = [ 5 ];
let Latency = 22;
}
def P10W_BF_24C : SchedWriteRes<[P10_BF]> {
let ReleaseAtCycles = [ 8 ];
let ResourceCycles = [ 8 ];
let Latency = 24;
}
def P10W_BF_26C : SchedWriteRes<[P10_BF]> {
let ReleaseAtCycles = [ 5 ];
let ResourceCycles = [ 5 ];
let Latency = 26;
}
def P10W_BF_27C : SchedWriteRes<[P10_BF]> {
let ReleaseAtCycles = [ 7 ];
let ResourceCycles = [ 7 ];
let Latency = 27;
}
def P10W_BF_36C : SchedWriteRes<[P10_BF]> {
let ReleaseAtCycles = [ 10 ];
let ResourceCycles = [ 10 ];
let Latency = 36;
}
@ -128,134 +128,134 @@ let SchedModel = P10Model in {
}
def P10W_DF_24C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 16 ];
let ResourceCycles = [ 16 ];
let Latency = 24;
}
def P10W_DF_25C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 17 ];
let ResourceCycles = [ 17 ];
let Latency = 25;
}
def P10W_DF_26C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 18 ];
let ResourceCycles = [ 18 ];
let Latency = 26;
}
def P10W_DF_32C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 22 ];
let ResourceCycles = [ 22 ];
let Latency = 32;
}
def P10W_DF_33C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 25 ];
let ResourceCycles = [ 25 ];
let Latency = 33;
}
def P10W_DF_34C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 25 ];
let ResourceCycles = [ 25 ];
let Latency = 34;
}
def P10W_DF_38C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 30 ];
let ResourceCycles = [ 30 ];
let Latency = 38;
}
def P10W_DF_40C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 17 ];
let ResourceCycles = [ 17 ];
let Latency = 40;
}
def P10W_DF_43C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 34 ];
let ResourceCycles = [ 34 ];
let Latency = 43;
}
def P10W_DF_59C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 49 ];
let ResourceCycles = [ 49 ];
let Latency = 59;
}
def P10W_DF_61C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 12 ];
let ResourceCycles = [ 12 ];
let Latency = 61;
}
def P10W_DF_68C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 15 ];
let ResourceCycles = [ 15 ];
let Latency = 68;
}
def P10W_DF_77C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 67 ];
let ResourceCycles = [ 67 ];
let Latency = 77;
}
def P10W_DF_87C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 12 ];
let ResourceCycles = [ 12 ];
let Latency = 87;
}
def P10W_DF_100C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 32 ];
let ResourceCycles = [ 32 ];
let Latency = 100;
}
def P10W_DF_174C : SchedWriteRes<[P10_DF]> {
let ReleaseAtCycles = [ 33 ];
let ResourceCycles = [ 33 ];
let Latency = 174;
}
// A DV pipeline may take from 20 to 83 cycles to complete.
// Some DV operations may keep the pipeline busy for up to 33 cycles.
def P10W_DV_20C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 10 ];
let ResourceCycles = [ 10 ];
let Latency = 20;
}
def P10W_DV_25C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 10 ];
let ResourceCycles = [ 10 ];
let Latency = 25;
}
def P10W_DV_27C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 10 ];
let ResourceCycles = [ 10 ];
let Latency = 27;
}
def P10W_DV_41C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 10 ];
let ResourceCycles = [ 10 ];
let Latency = 41;
}
def P10W_DV_43C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 21 ];
let ResourceCycles = [ 21 ];
let Latency = 43;
}
def P10W_DV_47C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 21 ];
let ResourceCycles = [ 21 ];
let Latency = 47;
}
def P10W_DV_54C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 33 ];
let ResourceCycles = [ 33 ];
let Latency = 54;
}
def P10W_DV_60C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 33 ];
let ResourceCycles = [ 33 ];
let Latency = 60;
}
def P10W_DV_75C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 21 ];
let ResourceCycles = [ 21 ];
let Latency = 75;
}
def P10W_DV_83C : SchedWriteRes<[P10_DV]> {
let ReleaseAtCycles = [ 33 ];
let ResourceCycles = [ 33 ];
let Latency = 83;
}

40
llvm/lib/Target/PowerPC/PPCScheduleP9.td
View File

@ -227,17 +227,17 @@ let SchedModel = P9Model in {
}
def P9_DIV_16C_8 : SchedWriteRes<[DIV]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 16;
}
def P9_DIV_24C_8 : SchedWriteRes<[DIV]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 24;
}
def P9_DIV_40C_8 : SchedWriteRes<[DIV]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 40;
}
@ -261,62 +261,62 @@ let SchedModel = P9Model in {
}
def P9_DP_22C_5 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
let Latency = 22;
}
def P9_DPO_24C_8 : SchedWriteRes<[DPO]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 24;
}
def P9_DPE_24C_8 : SchedWriteRes<[DPE]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 24;
}
def P9_DP_26C_5 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
let Latency = 22;
}
def P9_DPE_27C_10 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
let Latency = 27;
}
def P9_DPO_27C_10 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
let Latency = 27;
}
def P9_DP_33C_8 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 33;
}
def P9_DPE_33C_8 : SchedWriteRes<[DPE]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 33;
}
def P9_DPO_33C_8 : SchedWriteRes<[DPO]> {
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let Latency = 33;
}
def P9_DP_36C_10 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
let Latency = 36;
}
def P9_DPE_36C_10 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
let Latency = 36;
}
def P9_DPO_36C_10 : SchedWriteRes<[DP]> {
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
let Latency = 36;
}
@ -358,27 +358,27 @@ let SchedModel = P9Model in {
def P9_DFU_23C : SchedWriteRes<[DFU]> {
let Latency = 23;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
def P9_DFU_24C : SchedWriteRes<[DFU]> {
let Latency = 24;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
}
def P9_DFU_37C : SchedWriteRes<[DFU]> {
let Latency = 37;
let ReleaseAtCycles = [25];
let ResourceCycles = [25];
}
def P9_DFU_58C : SchedWriteRes<[DFU]> {
let Latency = 58;
let ReleaseAtCycles = [44];
let ResourceCycles = [44];
}
def P9_DFU_76C : SchedWriteRes<[DFU]> {
let Latency = 76;
let ReleaseAtCycles = [62];
let ResourceCycles = [62];
}
// 2 or 5 cycle latencies for the branch unit.

10
llvm/lib/Target/RISCV/RISCVSchedRocket.td
View File

@ -70,11 +70,11 @@ def : WriteRes<WriteIMul32, [RocketUnitIMul]>;
// Worst case latency is used.
def : WriteRes<WriteIDiv32, [RocketUnitIDiv]> {
let Latency = 34;
let ReleaseAtCycles = [34];
let ResourceCycles = [34];
}
def : WriteRes<WriteIDiv, [RocketUnitIDiv]> {
let Latency = 33;
let ReleaseAtCycles = [33];
let ResourceCycles = [33];
}
// Memory
@ -157,16 +157,16 @@ def : WriteRes<WriteFMA64, [RocketUnitFPALU]>;
// FP division
// FP division unit on Rocket is not pipelined, so set resource cycles to latency.
let Latency = 20, ReleaseAtCycles = [20] in {
let Latency = 20, ResourceCycles = [20] in {
def : WriteRes<WriteFDiv32, [RocketUnitFPDivSqrt]>;
def : WriteRes<WriteFDiv64, [RocketUnitFPDivSqrt]>;
}
// FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
def : WriteRes<WriteFSqrt32, [RocketUnitFPDivSqrt]> { let Latency = 20;
let ReleaseAtCycles = [20]; }
let ResourceCycles = [20]; }
def : WriteRes<WriteFSqrt64, [RocketUnitFPDivSqrt]> { let Latency = 25;
let ReleaseAtCycles = [25]; }
let ResourceCycles = [25]; }
// Others
def : WriteRes<WriteCSR, []>;

130
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
View File

@ -256,11 +256,11 @@ def : WriteRes<WriteIMul32, [SiFive7PipeB]>;
// Integer division
def : WriteRes<WriteIDiv, [SiFive7PipeB, SiFive7IDiv]> {
let Latency = 66;
let ReleaseAtCycles = [1, 65];
let ResourceCycles = [1, 65];
}
def : WriteRes<WriteIDiv32, [SiFive7PipeB, SiFive7IDiv]> {
let Latency = 34;
let ReleaseAtCycles = [1, 33];
let ResourceCycles = [1, 33];
}
// Bitmanip
@ -346,7 +346,7 @@ def : WriteRes<WriteFSGNJ16, [SiFive7PipeB]>;
def : WriteRes<WriteFMinMax16, [SiFive7PipeB]>;
}
let Latency = 14, ReleaseAtCycles = [1, 13] in {
let Latency = 14, ResourceCycles = [1, 13] in {
def : WriteRes<WriteFDiv16, [SiFive7PipeB, SiFive7FDiv]>;
def : WriteRes<WriteFSqrt16, [SiFive7PipeB, SiFive7FDiv]>;
}
@ -363,9 +363,9 @@ def : WriteRes<WriteFMinMax32, [SiFive7PipeB]>;
}
def : WriteRes<WriteFDiv32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
let ReleaseAtCycles = [1, 26]; }
let ResourceCycles = [1, 26]; }
def : WriteRes<WriteFSqrt32, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 27;
let ReleaseAtCycles = [1, 26]; }
let ResourceCycles = [1, 26]; }
// Double precision
let Latency = 7 in {
@ -379,9 +379,9 @@ def : WriteRes<WriteFMinMax64, [SiFive7PipeB]>;
}
def : WriteRes<WriteFDiv64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
let ReleaseAtCycles = [1, 55]; }
let ResourceCycles = [1, 55]; }
def : WriteRes<WriteFSqrt64, [SiFive7PipeB, SiFive7FDiv]> { let Latency = 56;
let ReleaseAtCycles = [1, 55]; }
let ResourceCycles = [1, 55]; }
// Conversions
let Latency = 3 in {
@ -431,20 +431,20 @@ def : WriteRes<WriteVSETVL, [SiFive7PipeA]>;
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDE", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDFF", [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in
let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSTE", [SiFive7VS], mx, IsWorstCase>;
}
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetMaskLoadStoreCycles<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in
let Latency = 4, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVLDM", [SiFive7VL], mx, IsWorstCase>;
let Latency = 1, ReleaseAtCycles = [Cycles] in
let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSTM", [SiFive7VS], mx, IsWorstCase>;
}
@ -458,12 +458,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 8>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS8", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX8", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX8", [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in {
let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS8", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX8", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX8", [SiFive7VS], mx, IsWorstCase>;
@ -472,12 +472,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 16>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS16", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX16", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX16", [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in {
let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS16", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX16", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX16", [SiFive7VS], mx, IsWorstCase>;
@ -486,12 +486,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 32>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS32", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX32", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX32", [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in {
let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS32", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX32", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX32", [SiFive7VS], mx, IsWorstCase>;
@ -500,12 +500,12 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, 64>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLDS64", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX64", [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX64", [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in {
let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSTS64", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX64", [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX64", [SiFive7VS], mx, IsWorstCase>;
@ -513,22 +513,22 @@ foreach mx = SchedMxList in {
}
// VLD*R is LMUL aware
let Latency = 4, ReleaseAtCycles = [2] in
let Latency = 4, ResourceCycles = [2] in
def : WriteRes<WriteVLD1R, [SiFive7VL]>;
let Latency = 4, ReleaseAtCycles = [4] in
let Latency = 4, ResourceCycles = [4] in
def : WriteRes<WriteVLD2R, [SiFive7VL]>;
let Latency = 4, ReleaseAtCycles = [8] in
let Latency = 4, ResourceCycles = [8] in
def : WriteRes<WriteVLD4R, [SiFive7VL]>;
let Latency = 4, ReleaseAtCycles = [16] in
let Latency = 4, ResourceCycles = [16] in
def : WriteRes<WriteVLD8R, [SiFive7VL]>;
// VST*R is LMUL aware
let Latency = 1, ReleaseAtCycles = [2] in
let Latency = 1, ResourceCycles = [2] in
def : WriteRes<WriteVST1R, [SiFive7VS]>;
let Latency = 1, ReleaseAtCycles = [4] in
let Latency = 1, ResourceCycles = [4] in
def : WriteRes<WriteVST2R, [SiFive7VS]>;
let Latency = 1, ReleaseAtCycles = [8] in
let Latency = 1, ResourceCycles = [8] in
def : WriteRes<WriteVST4R, [SiFive7VS]>;
let Latency = 1, ReleaseAtCycles = [16] in
let Latency = 1, ResourceCycles = [16] in
def : WriteRes<WriteVST8R, [SiFive7VS]>;
// Segmented Loads and Stores
@ -542,21 +542,21 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesSegmentedSeg2<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
// Does not chain so set latency high
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLSEG2e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLSEGFF2e" # eew, [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in
let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSSEG2e" # eew, [SiFive7VS], mx, IsWorstCase>;
foreach nf=3-8 in {
defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
// Does not chain so set latency high
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in
let Latency = 1, ResourceCycles = [Cycles] in
defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
}
}
@ -567,12 +567,12 @@ foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesSegmented<mx, eew, nf>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
// Does not chain so set latency high
let Latency = !add(3, Cycles), ReleaseAtCycles = [Cycles] in {
let Latency = !add(3, Cycles), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [SiFive7VL], mx, IsWorstCase>;
}
let Latency = 1, ReleaseAtCycles = [Cycles] in {
let Latency = 1, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [SiFive7VS], mx, IsWorstCase>;
@ -585,7 +585,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVIALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUI", [SiFive7VA], mx, IsWorstCase>;
@ -609,7 +609,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVIMovI", [SiFive7VA], mx, IsWorstCase>;
}
// Mask results can't chain.
let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVICmpV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVICmpI", [SiFive7VA], mx, IsWorstCase>;
@ -618,7 +618,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVExtV", [SiFive7VA], mx, IsWorstCase>;
}
}
@ -627,7 +627,7 @@ foreach mx = SchedMxList in {
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
!div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
let Latency = Cycles, ResourceCycles = [Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SiFive7VA], mx, sew, IsWorstCase>;
}
@ -638,7 +638,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVIWALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUI", [SiFive7VA], mx, IsWorstCase>;
@ -652,7 +652,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVNShiftV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftI", [SiFive7VA], mx, IsWorstCase>;
@ -663,7 +663,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVSALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUI", [SiFive7VA], mx, IsWorstCase>;
@ -680,7 +680,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVNClipV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipI", [SiFive7VA], mx, IsWorstCase>;
@ -691,7 +691,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFALUF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMulV", [SiFive7VA], mx, IsWorstCase>;
@ -702,7 +702,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVFCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
}
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFSgnjV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFSgnjF", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMinMaxV", [SiFive7VA], mx, IsWorstCase>;
@ -712,7 +712,7 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVFMovV", [SiFive7VA], mx, IsWorstCase>;
}
// Mask results can't chain.
let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFCmpV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCmpF", [SiFive7VA], mx, IsWorstCase>;
}
@ -722,7 +722,7 @@ foreach mx = SchedMxListF in {
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
!div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
let Latency = Cycles, ResourceCycles = [Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SiFive7VA], mx, sew, IsWorstCase>;
@ -734,14 +734,14 @@ foreach mx = SchedMxListF in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFWCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
}
}
foreach mx = SchedMxListFW in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFWALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFWMulV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFWMulAddV", [SiFive7VA], mx, IsWorstCase>;
@ -756,14 +756,14 @@ foreach mx = SchedMxListFW in {
foreach mx = SchedMxListW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SiFive7VA], mx, IsWorstCase>;
}
}
foreach mx = SchedMxListFW in {
defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVFNCvtIToFV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFNCvtFToFV", [SiFive7VA], mx, IsWorstCase>;
}
@ -774,7 +774,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in
let Latency = Cycles, ResourceCycles = [Cycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
@ -786,7 +786,7 @@ foreach mx = SchedMxListWRed in {
foreach sew = SchedSEWSet<mx, 0, 1>.val in {
defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in
let Latency = Cycles, ResourceCycles = [Cycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
@ -796,14 +796,14 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, 1>.val in {
defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in {
let Latency = RedCycles, ResourceCycles = [RedCycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in
let Latency = OrdRedCycles, ResourceCycles = [OrdRedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
@ -813,11 +813,11 @@ foreach mx = SchedMxListFWRed in {
foreach sew = SchedSEWSet<mx, 1, 1>.val in {
defvar RedCycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
let Latency = RedCycles, ReleaseAtCycles = [RedCycles] in
let Latency = RedCycles, ResourceCycles = [RedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew>.c;
let Latency = OrdRedCycles, ReleaseAtCycles = [OrdRedCycles] in
let Latency = OrdRedCycles, ResourceCycles = [OrdRedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SiFive7VA],
mx, sew, IsWorstCase>;
}
@ -827,7 +827,7 @@ foreach mx = SchedMxListFWRed in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesVMask<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVMALUV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMPopV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMFFSV", [SiFive7VA], mx, IsWorstCase>;
@ -837,14 +837,14 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VA], mx, IsWorstCase>;
}
}
// 16. Vector Permutation Instructions
let Latency = 4, ReleaseAtCycles = [1] in {
let Latency = 4, ResourceCycles = [1] in {
def : WriteRes<WriteVIMovVX, [SiFive7VA]>;
def : WriteRes<WriteVIMovXV, [SiFive7VA]>;
def : WriteRes<WriteVFMovVF, [SiFive7VA]>;
@ -853,7 +853,7 @@ let Latency = 4, ReleaseAtCycles = [1] in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 8, ReleaseAtCycles = [Cycles] in {
let Latency = 8, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVRGatherVX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVRGatherVI", [SiFive7VA], mx, IsWorstCase>;
}
@ -863,7 +863,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
let Latency = !add(Cycles, 3), ReleaseAtCycles = [Cycles] in {
let Latency = !add(Cycles, 3), ResourceCycles = [Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SiFive7VA], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SiFive7VA], mx, sew, IsWorstCase>;
}
@ -873,7 +873,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 4, ReleaseAtCycles = [Cycles] in {
let Latency = 4, ResourceCycles = [Cycles] in {
defm "" : LMULWriteResMX<"WriteVISlideX", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlideI", [SiFive7VA], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFive7VA], mx, IsWorstCase>;
@ -882,13 +882,13 @@ foreach mx = SchedMxList in {
}
// VMov*V is LMUL Aware
let Latency = 4, ReleaseAtCycles = [2] in
let Latency = 4, ResourceCycles = [2] in
def : WriteRes<WriteVMov1V, [SiFive7VA]>;
let Latency = 4, ReleaseAtCycles = [4] in
let Latency = 4, ResourceCycles = [4] in
def : WriteRes<WriteVMov2V, [SiFive7VA]>;
let Latency = 4, ReleaseAtCycles = [8] in
let Latency = 4, ResourceCycles = [8] in
def : WriteRes<WriteVMov4V, [SiFive7VA]>;
let Latency = 4, ReleaseAtCycles = [16] in
let Latency = 4, ResourceCycles = [16] in
def : WriteRes<WriteVMov8V, [SiFive7VA]>;
// Others

4
llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
View File

@ -55,14 +55,14 @@ def : WriteRes<WriteIMul, [SCR1_MUL]>;
def : WriteRes<WriteIMul32, [SCR1_MUL]>;
// Integer division: latency 33, inverse throughput 33
let Latency = 33, ReleaseAtCycles = [33] in {
let Latency = 33, ResourceCycles = [33] in {
def : WriteRes<WriteIDiv32, [SCR1_DIV]>;
def : WriteRes<WriteIDiv, [SCR1_DIV]>;
}
// Load/store instructions on SCR1 have latency 2 and inverse throughput 2
// (SCR1_CFG_RV32IMC_MAX includes TCM)
let Latency = 2, ReleaseAtCycles=[2] in {
let Latency = 2, ResourceCycles=[2] in {
// Memory
def : WriteRes<WriteSTB, [SCR1_LSU]>;
def : WriteRes<WriteSTH, [SCR1_LSU]>;

4
llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
View File

@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z13_VecUnit]>;
def : WriteRes<VecStr, [Z13_VecUnit]>;
def : WriteRes<VecXsPm, [Z13_VecUnit]>;
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
}}
def : WriteRes<VecFPd, [Z13_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
def : WriteRes<VecFPd, [Z13_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z13_VBUnit]>; // Virtual Branching Unit
}

4
llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
View File

@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z14_VecUnit]>;
def : WriteRes<VecStr, [Z14_VecUnit]>;
def : WriteRes<VecXsPm, [Z14_VecUnit]>;
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
}}
def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
def : WriteRes<VecFPd, [Z14_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z14_VBUnit]>; // Virtual Branching Unit
}

4
llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
View File

@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z15_VecUnit]>;
def : WriteRes<VecStr, [Z15_VecUnit]>;
def : WriteRes<VecXsPm, [Z15_VecUnit]>;
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z15_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z15_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z15_LSUnit]>;
@ -104,7 +104,7 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z15_VecUnit]>;
}}
def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
def : WriteRes<VecFPd, [Z15_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VBU, [Z15_VBUnit]>; // Virtual Branching Unit
}

6
llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
View File

@ -92,7 +92,7 @@ let NumMicroOps = 0 in {
def : WriteRes<VecMul, [Z16_VecUnit]>;
def : WriteRes<VecStr, [Z16_VecUnit]>;
def : WriteRes<VecXsPm, [Z16_VecUnit]>;
foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
foreach Num = 2-5 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z16_FXaUnit]>;
def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z16_FXbUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z16_LSUnit]>;
@ -104,8 +104,8 @@ let NumMicroOps = 0 in {
def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z16_VecUnit]>;
}}
def : WriteRes<VecFPd, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [30]; }
def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ReleaseAtCycles = [20]; }
def : WriteRes<VecFPd, [Z16_VecFPdUnit]> { let ResourceCycles = [30]; }
def : WriteRes<VecFPd20, [Z16_VecFPdUnit]> { let ResourceCycles = [20]; }
def : WriteRes<VBU, [Z16_VBUnit]>; // Virtual Branching Unit
}

2
llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
View File

@ -82,7 +82,7 @@ let NumMicroOps = 0 in {
def : WriteRes<LSU, [Z196_LSUnit]>;
def : WriteRes<FPU, [Z196_FPUnit]>;
def : WriteRes<DFU, [Z196_DFUnit]>;
foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
foreach Num = 2-6 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;

2
llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
View File

@ -83,7 +83,7 @@ let NumMicroOps = 0 in {
def : WriteRes<LSU, [ZEC12_LSUnit]>;
def : WriteRes<FPU, [ZEC12_FPUnit]>;
def : WriteRes<DFU, [ZEC12_DFUnit]>;
foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
foreach Num = 2-6 in { let ResourceCycles = [Num] in {
def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;

292
llvm/lib/Target/X86/X86SchedAlderlakeP.td
View File

File diff suppressed because it is too large Load Diff

282
llvm/lib/Target/X86/X86SchedBroadwell.td
View File

File diff suppressed because it is too large Load Diff

304
llvm/lib/Target/X86/X86SchedHaswell.td
View File

File diff suppressed because it is too large Load Diff

402
llvm/lib/Target/X86/X86SchedIceLake.td
View File

File diff suppressed because it is too large Load Diff

186
llvm/lib/Target/X86/X86SchedSandyBridge.td
View File

@ -90,7 +90,7 @@ multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -98,7 +98,7 @@ multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 5).
def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ReleaseAtCycles = !listconcat([1], Res);
let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -486,44 +486,44 @@ defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1
def : WriteRes<WritePCmpIStrM, [SBPort0]> {
let Latency = 11;
let NumMicroOps = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
let Latency = 17;
let NumMicroOps = 4;
let ReleaseAtCycles = [3,1];
let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Mask
def : WriteRes<WritePCmpEStrM, [SBPort015]> {
let Latency = 11;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
let Latency = 17;
let ReleaseAtCycles = [7, 1];
let ResourceCycles = [7, 1];
}
// Packed Compare Implicit Length Strings, Return Index
def : WriteRes<WritePCmpIStrI, [SBPort0]> {
let Latency = 11;
let NumMicroOps = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
let Latency = 17;
let NumMicroOps = 4;
let ReleaseAtCycles = [3,1];
let ResourceCycles = [3,1];
}
// Packed Compare Explicit Length Strings, Return Index
def : WriteRes<WritePCmpEStrI, [SBPort015]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
let Latency = 10;
let ReleaseAtCycles = [7, 1];
let ResourceCycles = [7, 1];
}
// MOVMSK Instructions.
@ -536,48 +536,48 @@ def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; }
def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
let Latency = 7;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
let Latency = 13;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def : WriteRes<WriteAESIMC, [SBPort5]> {
let Latency = 12;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
let Latency = 18;
let NumMicroOps = 3;
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
}
def : WriteRes<WriteAESKeyGen, [SBPort015]> {
let Latency = 8;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
let Latency = 14;
let ReleaseAtCycles = [10, 1];
let ResourceCycles = [10, 1];
}
// Carry-less multiplication instructions.
def : WriteRes<WriteCLMul, [SBPort015]> {
let Latency = 14;
let ReleaseAtCycles = [18];
let ResourceCycles = [18];
}
def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
let Latency = 20;
let ReleaseAtCycles = [17, 1];
let ResourceCycles = [17, 1];
}
// Load/store MXCSR.
// FIXME: This is probably wrong. Only STMXCSR should require Port4.
def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ReleaseAtCycles = [1,1,1,1]; }
def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ReleaseAtCycles = [1,1,1,1]; }
def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; }
def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
@ -601,7 +601,7 @@ defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1
def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
let Latency = 1;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
COM_FST0r,
@ -611,7 +611,7 @@ def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
let Latency = 1;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
LD_Frr, ST_Frr, ST_FPrr)>;
@ -620,14 +620,14 @@ def: InstRW<[SBWriteResGroup2], (instrs RET64)>;
def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
let Latency = 1;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
let Latency = 1;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
MMX_PABSDrr,
@ -641,7 +641,7 @@ def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroup11], (instrs SCASB,
SCASL,
@ -651,14 +651,14 @@ def: InstRW<[SBWriteResGroup11], (instrs SCASB,
def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>;
def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup15], (instrs CWD,
FNSTSW16r)>;
@ -666,7 +666,7 @@ def: InstRW<[SBWriteResGroup15], (instrs CWD,
def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
MMX_MOVDQ2Qrr)>;
@ -674,21 +674,21 @@ def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
let Latency = 3;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>;
def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
let Latency = 3;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
def SBWriteResGroup23 : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 2;
let NumMicroOps = 3;
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup23], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
@ -696,63 +696,63 @@ def: InstRW<[SBWriteResGroup23], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def SBWriteResGroup24 : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
let Latency = 3;
let NumMicroOps = 8;
let ReleaseAtCycles = [1,1,4,2];
let ResourceCycles = [1,1,4,2];
}
def: InstRW<[SBWriteResGroup24], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def SBWriteResGroup24b : SchedWriteRes<[SBPort1,SBPort5,SBPort05,SBPort015]> {
let Latency = 4;
let NumMicroOps = 8;
let ReleaseAtCycles = [1,1,4,2];
let ResourceCycles = [1,1,4,2];
}
def: InstRW<[SBWriteResGroup24b], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>;
def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
let Latency = 3;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
let Latency = 4;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>;
def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 4;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,3];
let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
def SBWriteResGroup30 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
let Latency = 3;
let NumMicroOps = 8;
let ReleaseAtCycles = [1,3,4];
let ResourceCycles = [1,3,4];
}
def: InstRW<[SBWriteResGroup30], (instrs LOOP)>;
def SBWriteResGroup31 : SchedWriteRes<[SBPort1,SBPort5,SBPort015,SBPort05]> {
let Latency = 4;
let NumMicroOps = 12;
let ReleaseAtCycles = [1,3,6,2];
let ResourceCycles = [1,3,6,2];
}
def: InstRW<[SBWriteResGroup31], (instrs LOOPE, LOOPNE)>;
def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> {
let Latency = 5;
let NumMicroOps = 8;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)rCL",
"RCR(8|16|32|64)rCL")>;
@ -760,21 +760,21 @@ def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)rCL",
def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
let Latency = 5;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup35], (instrs CLI)>;
def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>;
def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
@ -782,7 +782,7 @@ def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 5;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>;
def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
@ -791,21 +791,21 @@ def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 5;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>;
def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
let Latency = 5;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,3];
let ResourceCycles = [1,3];
}
def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
let Latency = 5;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,1,1,1];
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
"PUSHF(16|64)")>;
@ -813,21 +813,21 @@ def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 5;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,1,1,1];
let ResourceCycles = [1,1,1,1];
}
def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 5;
let NumMicroOps = 5;
let ReleaseAtCycles = [1,2,1,1];
let ResourceCycles = [1,2,1,1];
}
def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
let Latency = 6;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup48], (instrs VBROADCASTSSrm)>;
def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
@ -843,14 +843,14 @@ def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
MMX_PABSDrm,
@ -863,14 +863,14 @@ def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 6;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>;
def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
let Latency = 6;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
"ST_FP(32|64|80)m")>;
@ -878,7 +878,7 @@ def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
let Latency = 7;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
VBROADCASTSSYrm,
@ -889,49 +889,49 @@ def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 7;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>;
def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 7;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQrm)>;
def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>;
def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>;
def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup64], (instrs FARJMP64m)>;
def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,1,2];
let ResourceCycles = [1,1,2];
}
def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>;
def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,2,1];
let ResourceCycles = [1,2,1];
}
def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
"STR(16|32|64)r")>;
@ -939,7 +939,7 @@ def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,1,2];
let ResourceCycles = [1,1,2];
}
def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>;
def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
@ -947,7 +947,7 @@ def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 7;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,2,1];
let ResourceCycles = [1,2,1];
}
def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
"SHL(8|16|32|64)m(1|i)",
@ -956,21 +956,21 @@ def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 8;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> {
let Latency = 6;
let NumMicroOps = 3;
let ReleaseAtCycles = [1, 2, 1];
let ResourceCycles = [1, 2, 1];
}
def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>;
def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [2,3];
let ResourceCycles = [2,3];
}
def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
CMPSL,
@ -980,14 +980,14 @@ def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [1,2,2];
let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>;
def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [1,2,2];
let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
"ROR(8|16|32|64)m(1|i)")>;
@ -995,7 +995,7 @@ def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [1,2,2];
let ResourceCycles = [1,2,2];
}
def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
@ -1003,21 +1003,21 @@ def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
let Latency = 8;
let NumMicroOps = 5;
let ReleaseAtCycles = [1,1,1,2];
let ResourceCycles = [1,1,1,2];
}
def: InstRW<[SBWriteResGroup87], (instrs FARCALL64m)>;
def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
let Latency = 9;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>;
def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
let Latency = 9;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,1,2];
let ResourceCycles = [1,1,2];
}
def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
"IST_FP(16|32|64)m")>;
@ -1025,7 +1025,7 @@ def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 9;
let NumMicroOps = 6;
let ReleaseAtCycles = [1,2,3];
let ResourceCycles = [1,2,3];
}
def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
"ROR(8|16|32|64)mCL",
@ -1036,14 +1036,14 @@ def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
let Latency = 9;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,2,3];
let ResourceCycles = [1,2,3];
}
def: SchedAlias<WriteADCRMW, SBWriteResGroup98>;
def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
let NumMicroOps = 4;
let ReleaseAtCycles = [1,2,2,1];
let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
@ -1051,14 +1051,14 @@ def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr,
def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
let Latency = 9;
let NumMicroOps = 6;
let ReleaseAtCycles = [1,1,2,1,1];
let ResourceCycles = [1,1,2,1,1];
}
def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW
def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 10;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
"ILD_F(16|32|64)m")>;
@ -1066,21 +1066,21 @@ def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>;
def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 11;
let NumMicroOps = 3;
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>;
def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
let Latency = 11;
let NumMicroOps = 11;
let ReleaseAtCycles = [7,4];
let ResourceCycles = [7,4];
}
def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
"RCR(8|16|32|64)m")>;
@ -1088,49 +1088,49 @@ def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 12;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>;
def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
let Latency = 13;
let NumMicroOps = 3;
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
}
def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 15;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>;
def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
let Latency = 31;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,1];
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>;
def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
let Latency = 34;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,1,1];
let ResourceCycles = [1,1,1];
}
def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> {
let Latency = 9;
let NumMicroOps = 20;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>;
def SBWriteResGroupVzeroupper : SchedWriteRes<[]> {
let Latency = 1;
let NumMicroOps = 4;
let ReleaseAtCycles = [];
let ResourceCycles = [];
}
def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>;
@ -1190,7 +1190,7 @@ def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> {
let Latency = 5;
let NumMicroOps = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
@ -1202,13 +1202,13 @@ def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>;
// CMOVs that use both Z and C flag require an extra uop.
def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> {
let Latency = 3;
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
let NumMicroOps = 3;
}
def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
let Latency = 8;
let ReleaseAtCycles = [1,2,1];
let ResourceCycles = [1,2,1];
let NumMicroOps = 4;
}
@ -1228,13 +1228,13 @@ def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
// SETCCs that use both Z and C flag require an extra uop.
def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
let Latency = 3;
let ReleaseAtCycles = [1,1,2];
let ResourceCycles = [1,1,2];
let NumMicroOps = 4;
}

640
llvm/lib/Target/X86/X86SchedSapphireRapids.td
View File

File diff suppressed because it is too large Load Diff

296
llvm/lib/Target/X86/X86SchedSkylakeClient.td
View File

File diff suppressed because it is too large Load Diff

404
llvm/lib/Target/X86/X86SchedSkylakeServer.td
View File

File diff suppressed because it is too large Load Diff

4
llvm/lib/Target/X86/X86Schedule.td
View File

@ -27,13 +27,13 @@ def ReadInt2Fpu : SchedRead;
// load + WriteRMW.
def WriteRMW : SchedWrite;
// Helper to set SchedWrite ExePorts/Latency/ReleaseAtCycles/NumMicroOps.
// Helper to set SchedWrite ExePorts/Latency/ResourceCycles/NumMicroOps.
multiclass X86WriteRes<SchedWrite SchedRW,
list<ProcResourceKind> ExePorts,
int Lat, list<int> Res, int UOps> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}

136
llvm/lib/Target/X86/X86ScheduleAtom.td
View File

@ -62,14 +62,14 @@ multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant.
def : WriteRes<SchedRW, RRPorts> {
let Latency = RRLat;
let ReleaseAtCycles = RRRes;
let ResourceCycles = RRRes;
let NumMicroOps = RRUOps;
}
// Memory variant.
def : WriteRes<SchedRW.Folded, RMPorts> {
let Latency = RMLat;
let ReleaseAtCycles = RMRes;
let ResourceCycles = RMRes;
let NumMicroOps = RMUOps;
}
}
@ -122,11 +122,11 @@ defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move
def : WriteRes<WriteSETCC, [AtomPort01]>;
def : WriteRes<WriteSETCCStore, [AtomPort01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
@ -462,10 +462,10 @@ defm : X86WriteResPairUnsupported<WritePCmpEStrM>;
// MOVMSK Instructions.
////////////////////////////////////////////////////////////////////////////////
def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
defm : X86WriteResUnsupported<WriteVecMOVMSKY>;
def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ReleaseAtCycles = [3]; }
def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; }
////////////////////////////////////////////////////////////////////////////////
// AES instructions.
@ -505,7 +505,7 @@ defm : X86WriteRes<WriteSTMXCSR, [AtomPort0,AtomPort1], 15, [15,15], 4>;
// Port0
def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def : InstRW<[AtomWrite0_1], (instrs XAM_F, LD_Frr,
MOVSX64rr32)>;
@ -517,14 +517,14 @@ def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|6
// Port1
def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>;
def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>;
def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> {
let Latency = 5;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
}
def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,
MMX_CVTPS2PIrr, MMX_CVTTPS2PIrr)>;
@ -532,7 +532,7 @@ def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm,
// Port0 and Port1
def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
let Latency = 1;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
}
def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
POP16rmr, POP32rmr, POP64rmr,
@ -546,41 +546,41 @@ def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",
def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
let Latency = 5;
let ReleaseAtCycles = [5, 5];
let ResourceCycles = [5, 5];
}
def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIrm, MMX_CVTTPS2PIrm)>;
def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>;
def AtomWrite0_1_7 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 7;
let ReleaseAtCycles = [6,6];
let ResourceCycles = [6,6];
}
def : InstRW<[AtomWrite0_1_7], (instregex "CVTSI642SDrm(_Int)?")>;
def AtomWrite0_1_7_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 7;
let ReleaseAtCycles = [8,8];
let ResourceCycles = [8,8];
let NumMicroOps = 4;
}
def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrr(_Int)?")>;
def AtomWrite0_1_8_4 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 8;
let ReleaseAtCycles = [8,8];
let ResourceCycles = [8,8];
let NumMicroOps = 4;
}
def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrm(_Int)?")>;
def AtomWrite0_1_9 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 9;
let ReleaseAtCycles = [9,9];
let ResourceCycles = [9,9];
let NumMicroOps = 4;
}
def : InstRW<[AtomWrite0_1_9], (instregex "CVT(T)?SS2SI64rr(_Int)?")>;
def AtomWrite0_1_10 : SchedWriteRes<[AtomPort0,AtomPort1]> {
let Latency = 10;
let ReleaseAtCycles = [11,11];
let ResourceCycles = [11,11];
let NumMicroOps = 5;
}
def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>;
@ -588,7 +588,7 @@ def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>;
// Port0 or Port1
def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
LFENCE,
@ -597,7 +597,7 @@ def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT,
def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r,
PUSH16rmm, PUSH32rmm, PUSH64rmm,
@ -614,7 +614,7 @@ def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>;
def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> {
let Latency = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm,
CMPSB, CMPSL, CMPSQ, CMPSW,
@ -630,7 +630,7 @@ def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm",
def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO,
JCXZ, JECXZ, JRCXZ,
@ -640,14 +640,14 @@ def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm",
def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> {
let Latency = 5;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
}
def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>;
def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>;
def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> {
let Latency = 6;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
}
def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT,
SHLD16rrCL, SHRD16rrCL,
@ -659,13 +659,13 @@ def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m",
def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> {
let Latency = 7;
let ReleaseAtCycles = [7];
let ResourceCycles = [7];
}
def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>;
def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> {
let Latency = 8;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def : InstRW<[AtomWrite01_8], (instrs LOOPE,
PUSHA16, PUSHA32,
@ -674,7 +674,7 @@ def : InstRW<[AtomWrite01_8], (instrs LOOPE,
def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
let Latency = 9;
let ReleaseAtCycles = [9];
let ResourceCycles = [9];
}
def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
PUSHF16, PUSHF32, PUSHF64,
@ -686,256 +686,256 @@ def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F")>;
def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> {
let Latency = 10;
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
}
def : SchedAlias<WriteFLDC, AtomWrite01_10>;
def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> {
let Latency = 11;
let ReleaseAtCycles = [11];
let ResourceCycles = [11];
}
def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>;
def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>;
def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> {
let Latency = 13;
let ReleaseAtCycles = [13];
let ResourceCycles = [13];
}
def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>;
def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> {
let Latency = 14;
let ReleaseAtCycles = [14];
let ResourceCycles = [14];
}
def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>;
def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> {
let Latency = 17;
let ReleaseAtCycles = [17];
let ResourceCycles = [17];
}
def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>;
def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> {
let Latency = 18;
let ReleaseAtCycles = [18];
let ResourceCycles = [18];
}
def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>;
def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> {
let Latency = 20;
let ReleaseAtCycles = [20];
let ResourceCycles = [20];
}
def : InstRW<[AtomWrite01_20], (instrs DAS)>;
def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> {
let Latency = 21;
let ReleaseAtCycles = [21];
let ResourceCycles = [21];
}
def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>;
def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> {
let Latency = 22;
let ReleaseAtCycles = [22];
let ResourceCycles = [22];
}
def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>;
def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> {
let Latency = 23;
let ReleaseAtCycles = [23];
let ResourceCycles = [23];
}
def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>;
def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> {
let Latency = 25;
let ReleaseAtCycles = [25];
let ResourceCycles = [25];
}
def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>;
def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> {
let Latency = 26;
let ReleaseAtCycles = [26];
let ResourceCycles = [26];
}
def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>;
def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> {
let Latency = 29;
let ReleaseAtCycles = [29];
let ResourceCycles = [29];
}
def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>;
def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> {
let Latency = 30;
let ReleaseAtCycles = [30];
let ResourceCycles = [30];
}
def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>;
def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> {
let Latency = 32;
let ReleaseAtCycles = [32];
let ResourceCycles = [32];
}
def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>;
def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> {
let Latency = 45;
let ReleaseAtCycles = [45];
let ResourceCycles = [45];
}
def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>;
def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> {
let Latency = 46;
let ReleaseAtCycles = [46];
let ResourceCycles = [46];
}
def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>;
def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> {
let Latency = 48;
let ReleaseAtCycles = [48];
let ResourceCycles = [48];
}
def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>;
def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> {
let Latency = 55;
let ReleaseAtCycles = [55];
let ResourceCycles = [55];
}
def : InstRW<[AtomWrite01_55], (instrs FPREM)>;
def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> {
let Latency = 59;
let ReleaseAtCycles = [59];
let ResourceCycles = [59];
}
def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>;
def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> {
let Latency = 63;
let ReleaseAtCycles = [63];
let ResourceCycles = [63];
}
def : InstRW<[AtomWrite01_63], (instrs FNINIT)>;
def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> {
let Latency = 68;
let ReleaseAtCycles = [68];
let ResourceCycles = [68];
}
def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>;
def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> {
let Latency = 71;
let ReleaseAtCycles = [71];
let ResourceCycles = [71];
}
def : InstRW<[AtomWrite01_71], (instrs FPREM1,
INVLPG, INVLPGA32, INVLPGA64)>;
def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> {
let Latency = 72;
let ReleaseAtCycles = [72];
let ResourceCycles = [72];
}
def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>;
def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> {
let Latency = 74;
let ReleaseAtCycles = [74];
let ResourceCycles = [74];
}
def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>;
def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> {
let Latency = 77;
let ReleaseAtCycles = [77];
let ResourceCycles = [77];
}
def : InstRW<[AtomWrite01_77], (instrs FSCALE)>;
def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> {
let Latency = 78;
let ReleaseAtCycles = [78];
let ResourceCycles = [78];
}
def : InstRW<[AtomWrite01_78], (instrs RDMSR)>;
def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> {
let Latency = 79;
let ReleaseAtCycles = [79];
let ResourceCycles = [79];
}
def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$",
"LRETI?(16|32|64)")>;
def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> {
let Latency = 92;
let ReleaseAtCycles = [92];
let ResourceCycles = [92];
}
def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>;
def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> {
let Latency = 94;
let ReleaseAtCycles = [94];
let ResourceCycles = [94];
}
def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>;
def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> {
let Latency = 99;
let ReleaseAtCycles = [99];
let ResourceCycles = [99];
}
def : InstRW<[AtomWrite01_99], (instrs F2XM1)>;
def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> {
let Latency = 121;
let ReleaseAtCycles = [121];
let ResourceCycles = [121];
}
def : InstRW<[AtomWrite01_121], (instrs CPUID)>;
def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> {
let Latency = 127;
let ReleaseAtCycles = [127];
let ResourceCycles = [127];
}
def : InstRW<[AtomWrite01_127], (instrs INT)>;
def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> {
let Latency = 130;
let ReleaseAtCycles = [130];
let ResourceCycles = [130];
}
def : InstRW<[AtomWrite01_130], (instrs INT3)>;
def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> {
let Latency = 140;
let ReleaseAtCycles = [140];
let ResourceCycles = [140];
}
def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>;
def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> {
let Latency = 141;
let ReleaseAtCycles = [141];
let ResourceCycles = [141];
}
def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>;
def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> {
let Latency = 146;
let ReleaseAtCycles = [146];
let ResourceCycles = [146];
}
def : InstRW<[AtomWrite01_146], (instrs FYL2X)>;
def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> {
let Latency = 147;
let ReleaseAtCycles = [147];
let ResourceCycles = [147];
}
def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>;
def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> {
let Latency = 168;
let ReleaseAtCycles = [168];
let ResourceCycles = [168];
}
def : InstRW<[AtomWrite01_168], (instrs FPTAN)>;
def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> {
let Latency = 174;
let ReleaseAtCycles = [174];
let ResourceCycles = [174];
}
def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>;
def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> {
let Latency = 183;
let ReleaseAtCycles = [183];
let ResourceCycles = [183];
}
def : InstRW<[AtomWrite01_183], (instrs FPATAN)>;
def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> {
let Latency = 202;
let ReleaseAtCycles = [202];
let ResourceCycles = [202];
}
def : InstRW<[AtomWrite01_202], (instrs WRMSR)>;

134
llvm/lib/Target/X86/X86ScheduleBdVer2.td
View File

@ -192,7 +192,7 @@ multiclass PdWriteRes<SchedWrite SchedRW,
list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
@ -265,16 +265,16 @@ def : WriteRes<WriteRMW, [PdStore]>;
// Loads, stores, and moves, not folded with other operations.
////////////////////////////////////////////////////////////////////////////////
def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ReleaseAtCycles = [2]; }
def : WriteRes<WriteLoad, [PdLoad]> { let Latency = 5; let ResourceCycles = [2]; }
def : WriteRes<WriteStore, [PdStore]>;
def : WriteRes<WriteStoreNT, [PdStore]>;
def : WriteRes<WriteMove, [PdEX01]> { let ReleaseAtCycles = [2]; }
def : WriteRes<WriteMove, [PdEX01]> { let ResourceCycles = [2]; }
defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>;
// Load/store MXCSR.
// FIXME: These are copy and pasted from WriteLoad/Store.
def : WriteRes<WriteLDMXCSR, [PdLoad]> { let Latency = 5; }
def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ReleaseAtCycles = [18]; }
def : WriteRes<WriteSTMXCSR, [PdStore]> { let NumMicroOps = 2; let ResourceCycles = [18]; }
// Treat misc copies as a move.
def : InstRW<[WriteMove], (instrs COPY)>;
@ -308,7 +308,7 @@ def : InstRW<[PdWriteXLAT], (instrs XLAT)>;
def PdWriteLARrr : SchedWriteRes<[PdEX01]> {
let Latency = 184;
let ReleaseAtCycles = [375];
let ResourceCycles = [375];
let NumMicroOps = 45;
}
def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
@ -316,7 +316,7 @@ def : InstRW<[PdWriteLARrr], (instregex "LAR(16|32|64)rr",
// Nops don't have dependencies, so there's no actual latency, but we set this
// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
def : WriteRes<WriteNop, [PdEX01]> { let ReleaseAtCycles = [2]; }
def : WriteRes<WriteNop, [PdEX01]> { let ResourceCycles = [2]; }
////////////////////////////////////////////////////////////////////////////////
// Arithmetic.
@ -326,21 +326,21 @@ defm : PdWriteResExPair<WriteALU, [PdEX01], 1, [2]>;
def PdWriteALURMW : SchedWriteRes<[PdLoad, PdEX01, PdStore]> {
let Latency = 6;
let ReleaseAtCycles = [3, 2, 1];
let ResourceCycles = [3, 2, 1];
let NumMicroOps = 1;
}
def : SchedAlias<WriteALURMW, PdWriteALURMW>;
def PdWriteLXADD : SchedWriteRes<[PdEX01]> {
let Latency = 6;
let ReleaseAtCycles = [88];
let ResourceCycles = [88];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteLXADD], (instrs LXADD8, LXADD16, LXADD32, LXADD64)>;
def PdWriteBMI1 : SchedWriteRes<[PdEX01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBMI1],
@ -352,7 +352,7 @@ def : InstRW<[PdWriteBMI1],
def PdWriteBMI1m : SchedWriteRes<[PdLoad, PdEX01]> {
let Latency = 6;
let ReleaseAtCycles = [3, 3];
let ResourceCycles = [3, 3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBMI1m],
@ -365,7 +365,7 @@ def : InstRW<[PdWriteBMI1m],
defm : PdWriteResExPair<WriteADC, [PdEX01], 1, [2]>;
def PdWriteADCSBB64ri32 : SchedWriteRes<[PdEX01]> {
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
}
def : InstRW<[PdWriteADCSBB64ri32], (instrs ADC64ri32, SBB64ri32)>;
@ -377,21 +377,21 @@ defm : PdWriteRes<WriteXCHG, [PdEX1], 1, [],
def PdWriteCMPXCHG8rr : SchedWriteRes<[PdEX1]> {
let Latency = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 3;
}
def : InstRW<[PdWriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
def PdWriteCMPXCHG8rm : SchedWriteRes<[PdEX1]> {
let Latency = 3;
let ReleaseAtCycles = [23];
let ResourceCycles = [23];
let NumMicroOps = 5;
}
def : InstRW<[PdWriteCMPXCHG8rm], (instrs CMPXCHG8rm)>;
def PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm : SchedWriteRes<[PdEX1]> {
let Latency = 3;
let ReleaseAtCycles = [21];
let ResourceCycles = [21];
let NumMicroOps = 6;
}
def : InstRW<[PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm],
@ -399,21 +399,21 @@ def : InstRW<[PdWriteCMPXCHG16rm_CMPXCHG32rm_CMPXCHG64rm],
def PdWriteCMPXCHG8B : SchedWriteRes<[PdEX1]> {
let Latency = 3;
let ReleaseAtCycles = [26];
let ResourceCycles = [26];
let NumMicroOps = 18;
}
def : InstRW<[PdWriteCMPXCHG8B], (instrs CMPXCHG8B)>;
def PdWriteCMPXCHG16B : SchedWriteRes<[PdEX1]> {
let Latency = 3;
let ReleaseAtCycles = [69];
let ResourceCycles = [69];
let NumMicroOps = 22;
}
def : InstRW<[PdWriteCMPXCHG16B], (instrs CMPXCHG16B)>;
def PdWriteXADDm : SchedWriteRes<[PdEX1]> {
let Latency = 6;
let ReleaseAtCycles = [20];
let ResourceCycles = [20];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteXADDm], (instrs XADD8rm, XADD16rm, XADD32rm, XADD64rm)>;
@ -449,21 +449,21 @@ defm : PdWriteResExPair<WriteCRC32, [PdEX01], 2, [4],
def PdWriteCRC32r32r16 : SchedWriteRes<[PdEX01]> {
let Latency = 5;
let ReleaseAtCycles = [10];
let ResourceCycles = [10];
let NumMicroOps = 5;
}
def : InstRW<[PdWriteCRC32r32r16], (instrs CRC32r32r16)>;
def PdWriteCRC32r32r32 : SchedWriteRes<[PdEX01]> {
let Latency = 6;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 7;
}
def : InstRW<[PdWriteCRC32r32r32], (instrs CRC32r32r32)>;
def PdWriteCRC32r64r64 : SchedWriteRes<[PdEX01]> {
let Latency = 10;
let ReleaseAtCycles = [17];
let ResourceCycles = [17];
let NumMicroOps = 11;
}
def : InstRW<[PdWriteCRC32r64r64], (instrs CRC32r64r64)>;
@ -472,7 +472,7 @@ defm : PdWriteResExPair<WriteCMOV, [PdEX01]>; // Conditional move.
def PdWriteCMOVm : SchedWriteRes<[PdLoad, PdEX01]> {
let Latency = 5;
let ReleaseAtCycles = [3, 3];
let ResourceCycles = [3, 3];
let NumMicroOps = 2;
}
@ -494,7 +494,7 @@ def : WriteRes<WriteSETCC, [PdEX01]>; // Setcc.
def : WriteRes<WriteSETCCStore, [PdEX01, PdStore]>;
def PdWriteSETGEmSETGmSETLEmSETLm : SchedWriteRes<[PdEX01]> {
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
@ -511,14 +511,14 @@ defm : PdWriteRes<WriteLAHFSAHF, [PdEX01], 2, [4], 2>;
def PdWriteLAHF : SchedWriteRes<[PdEX01]> {
let Latency = 2;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteLAHF], (instrs LAHF)>;
def PdWriteSAHF : SchedWriteRes<[PdEX01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteSAHF], (instrs SAHF)>;
@ -532,24 +532,24 @@ defm : PdWriteRes<WriteBitTestSetRegLd, [PdEX01, PdLoad], 6, [1, 1], 10>;
def PdWriteBTSIm : SchedWriteRes<[PdEX01, PdLoad]> {
let Latency = 7;
let ReleaseAtCycles = [42, 1];
let ResourceCycles = [42, 1];
let NumMicroOps = 4;
}
def : SchedAlias<WriteBitTestSetImmRMW, PdWriteBTSIm>;
def PdWriteBTSRm : SchedWriteRes<[PdEX01, PdLoad]> {
let Latency = 7;
let ReleaseAtCycles = [44, 1];
let ResourceCycles = [44, 1];
let NumMicroOps = 10;
}
def : SchedAlias<WriteBitTestSetRegRMW, PdWriteBTSRm>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [PdEX01]> { let ReleaseAtCycles = [2]; }
def : WriteRes<WriteLEA, [PdEX01]> { let ResourceCycles = [2]; }
// This write is used for slow LEA instructions.
def PdWrite3OpsLEA : SchedWriteRes<[PdEX01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// On Piledriver, a slow LEA is either a 3Ops LEA (base, index, offset),
@ -574,7 +574,7 @@ def PdWriteLEA : SchedWriteVariant<[
def : InstRW<[PdWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def PdWriteLEA16r : SchedWriteRes<[PdEX01]> {
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteLEA16r], (instrs LEA16r)>;
@ -593,14 +593,14 @@ defm : PdWriteResExPair<WriteBZHI, [PdEX01]>;
def PdWriteBEXTRI : SchedWriteRes<[PdEX01]> {
let Latency = 2;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBEXTRI], (instrs BEXTRI32ri, BEXTRI64ri)>;
def PdWriteBEXTRIm : SchedWriteRes<[PdEX01]> {
let Latency = 2;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteBEXTRIm], (instrs BEXTRI32mi, BEXTRI64mi)>;
@ -616,56 +616,56 @@ defm : PdWriteResExPair<WriteRotateCL, [PdEX01]>;
def PdWriteRCL8rCL : SchedWriteRes<[PdEX01]> {
let Latency = 12;
let ReleaseAtCycles = [24];
let ResourceCycles = [24];
let NumMicroOps = 26;
}
def : InstRW<[PdWriteRCL8rCL], (instrs RCL8rCL)>;
def PdWriteRCR8ri : SchedWriteRes<[PdEX01]> {
let Latency = 12;
let ReleaseAtCycles = [23];
let ResourceCycles = [23];
let NumMicroOps = 23;
}
def : InstRW<[PdWriteRCR8ri], (instrs RCR8ri)>;
def PdWriteRCR8rCL : SchedWriteRes<[PdEX01]> {
let Latency = 11;
let ReleaseAtCycles = [22];
let ResourceCycles = [22];
let NumMicroOps = 24;
}
def : InstRW<[PdWriteRCR8rCL], (instrs RCR8rCL)>;
def PdWriteRCL16rCL : SchedWriteRes<[PdEX01]> {
let Latency = 10;
let ReleaseAtCycles = [20];
let ResourceCycles = [20];
let NumMicroOps = 22;
}
def : InstRW<[PdWriteRCL16rCL], (instrs RCL16rCL)>;
def PdWriteRCR16ri : SchedWriteRes<[PdEX01]> {
let Latency = 10;
let ReleaseAtCycles = [19];
let ResourceCycles = [19];
let NumMicroOps = 19;
}
def : InstRW<[PdWriteRCR16ri], (instrs RCR16ri)>;
def PdWriteRCL3264rCL : SchedWriteRes<[PdEX01]> {
let Latency = 7;
let ReleaseAtCycles = [14];
let ResourceCycles = [14];
let NumMicroOps = 17;
}
def : InstRW<[PdWriteRCL3264rCL], (instrs RCL32rCL, RCL64rCL)>;
def PdWriteRCR3264rCL : SchedWriteRes<[PdEX01]> {
let Latency = 7;
let ReleaseAtCycles = [13];
let ResourceCycles = [13];
let NumMicroOps = 16;
}
def : InstRW<[PdWriteRCR3264rCL], (instrs RCR32rCL, RCR64rCL)>;
def PdWriteRCR32riRCR64ri : SchedWriteRes<[PdEX01]> {
let Latency = 7;
let ReleaseAtCycles = [14];
let ResourceCycles = [14];
let NumMicroOps = 15;
}
def : InstRW<[PdWriteRCR32riRCR64ri], (instrs RCR32ri, RCR64ri)>;
@ -673,28 +673,28 @@ def : InstRW<[PdWriteRCR32riRCR64ri], (instrs RCR32ri, RCR64ri)>;
def PdWriteRCR16rCL : SchedWriteRes<[PdEX01]> {
let Latency = 9;
let ReleaseAtCycles = [18];
let ResourceCycles = [18];
let NumMicroOps = 20;
}
def : InstRW<[PdWriteRCR16rCL], (instrs RCR16rCL)>;
def PdWriteRCL16ri : SchedWriteRes<[PdEX01]> {
let Latency = 11;
let ReleaseAtCycles = [21];
let ResourceCycles = [21];
let NumMicroOps = 21;
}
def : InstRW<[PdWriteRCL16ri], (instrs RCL16ri)>;
def PdWriteRCL3264ri : SchedWriteRes<[PdEX01]> {
let Latency = 8;
let ReleaseAtCycles = [15];
let ResourceCycles = [15];
let NumMicroOps = 16;
}
def : InstRW<[PdWriteRCL3264ri], (instrs RCL32ri, RCL64ri)>;
def PdWriteRCL8ri : SchedWriteRes<[PdEX01]> {
let Latency = 13;
let ReleaseAtCycles = [25];
let ResourceCycles = [25];
let NumMicroOps = 25;
}
def : InstRW<[PdWriteRCL8ri], (instrs RCL8ri)>;
@ -705,7 +705,7 @@ defm : PdWriteRes<WriteSHDrrcl, [PdEX01], 3, [8], 7>;
def PdWriteSHLD16rrCLSHLD32rrCLSHRD32rrCL : SchedWriteRes<[PdEX01]> {
let Latency = 3;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[PdWriteSHLD16rrCLSHLD32rrCLSHRD32rrCL], (instrs SHLD16rrCL,
@ -736,7 +736,7 @@ defm : PdWriteRes<WriteFStoreY, [PdStore, PdFPU23, PdFPSTO], 1, [1, 3
def PdWriteMOVHPm : SchedWriteRes<[PdStore, PdFPU23, PdFPSTO]> {
let Latency = 2;
let ReleaseAtCycles = [1, 3, 1];
let ResourceCycles = [1, 3, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteMOVHPm], (instrs MOVHPDmr, MOVHPSmr, VMOVHPDmr, VMOVHPSmr)>;
@ -769,7 +769,7 @@ defm : X86WriteResPairUnsupported<WriteFAddZ>;
def PdWriteX87Add: SchedWriteRes<[PdLoad, PdFPU0, PdFPFMA]> {
let Latency = 5;
let ReleaseAtCycles = [3, 1, 10];
let ResourceCycles = [3, 1, 10];
}
def : InstRW<[PdWriteX87Add], (instrs ADD_FI16m, ADD_FI32m, ADD_F32m, ADD_F64m,
SUB_FI16m, SUB_FI32m, SUB_F32m, SUB_F64m,
@ -808,7 +808,7 @@ defm : X86WriteResPairUnsupported<WriteFMulZ>;
def PdWriteX87Mul: SchedWriteRes<[PdLoad, PdFPU1, PdFPFMA]> {
let Latency = 5;
let ReleaseAtCycles = [3, 1, 10];
let ResourceCycles = [3, 1, 10];
}
def : InstRW<[PdWriteX87Mul], (instrs MUL_FI16m, MUL_FI32m, MUL_F32m, MUL_F64m)>;
@ -829,7 +829,7 @@ defm : PdWriteResYMMPair<WriteDPPSY, [PdFPU1, PdFPFMA], 27, [2, 25], /*or
def PdWriteVDPPSrri : SchedWriteRes<[PdFPU1, PdFPFMA]> {
let Latency = 27;
let ReleaseAtCycles = [1, 14];
let ResourceCycles = [1, 14];
let NumMicroOps = 17;
}
def : InstRW<[PdWriteVDPPSrri], (instrs VDPPSrri)>;
@ -851,7 +851,7 @@ defm : X86WriteResPairUnsupported<WriteFDivZ>;
def PdWriteX87Div: SchedWriteRes<[PdLoad, PdFPU0, PdFPFMA]> {
let Latency = 9;
let ReleaseAtCycles = [3, 1, 18];
let ResourceCycles = [3, 1, 18];
}
def : InstRW<[PdWriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
DIVR_FI16m, DIVR_FI32m,
@ -882,21 +882,21 @@ defm : X86WriteResPairUnsupported<WriteFRndZ>;
def PdWriteVFRCZP : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 10;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVFRCZP], (instrs VFRCZPDrr, VFRCZPSrr)>;
def PdWriteVFRCZS : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 10;
let ReleaseAtCycles = [10, 1];
let ResourceCycles = [10, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVFRCZS], (instrs VFRCZSDrr, VFRCZSSrr)>;
def PdWriteVFRCZm : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 15;
let ReleaseAtCycles = [2, 1];
let ResourceCycles = [2, 1];
let NumMicroOps = 3;
}
def : InstRW<[PdWriteVFRCZm], (instrs VFRCZPDrm, VFRCZPSrm,
@ -904,14 +904,14 @@ def : InstRW<[PdWriteVFRCZm], (instrs VFRCZPDrm, VFRCZPSrm,
def PdWriteVFRCZY : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 10;
let ReleaseAtCycles = [3, 1];
let ResourceCycles = [3, 1];
let NumMicroOps = 4;
}
def : InstRW<[PdWriteVFRCZY], (instrs VFRCZPSYrr, VFRCZPDYrr)>;
def PdWriteVFRCZYm : SchedWriteRes<[PdFPU1, PdFPSTO]> {
let Latency = 15;
let ReleaseAtCycles = [4, 1];
let ResourceCycles = [4, 1];
let NumMicroOps = 8;
}
def : InstRW<[PdWriteVFRCZYm], (instrs VFRCZPSYrm, VFRCZPDYrm)>;
@ -930,7 +930,7 @@ defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
def PdWriteVBROADCASTF128 : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 7;
let ReleaseAtCycles = [1, 3];
let ResourceCycles = [1, 3];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVBROADCASTF128], (instrs VBROADCASTF128)>;
@ -952,27 +952,27 @@ defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
def PdWriteVEXTRACTF128rr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[PdWriteVEXTRACTF128rr], (instrs VEXTRACTF128rr)>;
def PdWriteVEXTRACTF128mr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 7;
let ReleaseAtCycles = [1, 4];
let ResourceCycles = [1, 4];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVEXTRACTF128mr], (instrs VEXTRACTF128mr)>;
def PdWriteVPERM2F128rr : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 4;
let ReleaseAtCycles = [1, 6];
let ResourceCycles = [1, 6];
let NumMicroOps = 8;
}
def : InstRW<[PdWriteVPERM2F128rr], (instrs VPERM2F128rr)>;
def PdWriteVPERM2F128rm : SchedWriteRes<[PdFPU01, PdFPFMA]> {
let Latency = 8; // 4 + 4
let ReleaseAtCycles = [1, 8];
let ResourceCycles = [1, 8];
let NumMicroOps = 10;
}
def : InstRW<[PdWriteVPERM2F128rm], (instrs VPERM2F128rm)>;
@ -1012,7 +1012,7 @@ defm : PdWriteResXMMPair<WriteCvtI2SD, [PdFPU0, PdFPCVT, PdFPSTO], 4, [], 2>;
def PdWriteCVTSI642SDrr_CVTSI642SSrr_CVTSI2SDr_CVTSI2SSrr : SchedWriteRes<[PdFPU0, PdFPCVT, PdFPSTO]> {
let Latency = 13;
let ReleaseAtCycles = [1, 3, 1];
let ResourceCycles = [1, 3, 1];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteCVTSI642SDrr_CVTSI642SSrr_CVTSI2SDr_CVTSI2SSrr], (instrs CVTSI642SDrr, CVTSI642SSrr, CVTSI2SDrr, CVTSI2SSrr)>;
@ -1161,13 +1161,13 @@ defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
def PdWriteVPPERM : SchedWriteRes<[PdFPU1, PdFPXBR]> {
let Latency = 2;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
}
def : InstRW<[PdWriteVPPERM], (instrs VPPERMrrr, VPPERMrrr_REV)>;
def PdWriteVPPERMLd : SchedWriteRes<[PdFPU1, PdFPXBR, PdLoad]> {
let Latency = 7;
let ReleaseAtCycles = [1, 1, 3];
let ResourceCycles = [1, 1, 3];
}
def : InstRW<[PdWriteVPPERMLd], (instrs VPPERMrrm, VPPERMrmr)>;
@ -1208,7 +1208,7 @@ defm : PdWriteRes<WriteVecExtractSt, [PdFPU1, PdFPSTO, PdStore], 13, [2, 1, 1],
def PdWriteEXTRQ : SchedWriteRes<[PdFPU01, PdFPMAL]> {
let Latency = 3;
let ReleaseAtCycles = [1, 3];
let ResourceCycles = [1, 3];
}
def : InstRW<[PdWriteEXTRQ], (instrs EXTRQ, EXTRQI)>;
@ -1277,7 +1277,7 @@ defm : PdWriteResXMMPair<WriteCLMul, [PdFPU0, PdFPMMA], 12, [1, 7], 5, 1>;
def PdWriteVPCLMULQDQrr : SchedWriteRes<[PdFPU0, PdFPMMA]> {
let Latency = 12;
let ReleaseAtCycles = [1, 7];
let ResourceCycles = [1, 7];
let NumMicroOps = 6;
}
def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
@ -1288,13 +1288,13 @@ def : InstRW<[PdWriteVPCLMULQDQrr], (instrs VPCLMULQDQrr)>;
def PdWriteINSERTQ : SchedWriteRes<[PdFPU01, PdFPMAL]> {
let Latency = 3;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[PdWriteINSERTQ], (instrs INSERTQ)>;
def PdWriteINSERTQI : SchedWriteRes<[PdFPU01, PdFPMAL]> {
let Latency = 3;
let ReleaseAtCycles = [1, 3];
let ResourceCycles = [1, 3];
}
def : InstRW<[PdWriteINSERTQI], (instrs INSERTQI)>;
@ -1304,7 +1304,7 @@ def : InstRW<[PdWriteINSERTQI], (instrs INSERTQI)>;
def PdWriteVBROADCASTYLd : SchedWriteRes<[PdLoad, PdFPU01, PdFPFMA]> {
let Latency = 6;
let ReleaseAtCycles = [1, 2, 4];
let ResourceCycles = [1, 2, 4];
let NumMicroOps = 2;
}
def : InstRW<[PdWriteVBROADCASTYLd, ReadAfterLd], (instrs VBROADCASTSDYrm,

50
llvm/lib/Target/X86/X86ScheduleBtVer2.td
View File

@ -125,7 +125,7 @@ multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -133,7 +133,7 @@ multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 3);
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -145,7 +145,7 @@ multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -153,7 +153,7 @@ multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 5);
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -165,7 +165,7 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -173,7 +173,7 @@ multiclass JWriteResYMMPair<X86FoldableSchedWrite SchedRW,
// latency.
def : WriteRes<SchedRW.Folded, !listconcat([JLAGU], ExePorts)> {
let Latency = !add(Lat, 5);
let ReleaseAtCycles = !listconcat([2], Res);
let ResourceCycles = !listconcat([2], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -313,49 +313,49 @@ def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
def JWriteCMPXCHG8rr : SchedWriteRes<[JALU01]> {
let Latency = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 3;
}
def JWriteLOCK_CMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 16;
let ReleaseAtCycles = [3,16,16];
let ResourceCycles = [3,16,16];
let NumMicroOps = 5;
}
def JWriteLOCK_CMPXCHGrm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 17;
let ReleaseAtCycles = [3,17,17];
let ResourceCycles = [3,17,17];
let NumMicroOps = 6;
}
def JWriteCMPXCHG8rm : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 11;
let ReleaseAtCycles = [3,1,1];
let ResourceCycles = [3,1,1];
let NumMicroOps = 5;
}
def JWriteCMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 11;
let ReleaseAtCycles = [3,1,1];
let ResourceCycles = [3,1,1];
let NumMicroOps = 18;
}
def JWriteCMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 32;
let ReleaseAtCycles = [6,1,1];
let ResourceCycles = [6,1,1];
let NumMicroOps = 28;
}
def JWriteLOCK_CMPXCHG8B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 19;
let ReleaseAtCycles = [3,19,19];
let ResourceCycles = [3,19,19];
let NumMicroOps = 18;
}
def JWriteLOCK_CMPXCHG16B : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 38;
let ReleaseAtCycles = [6,38,38];
let ResourceCycles = [6,38,38];
let NumMicroOps = 28;
}
@ -394,7 +394,7 @@ def : InstRW<[JWriteCMPXCHGVariant,
def JWriteLOCK_ALURMW : SchedWriteRes<[JALU01, JLAGU, JSAGU]> {
let Latency = 19;
let ReleaseAtCycles = [1,19,19];
let ResourceCycles = [1,19,19];
let NumMicroOps = 1;
}
@ -409,7 +409,7 @@ def : InstRW<[JWriteLOCK_ALURMWVariant], (instrs INC8m, INC16m, INC32m, INC64m,
def JWriteXCHG8rr_XADDrr : SchedWriteRes<[JALU01]> {
let Latency = 2;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 3;
}
def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
@ -434,7 +434,7 @@ def : InstRW<[JWriteXCHG8rr_XADDrr], (instrs XCHG8rr, XADD8rr, XADD16rr,
// latency is assumed to be 3cy.
def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 3; // load-to-use latency
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 3;
}
@ -451,7 +451,7 @@ def JWriteXADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
// execution. This write is used to specifically set that operand latency.
def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 11;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 3;
}
@ -463,19 +463,19 @@ def JWriteLOCK_XADDrm_XCHG_Part : SchedWriteRes<[JALU01]> {
// set the instruction latency to 16cy.
def JWriteXCHGrm_XCHG_Part : SchedWriteRes<[JALU01]> {
let Latency = 11;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def JWriteXADDrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
let Latency = 11;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 1;
}
def JWriteXCHGrm_LdSt_Part : SchedWriteRes<[JLAGU, JSAGU]> {
let Latency = 16;
let ReleaseAtCycles = [16, 16];
let ResourceCycles = [16, 16];
let NumMicroOps = 1;
}
@ -798,7 +798,7 @@ defm : JWriteResFpuPair<WriteCLMul, [JFPU0, JVIMUL], 2>;
def JWriteINSERTQ: SchedWriteRes<[JFPU01, JVALU]> {
let Latency = 2;
let ReleaseAtCycles = [1, 4];
let ResourceCycles = [1, 4];
}
def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>;
@ -811,7 +811,7 @@ def : InstRW<[JWriteVecExtractF128], (instrs VEXTRACTF128rr)>;
def JWriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX]> {
let Latency = 6;
let ReleaseAtCycles = [1, 2, 4];
let ResourceCycles = [1, 2, 4];
let NumMicroOps = 2;
}
def : InstRW<[JWriteVBROADCASTYLd], (instrs VBROADCASTSDYrm,
@ -836,7 +836,7 @@ def : InstRW<[JWriteJVZEROUPPER], (instrs VZEROUPPER)>;
def JWriteMASKMOVDQU: SchedWriteRes<[JFPU0, JFPA, JFPU1, JSTC, JLAGU, JSAGU, JALU01]> {
let Latency = 34;
let ReleaseAtCycles = [1, 1, 2, 2, 2, 16, 42];
let ResourceCycles = [1, 1, 2, 2, 2, 16, 42];
let NumMicroOps = 63;
}
def : InstRW<[JWriteMASKMOVDQU], (instrs MASKMOVDQU, MASKMOVDQU64,
@ -960,7 +960,7 @@ def : InstRW<[JWriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def JSlowLEA16r : SchedWriteRes<[JALU01]> {
let Latency = 3;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
}
def : InstRW<[JSlowLEA16r], (instrs LEA16r)>;

16
llvm/lib/Target/X86/X86ScheduleSLM.td
View File

@ -66,7 +66,7 @@ multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant is using a single cycle on ExePort.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -74,7 +74,7 @@ multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
// the latency (default = 3).
def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ReleaseAtCycles = !listconcat([1], Res);
let ResourceCycles = !listconcat([1], Res);
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -139,7 +139,7 @@ defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional mo
def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
// FIXME Latency and NumMicrOps?
let ReleaseAtCycles = [2,1];
let ResourceCycles = [2,1];
}
defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV0, SLM_IEC_RSV1], 1, [1,1], 1>;
@ -413,7 +413,7 @@ def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]> {
def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
let Latency = 4;
let NumMicroOps = 5;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
////////////////////////////////////////////////////////////////////////////////
@ -465,7 +465,7 @@ def : WriteRes<WriteNop, []>;
def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
let Latency = 4;
let NumMicroOps = 2;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
}
def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
MMX_PSUBQrr, PSUBQrr,
@ -474,14 +474,14 @@ def: InstRW<[SLMWriteResGroup1rr], (instrs MMX_PADDQrr, PADDQrr,
def SLMWriteResGroup2rr : SchedWriteRes<[SLM_FPC_RSV0]> {
let Latency = 5;
let NumMicroOps = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def: InstRW<[SLMWriteResGroup2rr], (instrs PCMPGTQrr)>;
def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
let Latency = 7;
let NumMicroOps = 3;
let ReleaseAtCycles = [1,8];
let ResourceCycles = [1,8];
}
def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
@ -491,7 +491,7 @@ def: InstRW<[SLMWriteResGroup1rm], (instrs MMX_PADDQrm, PADDQrm,
def SLMWriteResGroup2rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV0]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def: InstRW<[SLMWriteResGroup2rm], (instrs PCMPGTQrm)>;

44
llvm/lib/Target/X86/X86ScheduleZnver1.td
View File

@ -136,7 +136,7 @@ multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -144,7 +144,7 @@ multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -157,7 +157,7 @@ multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -165,7 +165,7 @@ multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 7).
def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -455,12 +455,12 @@ defm : ZnWriteResFpuPair<WriteVecInsert, [ZnFPU], 1>;
def : WriteRes<WriteVecExtract, [ZnFPU12, ZnFPU2]> {
let Latency = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : WriteRes<WriteVecExtractSt, [ZnAGU, ZnFPU12, ZnFPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2, 3];
let ResourceCycles = [1, 2, 3];
}
// MOVMSK Instructions.
@ -471,7 +471,7 @@ def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>;
def : WriteRes<WriteVecMOVMSKY, [ZnFPU2]> {
let NumMicroOps = 2;
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// AES Instructions.
@ -869,7 +869,7 @@ def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]>
{
let Latency = 12;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,3];
let ResourceCycles = [1,3];
}
// FICOM(P).
@ -910,12 +910,12 @@ def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>;
def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let NumMicroOps = 2;
let Latency = 8;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> {
let NumMicroOps = 2;
let Latency = 9;
let ReleaseAtCycles = [1, 3];
let ResourceCycles = [1, 3];
}
def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>;
def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
@ -938,7 +938,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[ZnWriteVPBROADCAST128Ld],
(instregex "VPBROADCAST(B|W)rm")>;
@ -947,7 +947,7 @@ def : InstRW<[ZnWriteVPBROADCAST128Ld],
def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[ZnWriteVPBROADCAST256Ld],
(instregex "VPBROADCAST(B|W)Yrm")>;
@ -977,7 +977,7 @@ def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>;
def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>;
@ -1004,14 +1004,14 @@ def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128,
def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> {
let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [5, 1, 2];
let ResourceCycles = [5, 1, 2];
}
// m32,x,i.
def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
@ -1027,12 +1027,12 @@ def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr,
def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> {
let Latency = 9;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
// VINSERTF128 / VINSERTI128.
// y,y,x,i.
@ -1051,7 +1051,7 @@ def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> {
def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// CVTPD2PS.
@ -1072,7 +1072,7 @@ def : SchedAlias<WriteCvtPD2PSLd, ZnWriteCVTPD2PSLd>;
def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def : SchedAlias<WriteCvtPD2PSYLd, ZnWriteCVTPD2PSYLd>;
// z,m512
@ -1121,7 +1121,7 @@ def : SchedAlias<WriteCvtSS2SD, ZnWriteCVTSS2SDr>;
def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> {
let Latency = 11;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : SchedAlias<WriteCvtSS2SDLd, ZnWriteCVTSS2SDLd>;
@ -1243,13 +1243,13 @@ def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>;
// x,x.
def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>;
// x,m.
def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> {
let Latency = 9;
let ReleaseAtCycles = [1,2];
let ResourceCycles = [1,2];
}
def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>;

32
llvm/lib/Target/X86/X86ScheduleZnver2.td
View File

@ -135,7 +135,7 @@ multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -143,7 +143,7 @@ multiclass Zn2WriteResPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 4).
def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -156,7 +156,7 @@ multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
// Register variant takes 1-cycle on Execution Port.
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
@ -164,7 +164,7 @@ multiclass Zn2WriteResFpuPair<X86FoldableSchedWrite SchedRW,
// adds LoadLat cycles to the latency (default = 7).
def : WriteRes<SchedRW.Folded, !listconcat([Zn2AGU], ExePorts)> {
let Latency = !add(Lat, LoadLat);
let ReleaseAtCycles = !if(!empty(Res), [], !listconcat([1], Res));
let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res));
let NumMicroOps = !add(UOps, LoadUOps);
}
}
@ -454,12 +454,12 @@ defm : Zn2WriteResFpuPair<WriteVecInsert, [Zn2FPU], 1>;
def : WriteRes<WriteVecExtract, [Zn2FPU12, Zn2FPU2]> {
let Latency = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : WriteRes<WriteVecExtractSt, [Zn2AGU, Zn2FPU12, Zn2FPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2, 3];
let ResourceCycles = [1, 2, 3];
}
// MOVMSK Instructions.
@ -470,7 +470,7 @@ def : WriteRes<WriteVecMOVMSK, [Zn2FPU2]>;
def : WriteRes<WriteVecMOVMSKY, [Zn2FPU2]> {
let NumMicroOps = 2;
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
}
// AES Instructions.
@ -879,7 +879,7 @@ def Zn2WriteFPU03 : SchedWriteRes<[Zn2AGU, Zn2FPU03]>
{
let Latency = 12;
let NumMicroOps = 2;
let ReleaseAtCycles = [1,3];
let ResourceCycles = [1,3];
}
// FICOM(P).
@ -920,12 +920,12 @@ def : InstRW<[Zn2WriteFPU01Y], (instrs VPBLENDDYrri)>;
def Zn2WriteFPU01Op2 : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
let NumMicroOps = 2;
let Latency = 8;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def Zn2WriteFPU01Op2Y : SchedWriteRes<[Zn2AGU, Zn2FPU01]> {
let NumMicroOps = 2;
let Latency = 9;
let ReleaseAtCycles = [1, 3];
let ResourceCycles = [1, 3];
}
def : InstRW<[Zn2WriteFPU01Op2], (instrs VPBLENDDrmi)>;
def : InstRW<[Zn2WriteFPU01Op2Y], (instrs VPBLENDDYrmi)>;
@ -948,7 +948,7 @@ def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
def Zn2WriteVPBROADCAST128Ld : SchedWriteRes<[Zn2AGU, Zn2FPU12]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[Zn2WriteVPBROADCAST128Ld],
(instregex "VPBROADCAST(B|W)rm")>;
@ -957,7 +957,7 @@ def : InstRW<[Zn2WriteVPBROADCAST128Ld],
def Zn2WriteVPBROADCAST256Ld : SchedWriteRes<[Zn2AGU, Zn2FPU1]> {
let Latency = 8;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[Zn2WriteVPBROADCAST256Ld],
(instregex "VPBROADCAST(B|W)Yrm")>;
@ -1012,14 +1012,14 @@ def : InstRW<[Zn2WriteBROADCAST], (instrs VBROADCASTF128,
def Zn2WriteEXTRACTPSr : SchedWriteRes<[Zn2FPU12, Zn2FPU2]> {
let Latency = 2;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : InstRW<[Zn2WriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>;
def Zn2WriteEXTRACTPSm : SchedWriteRes<[Zn2AGU,Zn2FPU12, Zn2FPU2]> {
let Latency = 5;
let NumMicroOps = 2;
let ReleaseAtCycles = [5, 1, 2];
let ResourceCycles = [5, 1, 2];
}
// m32,x,i.
def : InstRW<[Zn2WriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>;
@ -1035,7 +1035,7 @@ def : InstRW<[Zn2WriteFPU013m], (instrs VEXTRACTF128mr,
def Zn2WriteVINSERT128r: SchedWriteRes<[Zn2FPU013]> {
let Latency = 2;
// let ReleaseAtCycles = [2];
// let ResourceCycles = [2];
}
def Zn2WriteVINSERT128Ld: SchedWriteRes<[Zn2AGU,Zn2FPU013]> {
let Latency = 9;
@ -1124,7 +1124,7 @@ def : SchedAlias<WriteCvtSS2SD, Zn2WriteCVTSS2SDr>;
def Zn2WriteCVTSS2SDLd : SchedWriteRes<[Zn2AGU, Zn2FPU3]> {
let Latency = 10;
let NumMicroOps = 2;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
}
def : SchedAlias<WriteCvtSS2SDLd, Zn2WriteCVTSS2SDLd>;

138
llvm/lib/Target/X86/X86ScheduleZnver3.td
View File

@ -402,7 +402,7 @@ multiclass __zn3WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
int Lat = 1, list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
@ -501,7 +501,7 @@ defm : Zn3WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver3Model.LoadLa
def Zn3WriteMOVSlow : SchedWriteRes<[Zn3AGU012, Zn3Load]> {
let Latency = !add(Znver3Model.LoadLatency, 1);
let ReleaseAtCycles = [3, 1];
let ResourceCycles = [3, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
@ -515,14 +515,14 @@ def : InstRW<[WriteMove], (instrs COPY)>;
def Zn3WriteMOVBE16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = Znver3Model.LoadLatency;
let ReleaseAtCycles = [1, 1, 4];
let ResourceCycles = [1, 1, 4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMOVBE16rm], (instrs MOVBE16rm)>;
def Zn3WriteMOVBEmr : SchedWriteRes<[Zn3ALU0123, Zn3AGU012, Zn3Store]> {
let Latency = Znver3Model.StoreLatency;
let ReleaseAtCycles = [4, 1, 1];
let ResourceCycles = [4, 1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
@ -532,7 +532,7 @@ defm : Zn3WriteResIntPair<WriteALU, [Zn3ALU0123], 1, [1], 1>; // Simple integer
def Zn3WriteALUSlow : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
@ -543,21 +543,21 @@ def : InstRW<[Zn3WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
def Zn3WriteMoveExtend : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
def Zn3WriteMaterialize32bitImm: SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
def Zn3WritePDEP_PEXT : SchedWriteRes<[Zn3ALU1]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
@ -567,7 +567,7 @@ defm : Zn3WriteResIntPair<WriteADC, [Zn3ALU0123], 1, [4], 1>; // Integer ALU + f
def Zn3WriteADC8mr_SBB8mr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123, Zn3Store]> {
let Latency = 1;
let ReleaseAtCycles = [1, 1, 7, 1];
let ResourceCycles = [1, 1, 7, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
@ -578,7 +578,7 @@ defm : Zn3WriteResInt<WriteLEA, [Zn3AGU012], 1, [1], 1>; // LEA instructions
// This write is used for slow LEA instructions.
def Zn3Write3OpsLEA : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -605,7 +605,7 @@ def : InstRW<[Zn3WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def Zn3SlowLEA16r : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 2; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 2;
}
@ -634,7 +634,7 @@ defm : Zn3WriteResIntPair<WriteCMPXCHG, [Zn3ALU0123], 3, [12], 5>; // Compare an
def Zn3WriteCMPXCHG8rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 3;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 3;
}
def : InstRW<[Zn3WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
@ -643,42 +643,42 @@ defm : Zn3WriteResInt<WriteCMPXCHGRMW, [Zn3ALU0123], 3, [12], 6>; // Compare
def Zn3WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteCMPXCHG8rr.Latency);
let ReleaseAtCycles = [1, 1, 12];
let ResourceCycles = [1, 1, 12];
let NumMicroOps = !add(Zn3WriteCMPXCHG8rr.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
def Zn3WriteCMPXCHG8B : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 3; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [24];
let ResourceCycles = [24];
let NumMicroOps = 19;
}
def : InstRW<[Zn3WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
def Zn3WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 4; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [59];
let ResourceCycles = [59];
let NumMicroOps = 28;
}
def : InstRW<[Zn3WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
def Zn3WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
def Zn3WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = 5;
}
def : InstRW<[Zn3WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
def Zn3WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
@ -702,7 +702,7 @@ defm : Zn3WriteResIntPair<WritePOPCNT, [Zn3ALU0123], 1, [1], 1>; // Bit populati
def Zn3WritePOPCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WritePOPCNT16rr], (instrs POPCNT16rr)>;
@ -711,7 +711,7 @@ defm : Zn3WriteResIntPair<WriteLZCNT, [Zn3ALU0123], 1, [1], 1>; // Leading zero
def Zn3WriteLZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteLZCNT16rr], (instrs LZCNT16rr)>;
@ -720,7 +720,7 @@ defm : Zn3WriteResIntPair<WriteTZCNT, [Zn3ALU12], 2, [1], 2>; // Trailing zero c
def Zn3WriteTZCNT16rr : SchedWriteRes<[Zn3ALU0123]> {
let Latency = 2;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteTZCNT16rr], (instrs TZCNT16rr)>;
@ -746,7 +746,7 @@ defm : Zn3WriteResIntPair<WriteRotate, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn3WriteRotateR1 : SchedWriteRes<[Zn3ALU12]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
@ -754,7 +754,7 @@ def : InstRW<[Zn3WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def Zn3WriteRotateM1 : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateR1.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteRotateR1.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
@ -762,28 +762,28 @@ def : InstRW<[Zn3WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
def Zn3WriteRotateRightRI : SchedWriteRes<[Zn3ALU12]> {
let Latency = 3;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn3WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def Zn3WriteRotateRightMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRI.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateRightRI.NumMicroOps, 3);
}
def : InstRW<[Zn3WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
def Zn3WriteRotateLeftRI : SchedWriteRes<[Zn3ALU12]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn3WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def Zn3WriteRotateLeftMI : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRI.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateLeftRI.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
@ -792,28 +792,28 @@ defm : Zn3WriteResIntPair<WriteRotateCL, [Zn3ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn3WriteRotateRightRCL : SchedWriteRes<[Zn3ALU12]> {
let Latency = 3;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn3WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
def Zn3WriteRotateRightMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateRightRCL.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateRightRCL.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
def Zn3WriteRotateLeftRCL : SchedWriteRes<[Zn3ALU12]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn3WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
def Zn3WriteRotateLeftMCL : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3ALU12]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteRotateLeftRCL.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteRotateLeftRCL.NumMicroOps, 2);
}
def : InstRW<[Zn3WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
@ -850,7 +850,7 @@ defm : Zn3WriteResXMM<WriteFStore, [Zn3FPSt, Zn3Store], Znver3Model.StoreLatency
def Zn3WriteWriteFStoreMMX : SchedWriteRes<[Zn3FPSt, Zn3Store]> {
let Latency = 2; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteWriteFStoreMMX], (instrs MOVHPDmr, MOVHPSmr,
@ -871,7 +871,7 @@ defm : Zn3WriteResXMMPair<WriteFAdd, [Zn3FPFAdd01], 3, [1], 1>; // Floating poi
def Zn3WriteX87Arith : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 24];
let ResourceCycles = [1, 1, 24];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
@ -881,7 +881,7 @@ def : InstRW<[Zn3WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
def Zn3WriteX87Div : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 62];
let ResourceCycles = [1, 1, 62];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
@ -989,21 +989,21 @@ defm : Zn3WriteResXMM<WriteVecStoreX, [Zn3FPSt, Zn3Store], Znver3Model.StoreLate
def Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn3FPFMisc0]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
def Zn3WriteVEXTRACTI128mr : SchedWriteRes<[Zn3FPFMisc0, Zn3FPSt, Zn3Store]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
def Zn3WriteVINSERTF128rmr : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPFMisc0]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn3WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
}
def : InstRW<[Zn3WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
@ -1021,14 +1021,14 @@ defm : Zn3WriteResXMM<WriteVecMoveFromGpr, [Zn3FPLd01], 1, [2], 1>;
def Zn3WriteMOVMMX : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
let Latency = 1;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
def Zn3WriteMOVMMXSlow : SchedWriteRes<[Zn3FPLd01, Zn3FPFMisc0123]> {
let Latency = 1;
let ReleaseAtCycles = [1, 4];
let ResourceCycles = [1, 4];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
@ -1037,14 +1037,14 @@ defm : Zn3WriteResXMMPair<WriteVecALU, [Zn3FPVAdd0123], 1, [1], 1>; // Vector i
def Zn3WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
let Latency = 3;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
def Zn3WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn3FPVShuf01, Zn3FPLd01]> {
let Latency = 3;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
@ -1053,7 +1053,7 @@ defm : Zn3WriteResXMMPair<WriteVecALUX, [Zn3FPVAdd0123], 1, [1], 1>; // Vector i
def Zn3WriteVecALUXSlow : SchedWriteRes<[Zn3FPVAdd01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
@ -1069,7 +1069,7 @@ def : InstRW<[Zn3WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
def Zn3WriteVecALUXMMX : SchedWriteRes<[Zn3FPVAdd01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVecALUXMMX], (instrs MMX_PABSBrr, MMX_PABSDrr, MMX_PABSWrr,
@ -1082,7 +1082,7 @@ defm : Zn3WriteResYMMPair<WriteVecALUY, [Zn3FPVAdd0123], 1, [1], 1>; // Vector i
def Zn3WriteVecALUYSlow : SchedWriteRes<[Zn3FPVAdd01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
@ -1157,7 +1157,7 @@ defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; // Double -> Integer (ZMM).
def Zn3WriteCvtPD2IMMX : SchedWriteRes<[Zn3FPFCvt01]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteCvtPD2IMMX], (instrs MMX_CVTPD2PIrm, MMX_CVTTPD2PIrm, MMX_CVTPD2PIrr, MMX_CVTTPD2PIrr)>;
@ -1175,7 +1175,7 @@ defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; // Integer -> Double (ZMM).
def Zn3WriteCvtI2PDMMX : SchedWriteRes<[Zn3FPFCvt01]> {
let Latency = 2;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteCvtI2PDMMX], (instrs MMX_CVTPI2PDrm, MMX_CVTPI2PDrr)>;
@ -1187,7 +1187,7 @@ defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; // Integer -> Float (ZMM).
def Zn3WriteCvtI2PSMMX : SchedWriteRes<[Zn3FPFCvt01]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteCvtI2PSMMX], (instrs MMX_CVTPI2PSrr)>;
@ -1218,70 +1218,70 @@ defm : Zn3WriteResIntPair<WriteCRC32, [Zn3ALU1], 3, [1], 1>;
def Zn3WriteSHA1MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
def Zn3WriteSHA1MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG1rr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteSHA1MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn3WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
def Zn3WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
def Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
}
def : InstRW<[Zn3Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
def Zn3WriteSHA256MSG1rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 2;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
def Zn3Writerm_SHA256MSG1rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG1rr.Latency);
let ReleaseAtCycles = [1, 1, 3];
let ResourceCycles = [1, 1, 3];
let NumMicroOps = !add(Zn3WriteSHA256MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn3Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
def Zn3WriteSHA256MSG2rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 3;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def : InstRW<[Zn3WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
def Zn3WriteSHA256MSG2rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPU0123]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteSHA256MSG2rr.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn3WriteSHA256MSG2rr.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
def Zn3WriteSHA1RNDS4rri : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 6;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
def Zn3WriteSHA256RNDS2rr : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
@ -1316,14 +1316,14 @@ defm : Zn3WriteResInt<WriteSystem, [Zn3ALU0123], 100, [100], 100>;
def Zn3WriteVZEROUPPER : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 0; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVZEROUPPER], (instrs VZEROUPPER)>;
def Zn3WriteVZEROALL : SchedWriteRes<[Zn3FPU0123]> {
let Latency = 10; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [24];
let ResourceCycles = [24];
let NumMicroOps = 18;
}
def : InstRW<[Zn3WriteVZEROALL], (instrs VZEROALL)>;
@ -1335,42 +1335,42 @@ defm : Zn3WriteResYMMPair<WriteShuffle256, [Zn3FPVShuf], 2, [1], 1>; // 256-bit
def Zn3WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn3FPVShuf]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
def Zn3WriteVPERM2F128rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERM2I128rr_VPERM2F128rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn3WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
}
def : InstRW<[Zn3WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
def Zn3WriteVPERMPSYrm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, 7);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = 3;
}
def : InstRW<[Zn3WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
def Zn3WriteVPERMYri : SchedWriteRes<[Zn3FPVShuf]> {
let Latency = 6;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
def Zn3WriteVPERMPDYmi : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMYri.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn3WriteVPERMYri.NumMicroOps, 1);
}
def : InstRW<[Zn3WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
def Zn3WriteVPERMDYm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
let Latency = !add(Znver3Model.LoadLatency, 5);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteVPERMDYm], (instrs VPERMQYmi, VPERMDYrm)>;
@ -1389,14 +1389,14 @@ defm : Zn3WriteResInt<WriteFence, [Zn3ALU0123], 1, [100], 1>;
def Zn3WriteLFENCE : SchedWriteRes<[Zn3LSU]> {
let Latency = 1;
let ReleaseAtCycles = [30];
let ResourceCycles = [30];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteLFENCE], (instrs LFENCE)>;
def Zn3WriteSFENCE : SchedWriteRes<[Zn3LSU]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteSFENCE], (instrs SFENCE)>;
@ -1411,7 +1411,7 @@ defm : Zn3WriteResInt<WriteNop, [Zn3ALU0123], 0, [1], 1>; // FIXME: latency not
def Zn3WriteZeroLatency : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let ResourceCycles = [];
let NumMicroOps = 1;
}
def : InstRW<[Zn3WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
@ -1420,7 +1420,7 @@ def : InstRW<[Zn3WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
def Zn3WriteSwapRenameable : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let ResourceCycles = [];
let NumMicroOps = 2;
}
def : InstRW<[Zn3WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,

196
llvm/lib/Target/X86/X86ScheduleZnver4.td
View File

@ -402,7 +402,7 @@ multiclass __Zn4WriteRes<SchedWrite SchedRW, list<ProcResourceKind> ExePorts,
int Lat = 1, list<int> Res = [], int UOps = 1> {
def : WriteRes<SchedRW, ExePorts> {
let Latency = Lat;
let ReleaseAtCycles = Res;
let ResourceCycles = Res;
let NumMicroOps = UOps;
}
}
@ -515,7 +515,7 @@ defm : Zn4WriteResInt<WriteVecMaskedGatherWriteback, [], !add(Znver4Model.LoadLa
def Zn4WriteMOVSlow : SchedWriteRes<[Zn4AGU012, Zn4Load]> {
let Latency = !add(Znver4Model.LoadLatency, 1);
let ReleaseAtCycles = [3, 1];
let ResourceCycles = [3, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMOVSlow], (instrs MOV8rm, MOV8rm_NOREX, MOV16rm, MOVSX16rm16, MOVSX16rm32, MOVZX16rm16, MOVSX16rm8, MOVZX16rm8)>;
@ -529,14 +529,14 @@ def : InstRW<[WriteMove], (instrs COPY)>;
def Zn4WriteMOVBE16rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = Znver4Model.LoadLatency;
let ReleaseAtCycles = [1, 1, 4];
let ResourceCycles = [1, 1, 4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMOVBE16rm], (instrs MOVBE16rm)>;
def Zn4WriteMOVBEmr : SchedWriteRes<[Zn4ALU0123, Zn4AGU012, Zn4Store]> {
let Latency = Znver4Model.StoreLatency;
let ReleaseAtCycles = [4, 1, 1];
let ResourceCycles = [4, 1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteMOVBEmr], (instrs MOVBE16mr, MOVBE32mr, MOVBE64mr)>;
@ -546,7 +546,7 @@ defm : Zn4WriteResIntPair<WriteALU, [Zn4ALU0123], 1, [1], 1>; // Simple integer
def Zn4WriteALUSlow : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
@ -557,21 +557,21 @@ def : InstRW<[Zn4WriteALUSlow], (instrs ADD8i8, ADD16i16, ADD32i32, ADD64i32,
def Zn4WriteMoveExtend : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMoveExtend], (instrs MOVSX16rr16, MOVSX16rr32, MOVZX16rr16, MOVSX16rr8, MOVZX16rr8)>;
def Zn4WriteMaterialize32bitImm: SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteMaterialize32bitImm], (instrs MOV32ri, MOV32ri_alt, MOV64ri32)>;
def Zn4WritePDEP_PEXT : SchedWriteRes<[Zn4ALU1]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WritePDEP_PEXT], (instrs PDEP32rr, PDEP64rr,
@ -581,7 +581,7 @@ defm : Zn4WriteResIntPair<WriteADC, [Zn4ALU0123], 1, [4], 1>; // Integer ALU + f
def Zn4WriteADC8mr_SBB8mr : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123, Zn4Store]> {
let Latency = 1;
let ReleaseAtCycles = [1, 1, 7, 1];
let ResourceCycles = [1, 1, 7, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteADC8mr_SBB8mr], (instrs ADC8mr, SBB8mr)>;
@ -592,7 +592,7 @@ defm : Zn4WriteResInt<WriteLEA, [Zn4AGU012], 1, [1], 1>; // LEA instructions
// This write is used for slow LEA instructions.
def Zn4Write3OpsLEA : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 2;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -619,7 +619,7 @@ def : InstRW<[Zn4WriteLEA], (instrs LEA32r, LEA64r, LEA64_32r)>;
def Zn4SlowLEA16r : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 2; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 2;
}
@ -648,7 +648,7 @@ defm : Zn4WriteResIntPair<WriteCMPXCHG, [Zn4ALU0123], 3, [12], 5>; // Compare an
def Zn4WriteCMPXCHG8rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 3;
let ReleaseAtCycles = [12];
let ResourceCycles = [12];
let NumMicroOps = 3;
}
def : InstRW<[Zn4WriteCMPXCHG8rr], (instrs CMPXCHG8rr)>;
@ -657,42 +657,42 @@ defm : Zn4WriteResInt<WriteCMPXCHGRMW, [Zn4ALU0123], 3, [12], 6>; // Compare
def Zn4WriteCMPXCHG8rm_LCMPXCHG8 : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteCMPXCHG8rr.Latency);
let ReleaseAtCycles = [1, 1, 12];
let ResourceCycles = [1, 1, 12];
let NumMicroOps = !add(Zn4WriteCMPXCHG8rr.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteCMPXCHG8rm_LCMPXCHG8], (instrs CMPXCHG8rm, LCMPXCHG8)>;
def Zn4WriteCMPXCHG8B : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 3; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [24];
let ResourceCycles = [24];
let NumMicroOps = 19;
}
def : InstRW<[Zn4WriteCMPXCHG8B], (instrs CMPXCHG8B)>;
def Zn4WriteCMPXCHG16B_LCMPXCHG16B : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 4; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [59];
let ResourceCycles = [59];
let NumMicroOps = 28;
}
def : InstRW<[Zn4WriteCMPXCHG16B_LCMPXCHG16B], (instrs CMPXCHG16B, LCMPXCHG16B)>;
def Zn4WriteWriteXCHGUnrenameable : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteWriteXCHGUnrenameable], (instrs XCHG8rr, XCHG16rr, XCHG16ar)>;
def Zn4WriteXCHG8rm_XCHG16rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 3); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = 5;
}
def : InstRW<[Zn4WriteXCHG8rm_XCHG16rm], (instrs XCHG8rm, XCHG16rm)>;
def Zn4WriteXCHG32rm_XCHG64rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 2); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteXCHG32rm_XCHG64rm], (instrs XCHG32rm, XCHG64rm)>;
@ -716,7 +716,7 @@ defm : Zn4WriteResIntPair<WritePOPCNT, [Zn4ALU0123], 1, [1], 1>; // Bit populati
def Zn4WritePOPCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WritePOPCNT16rr], (instrs POPCNT16rr)>;
@ -725,7 +725,7 @@ defm : Zn4WriteResIntPair<WriteLZCNT, [Zn4ALU0123], 1, [1], 1>; // Leading zero
def Zn4WriteLZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 1;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteLZCNT16rr], (instrs LZCNT16rr)>;
@ -734,7 +734,7 @@ defm : Zn4WriteResIntPair<WriteTZCNT, [Zn4ALU12], 2, [1], 2>; // Trailing zero c
def Zn4WriteTZCNT16rr : SchedWriteRes<[Zn4ALU0123]> {
let Latency = 2;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteTZCNT16rr], (instrs TZCNT16rr)>;
@ -760,7 +760,7 @@ defm : Zn4WriteResIntPair<WriteRotate, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn4WriteRotateR1 : SchedWriteRes<[Zn4ALU12]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
@ -768,7 +768,7 @@ def : InstRW<[Zn4WriteRotateR1], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
def Zn4WriteRotateM1 : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateR1.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteRotateR1.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
@ -776,28 +776,28 @@ def : InstRW<[Zn4WriteRotateM1], (instrs RCL8m1, RCL16m1, RCL32m1, RCL64m1,
def Zn4WriteRotateRightRI : SchedWriteRes<[Zn4ALU12]> {
let Latency = 3;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn4WriteRotateRightRI], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
def Zn4WriteRotateRightMI : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateRightRI.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateRightRI.NumMicroOps, 3);
}
def : InstRW<[Zn4WriteRotateRightMI], (instrs RCR8mi, RCR16mi, RCR32mi, RCR64mi)>;
def Zn4WriteRotateLeftRI : SchedWriteRes<[Zn4ALU12]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn4WriteRotateLeftRI], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
def Zn4WriteRotateLeftMI : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateLeftRI.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateLeftRI.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteRotateLeftMI], (instrs RCL8mi, RCL16mi, RCL32mi, RCL64mi)>;
@ -806,28 +806,28 @@ defm : Zn4WriteResIntPair<WriteRotateCL, [Zn4ALU12], 1, [1], 1, /*LoadUOps=*/1>;
def Zn4WriteRotateRightRCL : SchedWriteRes<[Zn4ALU12]> {
let Latency = 3;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 7;
}
def : InstRW<[Zn4WriteRotateRightRCL], (instrs RCR8rCL, RCR16rCL, RCR32rCL, RCR64rCL)>;
def Zn4WriteRotateRightMCL : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateRightRCL.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateRightRCL.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteRotateRightMCL], (instrs RCR8mCL, RCR16mCL, RCR32mCL, RCR64mCL)>;
def Zn4WriteRotateLeftRCL : SchedWriteRes<[Zn4ALU12]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 9;
}
def : InstRW<[Zn4WriteRotateLeftRCL], (instrs RCL8rCL, RCL16rCL, RCL32rCL, RCL64rCL)>;
def Zn4WriteRotateLeftMCL : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4ALU12]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteRotateLeftRCL.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteRotateLeftRCL.NumMicroOps, 2);
}
def : InstRW<[Zn4WriteRotateLeftMCL], (instrs RCL8mCL, RCL16mCL, RCL32mCL, RCL64mCL)>;
@ -864,7 +864,7 @@ defm : Zn4WriteResXMM<WriteFStore, [Zn4FPSt, Zn4Store], Znver4Model.StoreLatency
def Zn4WriteWriteFStoreMMX : SchedWriteRes<[Zn4FPSt, Zn4Store]> {
let Latency = 2; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteWriteFStoreMMX], (instrs MOVHPDmr, MOVHPSmr,
@ -885,7 +885,7 @@ defm : Zn4WriteResXMMPair<WriteFAdd, [Zn4FPFAdd01], 3, [1], 1>; // Floating poi
def Zn4WriteX87Arith : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 24];
let ResourceCycles = [1, 1, 24];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
@ -895,7 +895,7 @@ def : InstRW<[Zn4WriteX87Arith], (instrs ADD_FI16m, ADD_FI32m,
def Zn4WriteX87Div : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, 1); // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1, 1, 62];
let ResourceCycles = [1, 1, 62];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteX87Div], (instrs DIV_FI16m, DIV_FI32m,
@ -1004,21 +1004,21 @@ defm : Zn4WriteResXMM<WriteVecStoreX, [Zn4FPSt, Zn4Store], Znver4Model.StoreLate
def Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr : SchedWriteRes<[Zn4FPFMisc0]> {
let Latency = 4;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr], (instrs VEXTRACTF128rr, VEXTRACTI128rr)>;
def Zn4WriteVEXTRACTI128mr : SchedWriteRes<[Zn4FPFMisc0, Zn4FPSt, Zn4Store]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteVEXTRACTI128mr], (instrs VEXTRACTI128mr, VEXTRACTF128mr)>;
def Zn4WriteVINSERTF128rmr : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPFMisc0]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn4WriteVEXTRACTF128rr_VEXTRACTI128rr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteVINSERTF128rmr], (instrs VINSERTF128rm)>;
@ -1036,14 +1036,14 @@ defm : Zn4WriteResXMM<WriteVecMoveFromGpr, [Zn4FPLd01], 1, [2], 1>;
def Zn4WriteMOVMMX : SchedWriteRes<[Zn4FPLd01, Zn4FPFMisc0123]> {
let Latency = 1;
let ReleaseAtCycles = [1, 2];
let ResourceCycles = [1, 2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteMOVMMX], (instrs MMX_MOVQ2FR64rr, MMX_MOVQ2DQrr)>;
def Zn4WriteMOVMMXSlow : SchedWriteRes<[Zn4FPLd01, Zn4FPFMisc0123]> {
let Latency = 1;
let ReleaseAtCycles = [1, 4];
let ResourceCycles = [1, 4];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteMOVMMXSlow], (instrs MMX_MOVD64rr, MMX_MOVD64to64rr)>;
@ -1052,14 +1052,14 @@ defm : Zn4WriteResXMMPair<WriteVecALU, [Zn4FPVAdd0123], 1, [1], 1>; // Vector i
def Zn4WriteEXTRQ_INSERTQ : SchedWriteRes<[Zn4FPVShuf01, Zn4FPLd01]> {
let Latency = 3;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteEXTRQ_INSERTQ], (instrs EXTRQ, INSERTQ)>;
def Zn4WriteEXTRQI_INSERTQI : SchedWriteRes<[Zn4FPVShuf01, Zn4FPLd01]> {
let Latency = 3;
let ReleaseAtCycles = [1, 1];
let ResourceCycles = [1, 1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteEXTRQI_INSERTQI], (instrs EXTRQI, INSERTQI)>;
@ -1068,7 +1068,7 @@ defm : Zn4WriteResXMMPair<WriteVecALUX, [Zn4FPVAdd0123], 1, [1], 1>; // Vector i
def Zn4WriteVecALUXSlow : SchedWriteRes<[Zn4FPVAdd01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
@ -1084,7 +1084,7 @@ def : InstRW<[Zn4WriteVecALUXSlow], (instrs PABSBrr, PABSDrr, PABSWrr,
def Zn4WriteVecOpMask : SchedWriteRes<[Zn4FPOpMask01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecOpMask], (instrs KADDBrr, KADDDrr, KADDQrr, KADDWrr,
@ -1102,14 +1102,14 @@ def : InstRW<[Zn4WriteVecOpMask], (instrs KADDBrr, KADDDrr, KADDQrr, KADDWrr,
def Zn4WriteVecOpMaskMemMov : SchedWriteRes<[Zn4FPOpMask4]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecOpMaskMemMov], (instrs KMOVBmk, KMOVDmk, KMOVQmk, KMOVWmk)>;
def Zn4WriteVecOpMaskKRMov : SchedWriteRes<[Zn4FPOpMask4]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecOpMaskKRMov], (instrs KMOVBkr, KMOVDkr, KMOVQkr, KMOVWkr)>;
@ -1117,7 +1117,7 @@ def : InstRW<[Zn4WriteVecOpMaskKRMov], (instrs KMOVBkr, KMOVDkr, KMOVQkr, KMOVWk
def Zn4WriteVecALU2Slow : SchedWriteRes<[Zn4FPVAdd12]> {
// TODO: All align instructions are expected to be of 4 cycle latency
let Latency = 4;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecALU2Slow], (instrs VALIGNDZrri, VALIGNDZ128rri, VALIGNDZ256rri,
@ -1127,7 +1127,7 @@ defm : Zn4WriteResYMMPair<WriteVecALUY, [Zn4FPVAdd0123], 1, [1], 1>; // Vector i
def Zn4WriteVecALUYSlow : SchedWriteRes<[Zn4FPVAdd01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVecALUYSlow], (instrs VPABSBYrr, VPABSDYrr, VPABSWYrr,
@ -1203,7 +1203,7 @@ defm : Zn4WriteResZMMPair<WriteCvtPD2IZ, [Zn4FPFCvt01], 3, [4], 2>; // Double ->
def Zn4WriteCvtPD2IMMX : SchedWriteRes<[Zn4FPFCvt01]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
defm : Zn4WriteResXMMPair<WriteCvtSS2I, [Zn4FPFCvt01], 5, [5], 2>; // Float -> Integer.
@ -1219,7 +1219,7 @@ defm : Zn4WriteResZMMPair<WriteCvtI2PDZ, [Zn4FPFCvt01], 4, [4], 4, /*LoadUOps=*/
def Zn4WriteCvtI2PDMMX : SchedWriteRes<[Zn4FPFCvt01]> {
let Latency = 2;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 2;
}
@ -1230,7 +1230,7 @@ defm : Zn4WriteResZMMPair<WriteCvtI2PSZ, [Zn4FPFCvt01], 3, [2], 2>; // Integer -
def Zn4WriteCvtI2PSMMX : SchedWriteRes<[Zn4FPFCvt01]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
@ -1261,70 +1261,70 @@ defm : Zn4WriteResIntPair<WriteCRC32, [Zn4ALU1], 3, [1], 1>;
def Zn4WriteSHA1MSG1rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSHA1MSG1rr], (instrs SHA1MSG1rr)>;
def Zn4WriteSHA1MSG1rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA1MSG1rr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteSHA1MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteSHA1MSG1rm], (instrs SHA1MSG1rm)>;
def Zn4WriteSHA1MSG2rr_SHA1NEXTErr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 1;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHA1MSG2rr_SHA1NEXTErr], (instrs SHA1MSG2rr, SHA1NEXTErr)>;
def Zn4Writerm_SHA1MSG2rm_SHA1NEXTErm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA1MSG2rr_SHA1NEXTErr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteSHA1MSG2rr_SHA1NEXTErr.NumMicroOps, 0);
}
def : InstRW<[Zn4Writerm_SHA1MSG2rm_SHA1NEXTErm], (instrs SHA1MSG2rm, SHA1NEXTErm)>;
def Zn4WriteSHA256MSG1rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 2;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSHA256MSG1rr], (instrs SHA256MSG1rr)>;
def Zn4Writerm_SHA256MSG1rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA256MSG1rr.Latency);
let ReleaseAtCycles = [1, 1, 3];
let ResourceCycles = [1, 1, 3];
let NumMicroOps = !add(Zn4WriteSHA256MSG1rr.NumMicroOps, 0);
}
def : InstRW<[Zn4Writerm_SHA256MSG1rm], (instrs SHA256MSG1rm)>;
def Zn4WriteSHA256MSG2rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 3;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 4;
}
def : InstRW<[Zn4WriteSHA256MSG2rr], (instrs SHA256MSG2rr)>;
def Zn4WriteSHA256MSG2rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPU0123]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteSHA256MSG2rr.Latency);
let ReleaseAtCycles = [1, 1, 8];
let ResourceCycles = [1, 1, 8];
let NumMicroOps = !add(Zn4WriteSHA256MSG2rr.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteSHA256MSG2rm], (instrs SHA256MSG2rm)>;
def Zn4WriteSHA1RNDS4rri : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 6;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHA1RNDS4rri], (instrs SHA1RNDS4rri)>;
def Zn4WriteSHA256RNDS2rr : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 4;
let ReleaseAtCycles = [8];
let ResourceCycles = [8];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHA256RNDS2rr], (instrs SHA256RNDS2rr)>;
@ -1359,14 +1359,14 @@ defm : Zn4WriteResInt<WriteSystem, [Zn4ALU0123], 100, [100], 100>;
def Zn4WriteVZEROUPPER : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 0; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVZEROUPPER], (instrs VZEROUPPER)>;
def Zn4WriteVZEROALL : SchedWriteRes<[Zn4FPU0123]> {
let Latency = 10; // FIXME: not from llvm-exegesis
let ReleaseAtCycles = [24];
let ResourceCycles = [24];
let NumMicroOps = 18;
}
def : InstRW<[Zn4WriteVZEROALL], (instrs VZEROALL)>;
@ -1378,56 +1378,56 @@ defm : Zn4WriteResYMMPair<WriteShuffle256, [Zn4FPVShuf], 1, [1], 1>; // 256-bit
def Zn4WriteVPERM2I128rr_VPERM2F128rr : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 3;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVPERM2I128rr_VPERM2F128rr], (instrs VPERM2I128rr, VPERM2F128rr)>;
def Zn4WriteVPERM2F128rm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERM2I128rr_VPERM2F128rr.Latency);
let ReleaseAtCycles = [1, 1, 1];
let ResourceCycles = [1, 1, 1];
let NumMicroOps = !add(Zn4WriteVPERM2I128rr_VPERM2F128rr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
def Zn4WriteVPERMPSYrr : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 7;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteVPERMPSYrr], (instrs VPERMPSYrr)>;
def Zn4WriteVPERMPSYrm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMPSYrr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteVPERMPSYrr.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
def Zn4WriteVPERMYri : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 6;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteVPERMYri], (instrs VPERMPDYri, VPERMQYri)>;
def Zn4WriteVPERMPDYmi : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMYri.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteVPERMYri.NumMicroOps, 1);
}
def : InstRW<[Zn4WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
def Zn4WriteVPERMDYrr : SchedWriteRes<[Zn4FPVShuf]> {
let Latency = 5;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteVPERMDYrr], (instrs VPERMDYrr)>;
def Zn4WriteVPERMYm : SchedWriteRes<[Zn4AGU012, Zn4Load, Zn4FPVShuf]> {
let Latency = !add(Znver4Model.LoadLatency, Zn4WriteVPERMDYrr.Latency);
let ReleaseAtCycles = [1, 1, 2];
let ResourceCycles = [1, 1, 2];
let NumMicroOps = !add(Zn4WriteVPERMDYrr.NumMicroOps, 0);
}
def : InstRW<[Zn4WriteVPERMYm], (instrs VPERMQYmi, VPERMDYrm)>;
@ -1446,14 +1446,14 @@ defm : Zn4WriteResInt<WriteFence, [Zn4ALU0123], 1, [100], 1>;
def Zn4WriteLFENCE : SchedWriteRes<[Zn4LSU]> {
let Latency = 1;
let ReleaseAtCycles = [30];
let ResourceCycles = [30];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteLFENCE], (instrs LFENCE)>;
def Zn4WriteSFENCE : SchedWriteRes<[Zn4LSU]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSFENCE], (instrs SFENCE)>;
@ -1468,7 +1468,7 @@ defm : Zn4WriteResInt<WriteNop, [Zn4ALU0123], 0, [1], 1>; // FIXME: latency not
def Zn4WriteZeroLatency : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let ResourceCycles = [];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
@ -1477,7 +1477,7 @@ def : InstRW<[Zn4WriteZeroLatency], (instrs MOV32rr, MOV32rr_REV,
def Zn4WriteSwapRenameable : SchedWriteRes<[]> {
let Latency = 0;
let ReleaseAtCycles = [];
let ResourceCycles = [];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSwapRenameable], (instrs XCHG32rr, XCHG32ar,
@ -1535,7 +1535,7 @@ def : IsOptimizableRegisterMove<[
// FIXUP and RANGE Instructions
def Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr : SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr], (instregex
@ -1547,7 +1547,7 @@ def : InstRW<[Zn4WriteVFIXUPIMMPDZrr_VRANGESDrr], (instregex
// SCALE & REDUCE instructions
def Zn4WriteSCALErr: SchedWriteRes<[Zn4FPFMisc23]> {
let Latency = 6;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteSCALErr], (instregex
@ -1558,7 +1558,7 @@ def : InstRW<[Zn4WriteSCALErr], (instregex
//BF16PS Instructions
def Zn4WriteBF16: SchedWriteRes<[Zn4FPFMisc23]> {
let Latency = 6;
let ReleaseAtCycles = [6];
let ResourceCycles = [6];
let NumMicroOps = 2;
}
def : InstRW<[Zn4WriteBF16], (instregex
@ -1568,7 +1568,7 @@ def : InstRW<[Zn4WriteBF16], (instregex
// BUSD and VPMADD Instructions
def Zn4WriteBUSDr_VPMADDr: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteBUSDr_VPMADDr], (instregex
@ -1579,7 +1579,7 @@ def : InstRW<[Zn4WriteBUSDr_VPMADDr], (instregex
// SHIFT instructions
def Zn4WriteSHIFTrr: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHIFTrr], (instregex
@ -1596,7 +1596,7 @@ def : InstRW<[Zn4WriteSHIFTrr], (instregex
def Zn4WriteSHIFTri: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 1;
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteSHIFTri], (instregex
@ -1606,7 +1606,7 @@ def : InstRW<[Zn4WriteSHIFTri], (instregex
// ALIGN Instructions
def Zn4WriteALIGN: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteALIGN], (instregex
@ -1616,7 +1616,7 @@ def : InstRW<[Zn4WriteALIGN], (instregex
//PACK Instructions
def Zn4WritePACK: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WritePACK], (instregex
@ -1626,7 +1626,7 @@ def : InstRW<[Zn4WritePACK], (instregex
// MAX and MIN Instructions
def Zn4WriteFCmp64: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4WriteFCmp64], (instregex
@ -1639,7 +1639,7 @@ def : InstRW<[Zn4WriteFCmp64], (instregex
// MOV Instructions
def Zn4MOVS: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4MOVS], (instregex
@ -1652,7 +1652,7 @@ def : InstRW<[Zn4MOVS], (instregex
def Zn4MOVSZ: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4MOVSZ], (instregex
@ -1661,7 +1661,7 @@ def : InstRW<[Zn4MOVSZ], (instregex
def Zn4MOVSrr: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 5;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
let NumMicroOps = 1;
}
def : InstRW<[Zn4MOVSrr], (instregex
@ -1672,7 +1672,7 @@ def : InstRW<[Zn4MOVSrr], (instregex
//VPTEST Instructions
def Zn4VPTESTZ128: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 3;
let ReleaseAtCycles = [3];
let ResourceCycles = [3];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VPTESTZ128], (instregex
@ -1681,7 +1681,7 @@ def : InstRW<[Zn4VPTESTZ128], (instregex
def Zn4VPTESTZ256: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 4;
let ReleaseAtCycles = [4];
let ResourceCycles = [4];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VPTESTZ256], (instregex
@ -1690,7 +1690,7 @@ def : InstRW<[Zn4VPTESTZ256], (instregex
def Zn4VPTESTZ: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 5;
let ReleaseAtCycles = [5];
let ResourceCycles = [5];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VPTESTZ], (instregex
@ -1700,7 +1700,7 @@ def : InstRW<[Zn4VPTESTZ], (instregex
// CONFLICT Instructions
def Zn4CONFLICTZ128: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4CONFLICTZ128], (instregex
@ -1709,7 +1709,7 @@ def : InstRW<[Zn4CONFLICTZ128], (instregex
def Zn4CONFLICTrr: SchedWriteRes<[Zn4FPFMisc01,Zn4FPFMisc12,Zn4FPFMisc23]> {
let Latency = 6;
let ReleaseAtCycles = [2,2,2];
let ResourceCycles = [2,2,2];
let NumMicroOps = 4;
}
def : InstRW<[Zn4CONFLICTrr], (instregex
@ -1719,7 +1719,7 @@ def : InstRW<[Zn4CONFLICTrr], (instregex
// RSQRT Instructions
def Zn4VRSQRT14PDZ256: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VRSQRT14PDZ256], (instregex
@ -1730,7 +1730,7 @@ def : InstRW<[Zn4VRSQRT14PDZ256], (instregex
// PERM Instructions
def Zn4PERMILP: SchedWriteRes<[Zn4FPFMisc123]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMILP], (instregex
@ -1739,7 +1739,7 @@ def : InstRW<[Zn4PERMILP], (instregex
def Zn4PERMIT2_128: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 3;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2_128], (instregex
@ -1749,7 +1749,7 @@ def : InstRW<[Zn4PERMIT2_128], (instregex
def Zn4PERMIT2_128rr:SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2_128rr], (instregex
@ -1759,7 +1759,7 @@ def : InstRW<[Zn4PERMIT2_128rr], (instregex
def Zn4PERMIT2_256: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 4;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2_256], (instregex
@ -1773,7 +1773,7 @@ def : InstRW<[Zn4PERMIT2_256], (instregex
def Zn4PERMIT2Z: SchedWriteRes<[Zn4FPFMisc12]> {
let Latency = 5;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4PERMIT2Z], (instregex
@ -1788,7 +1788,7 @@ def : InstRW<[Zn4PERMIT2Z], (instregex
// ALU SLOW Misc Instructions
def Zn4VecALUZSlow: SchedWriteRes<[Zn4FPFMisc01]> {
let Latency = 2;
let ReleaseAtCycles = [2];
let ResourceCycles = [2];
let NumMicroOps = 1;
}
def : InstRW<[Zn4VecALUZSlow], (instrs

28
llvm/test/TableGen/AcquireAtCycle.td → llvm/test/TableGen/StartAtCycle.td
View File

@ -10,7 +10,7 @@
// RUN: not llvm-tblgen -gen-subtarget -DNEGATIVE_INVALID -I %p/../../include %s 2>&1 | \
// RUN: FileCheck %s --check-prefix=NEGATIVE_INVALID
// Make sure that AcquireAtCycle in WriteRes is used to generate the
// Make sure that StartAtCycle in WriteRes is used to generate the
// correct data.
include "llvm/Target/Target.td"
@ -44,37 +44,37 @@ def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
// CORRECT-NEXT: { 1, 2, 0}, // #1
// CORRECT-NEXT: { 2, 4, 1}, // #2
// CORRECT-NEXT: { 3, 3, 2}, // #3
let ReleaseAtCycles = [2, 4, 3];
let AcquireAtCycles = [0, 1, 2];
let ResourceCycles = [2, 4, 3];
let StartAtCycles = [0, 1, 2];
}
def : WriteRes<WriteInst_B, [ResX2]> {
// If unspecified, AcquireAtCycle is set to 0.
// If unspecified, StartAtCycle is set to 0.
// CORRECT-NEXT: { 3, 1, 0} // #4
let ReleaseAtCycles = [1];
let ResourceCycles = [1];
}
#endif // CORRECT
#ifdef WRONG_SIZE
// WRONG_SIZE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(AcquireAtCycles) != size(ProcResources): 2 vs 3
// WRONG_SIZE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: size(StartAtCycles) != size(ProcResources): 2 vs 3
def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
let ReleaseAtCycles = [2, 4, 3];
let AcquireAtCycles = [0, 1];
let ResourceCycles = [2, 4, 3];
let StartAtCycles = [0, 1];
}
#endif
#ifdef WRONG_VALUE
// WRONG_VALUE: AcquireAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: AcquireAtCycles < ReleaseAtCycles must hold
// WRONG_VALUE: StartAtCycle.td:[[@LINE+1]]:1: error: Inconsistent resource cycles: StartAtCycles < Cycles must hold
def : WriteRes<WriteInst_A, [ResX0, ResX1, ResX2]> {
let ReleaseAtCycles = [2, 4, 3];
let AcquireAtCycles = [0, 1, 8];
let ResourceCycles = [2, 4, 3];
let StartAtCycles = [0, 1, 8];
}
#endif
#ifdef NEGATIVE_INVALID
// NEGATIVE_INVALID: AcquireAtCycle.td:[[@LINE+1]]:1: error: Invalid value: AcquireAtCycle must be a non-negative value.
// NEGATIVE_INVALID: StartAtCycle.td:[[@LINE+1]]:1: error: Invalid value: StartAtCycle must be a non-negative value.
def : WriteRes<WriteInst_A, [ResX0]> {
let ReleaseAtCycles = [2];
let AcquireAtCycles = [-1];
let ResourceCycles = [2];
let StartAtCycles = [-1];
}
#endif

2
llvm/tools/llvm-exegesis/lib/Analysis.cpp
View File

@ -390,7 +390,7 @@ void Analysis::printSchedClassDescHtml(const ResolvedSchedClass &RSC,
OS << "<li><span class=\"mono\">";
writeEscaped<kEscapeHtml>(OS,
SM.getProcResource(WPR.ProcResourceIdx)->Name);
OS << "</span>: " << WPR.ReleaseAtCycle << "</li>";
OS << "</span>: " << WPR.Cycles << "</li>";
}
OS << "</ul></td>";
// Idealized port pressure.

19
llvm/tools/llvm-exegesis/lib/SchedClassResolution.cpp
View File

@ -83,20 +83,19 @@ getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc,
const MCWriteProcResEntry *WPR = Entry.second;
const MCProcResourceDesc *const ProcResDesc =
SM.getProcResource(WPR->ProcResourceIdx);
// TODO: Handle AcquireAtAtCycle in llvm-exegesis and llvm-mca. See
// TODO: Handle StartAtCycle in llvm-exegesis and llvm-mca. See
// https://github.com/llvm/llvm-project/issues/62680 and
// https://github.com/llvm/llvm-project/issues/62681
assert(WPR->AcquireAtCycle == 0 &&
"`llvm-exegesis` does not handle AcquireAtCycle > 0");
assert(WPR->StartAtCycle == 0 &&
"`llvm-exegesis` does not handle StartAtCycle > 0");
if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
// This is a ProcResUnit.
Result.push_back(
{WPR->ProcResourceIdx, WPR->ReleaseAtCycle, WPR->AcquireAtCycle});
ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->ReleaseAtCycle;
Result.push_back({WPR->ProcResourceIdx, WPR->Cycles, WPR->StartAtCycle});
ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles;
} else {
// This is a ProcResGroup. First see if it contributes any cycles or if
// it has cycles just from subunits.
float RemainingCycles = WPR->ReleaseAtCycle;
float RemainingCycles = WPR->Cycles;
for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
++SubResIdx) {
@ -109,7 +108,7 @@ getNonRedundantWriteProcRes(const MCSchedClassDesc &SCDesc,
// The ProcResGroup contributes `RemainingCycles` cycles of its own.
Result.push_back({WPR->ProcResourceIdx,
static_cast<uint16_t>(std::round(RemainingCycles)),
WPR->AcquireAtCycle});
WPR->StartAtCycle});
// Spread the remaining cycles over all subunits.
for (const auto *SubResIdx = ProcResDesc->SubUnitsIdxBegin;
SubResIdx != ProcResDesc->SubUnitsIdxBegin + ProcResDesc->NumUnits;
@ -214,13 +213,13 @@ computeIdealizedProcResPressure(const MCSchedModel &SM,
SM.getProcResource(WPR.ProcResourceIdx);
if (ProcResDesc->SubUnitsIdxBegin == nullptr) {
// This is a ProcResUnit.
DensePressure[WPR.ProcResourceIdx] += WPR.ReleaseAtCycle;
DensePressure[WPR.ProcResourceIdx] += WPR.Cycles;
} else {
// This is a ProcResGroup.
SmallVector<uint16_t, 32> Subunits(ProcResDesc->SubUnitsIdxBegin,
ProcResDesc->SubUnitsIdxBegin +
ProcResDesc->NumUnits);
distributePressure(WPR.ReleaseAtCycle, Subunits, DensePressure);
distributePressure(WPR.Cycles, Subunits, DensePressure);
}
}
// Turn dense pressure into sparse pressure by removing zero entries.

6
llvm/tools/llvm-mca/Views/BottleneckAnalysis.cpp
View File

@ -611,9 +611,9 @@ void BottleneckAnalysis::printBottleneckHints(raw_ostream &OS) const {
ArrayRef<unsigned> Distribution = Tracker.getResourcePressureDistribution();
const MCSchedModel &SM = getSubTargetInfo().getSchedModel();
for (unsigned I = 0, E = Distribution.size(); I < E; ++I) {
unsigned ReleaseAtCycles = Distribution[I];
if (ReleaseAtCycles) {
double Frequency = (double)ReleaseAtCycles * 100 / TotalCycles;
unsigned ResourceCycles = Distribution[I];
if (ResourceCycles) {
double Frequency = (double)ResourceCycles * 100 / TotalCycles;
const MCProcResourceDesc &PRDesc = *SM.getProcResource(I);
OS << "\n - " << PRDesc.Name << " [ "
<< format("%.2f", floor((Frequency * 100) + 0.5) / 100) << "% ]";

4
llvm/tools/llvm-mca/Views/ResourcePressureView.cpp
View File

@ -54,7 +54,7 @@ void ResourcePressureView::onEvent(const HWInstructionEvent &Event) {
const auto &IssueEvent = static_cast<const HWInstructionIssuedEvent &>(Event);
ArrayRef<llvm::MCInst> Source = getSource();
const unsigned SourceIdx = Event.IR.getSourceIndex() % Source.size();
for (const std::pair<ResourceRef, ReleaseAtCycles> &Use :
for (const std::pair<ResourceRef, ResourceCycles> &Use :
IssueEvent.UsedResources) {
const ResourceRef &RR = Use.first;
assert(Resource2VecIndex.contains(RR.first));
@ -181,7 +181,7 @@ json::Value ResourcePressureView::toJSON() const {
ArrayRef<llvm::MCInst> Source = getSource();
const unsigned Executions = LastInstructionIdx / Source.size() + 1;
for (const auto &R : enumerate(ResourceUsage)) {
const ReleaseAtCycles &RU = R.value();
const ResourceCycles &RU = R.value();
if (RU.getNumerator() == 0)
continue;
unsigned InstructionIndex = R.index() / NumResourceUnits;

2
llvm/tools/llvm-mca/Views/ResourcePressureView.h
View File

@ -78,7 +78,7 @@ class ResourcePressureView : public InstructionView {
llvm::DenseMap<unsigned, unsigned> Resource2VecIndex;
// Table of resources used by instructions.
std::vector<ReleaseAtCycles> ResourceUsage;
std::vector<ResourceCycles> ResourceUsage;
unsigned NumResourceUnits;
void printResourcePressurePerIter(llvm::raw_ostream &OS) const;

92
llvm/utils/TableGen/SubtargetEmitter.cpp
View File

@ -119,8 +119,8 @@ class SubtargetEmitter {
const CodeGenProcModel &ProcModel);
Record *FindReadAdvance(const CodeGenSchedRW &SchedRead,
const CodeGenProcModel &ProcModel);
void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
std::vector<int64_t> &AcquireAtCycles,
void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
std::vector<int64_t> &StartAtCycles,
const CodeGenProcModel &ProcModel);
void GenSchedClassTables(const CodeGenProcModel &ProcModel,
SchedClassTables &SchedTables);
@ -976,10 +976,11 @@ Record *SubtargetEmitter::FindReadAdvance(const CodeGenSchedRW &SchedRead,
// Expand an explicit list of processor resources into a full list of implied
// resource groups and super resources that cover them.
void SubtargetEmitter::ExpandProcResources(
RecVec &PRVec, std::vector<int64_t> &ReleaseAtCycles,
std::vector<int64_t> &AcquireAtCycles, const CodeGenProcModel &PM) {
assert(PRVec.size() == ReleaseAtCycles.size() && "failed precondition");
void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
std::vector<int64_t> &Cycles,
std::vector<int64_t> &StartAtCycles,
const CodeGenProcModel &PM) {
assert(PRVec.size() == Cycles.size() && "failed precondition");
for (unsigned i = 0, e = PRVec.size(); i != e; ++i) {
Record *PRDef = PRVec[i];
RecVec SubResources;
@ -999,8 +1000,8 @@ void SubtargetEmitter::ExpandProcResources(
SchedModels.findProcResUnits(SubDef->getValueAsDef("Super"), PM,
SubDef->getLoc());
PRVec.push_back(SuperDef);
ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
AcquireAtCycles.push_back(AcquireAtCycles[i]);
Cycles.push_back(Cycles[i]);
StartAtCycles.push_back(StartAtCycles[i]);
SubDef = SuperDef;
}
}
@ -1016,8 +1017,8 @@ void SubtargetEmitter::ExpandProcResources(
}
if (SubI == SubE) {
PRVec.push_back(PR);
ReleaseAtCycles.push_back(ReleaseAtCycles[i]);
AcquireAtCycles.push_back(AcquireAtCycles[i]);
Cycles.push_back(Cycles[i]);
StartAtCycles.push_back(StartAtCycles[i]);
}
}
}
@ -1149,69 +1150,67 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
// Create an entry for each ProcResource listed in WriteRes.
RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
std::vector<int64_t> ReleaseAtCycles =
WriteRes->getValueAsListOfInts("ReleaseAtCycles");
std::vector<int64_t> Cycles =
WriteRes->getValueAsListOfInts("ResourceCycles");
std::vector<int64_t> AcquireAtCycles =
WriteRes->getValueAsListOfInts("AcquireAtCycles");
std::vector<int64_t> StartAtCycles =
WriteRes->getValueAsListOfInts("StartAtCycles");
// Check consistency of the two vectors carrying the start and
// stop cycles of the resources.
if (!ReleaseAtCycles.empty() &&
ReleaseAtCycles.size() != PRVec.size()) {
// If ReleaseAtCycles is provided, check consistency.
if (!Cycles.empty() && Cycles.size() != PRVec.size()) {
// If ResourceCycles is provided, check consistency.
PrintFatalError(
WriteRes->getLoc(),
Twine("Inconsistent release at cycles: size(ReleaseAtCycles) != "
Twine("Inconsistent resource cycles: size(ResourceCycles) != "
"size(ProcResources): ")
.concat(Twine(PRVec.size()))
.concat(" vs ")
.concat(Twine(ReleaseAtCycles.size())));
.concat(Twine(Cycles.size())));
}
if (!AcquireAtCycles.empty() && AcquireAtCycles.size() != PRVec.size()) {
if (!StartAtCycles.empty() && StartAtCycles.size() != PRVec.size()) {
PrintFatalError(
WriteRes->getLoc(),
Twine("Inconsistent resource cycles: size(AcquireAtCycles) != "
Twine("Inconsistent resource cycles: size(StartAtCycles) != "
"size(ProcResources): ")
.concat(Twine(AcquireAtCycles.size()))
.concat(Twine(StartAtCycles.size()))
.concat(" vs ")
.concat(Twine(PRVec.size())));
}
if (ReleaseAtCycles.empty()) {
// If ReleaseAtCycles is not provided, default to one cycle
if (Cycles.empty()) {
// If ResourceCycles is not provided, default to one cycle
// per resource.
ReleaseAtCycles.resize(PRVec.size(), 1);
Cycles.resize(PRVec.size(), 1);
}
if (AcquireAtCycles.empty()) {
// If AcquireAtCycles is not provided, reserve the resource
if (StartAtCycles.empty()) {
// If StartAtCycles is not provided, reserve the resource
// starting from cycle 0.
AcquireAtCycles.resize(PRVec.size(), 0);
StartAtCycles.resize(PRVec.size(), 0);
}
assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
assert(StartAtCycles.size() == Cycles.size());
ExpandProcResources(PRVec, ReleaseAtCycles, AcquireAtCycles, ProcModel);
assert(AcquireAtCycles.size() == ReleaseAtCycles.size());
ExpandProcResources(PRVec, Cycles, StartAtCycles, ProcModel);
assert(StartAtCycles.size() == Cycles.size());
for (unsigned PRIdx = 0, PREnd = PRVec.size();
PRIdx != PREnd; ++PRIdx) {
MCWriteProcResEntry WPREntry;
WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
WPREntry.ReleaseAtCycle = ReleaseAtCycles[PRIdx];
WPREntry.AcquireAtCycle = AcquireAtCycles[PRIdx];
if (AcquireAtCycles[PRIdx] > ReleaseAtCycles[PRIdx]) {
PrintFatalError(
WriteRes->getLoc(),
Twine("Inconsistent resource cycles: AcquireAtCycles "
"< ReleaseAtCycles must hold."));
}
if (AcquireAtCycles[PRIdx] < 0) {
WPREntry.Cycles = Cycles[PRIdx];
WPREntry.StartAtCycle = StartAtCycles[PRIdx];
if (StartAtCycles[PRIdx] > Cycles[PRIdx]) {
PrintFatalError(WriteRes->getLoc(),
Twine("Invalid value: AcquireAtCycle "
Twine("Inconsistent resource cycles: StartAtCycles "
"< Cycles must hold."));
}
if (StartAtCycles[PRIdx] < 0) {
PrintFatalError(WriteRes->getLoc(),
Twine("Invalid value: StartAtCycle "
"must be a non-negative value."));
}
// If this resource is already used in this sequence, add the current
@ -1229,10 +1228,9 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
// `SubtargetEmitter::EmitSchedClassTables`), or
// 2. thinking how to merge multiple intervals into a
// single interval.
assert(WPREntry.AcquireAtCycle == 0 &&
assert(WPREntry.StartAtCycle == 0 &&
"multiple use ofthe same resource is not yet handled");
WriteProcResources[WPRIdx].ReleaseAtCycle +=
WPREntry.ReleaseAtCycle;
WriteProcResources[WPRIdx].Cycles += WPREntry.Cycles;
break;
}
}
@ -1336,7 +1334,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
raw_ostream &OS) {
// Emit global WriteProcResTable.
OS << "\n// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}\n"
OS << "\n// {ProcResourceIdx, Cycles, StartAtCycle}\n"
<< "extern const llvm::MCWriteProcResEntry " << Target
<< "WriteProcResTable[] = {\n"
<< " { 0, 0, 0 }, // Invalid\n";
@ -1344,8 +1342,8 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
WPRIdx != WPREnd; ++WPRIdx) {
MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
<< format("%2d", WPREntry.ReleaseAtCycle) << ", "
<< format("%2d", WPREntry.AcquireAtCycle) << "}";
<< format("%2d", WPREntry.Cycles) << ", "
<< format("%2d", WPREntry.StartAtCycle) << "}";
if (WPRIdx + 1 < WPREnd)
OS << ',';
OS << " // #" << WPRIdx << '\n';