From 4e3699b4c6255070f2bf4c3ce98978a9bd2614fd Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Thu, 8 Jan 2026 09:28:29 -0800 Subject: [PATCH] [RISCV] Mark More Relocs as Relaxable (#151422) Since this code was last reviewed, more relaxations have been added to the psABI for existing standard relocations that LLVM didn't have marked as relaxable. This change ensures that LLVM marks the following relocations (and their respective fixups) as relaxable: - `R_RISCV_JAL` - `R_RISCV_GOT_HI20` - `R_RISCV_TPREL_HI20` - `R_RISCV_TLSDESC_HI20` This also updates the linker relaxation test to use `-NEXT` to check all the output lines. There are lots more emitted relocations, not only due to JAL being relaxable, but branches are now also marked linker relaxable because they can be turned into `b; jal` during assembly relaxation, which may also be marked relaxable. --- bolt/test/RISCV/reloc-label-diff.s | 2 +- .../RISCV/MCTargetDesc/RISCVAsmBackend.cpp | 3 +- .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 43 ++++--- .../CodeGen/RISCV/option-relax-relocation.ll | 28 +++-- llvm/test/MC/RISCV/Relocations/expr.s | 10 +- llvm/test/MC/RISCV/Relocations/relocations.s | 6 + llvm/test/MC/RISCV/align.s | 21 +++- llvm/test/MC/RISCV/compressed-relocations.s | 4 +- llvm/test/MC/RISCV/linker-relaxation.s | 112 +++++++++++------- llvm/test/MC/RISCV/long-conditional-jump.s | 42 ++++++- llvm/test/MC/RISCV/option-relax.s | 1 + llvm/test/MC/RISCV/tlsdesc.s | 6 + llvm/test/MC/RISCV/xqcibi-linker-relaxation.s | 8 +- llvm/test/MC/RISCV/xqcibi-relocations.s | 2 + 14 files changed, 208 insertions(+), 80 deletions(-) diff --git a/bolt/test/RISCV/reloc-label-diff.s b/bolt/test/RISCV/reloc-label-diff.s index f1144767714b..4f2eb00322c6 100644 --- a/bolt/test/RISCV/reloc-label-diff.s +++ b/bolt/test/RISCV/reloc-label-diff.s @@ -12,7 +12,7 @@ _start: // BOLT removes this nop so the label difference is initially 8 but should be // 4 after BOLT processes it. nop - beq x0, x0, _test_end + li x0, _test_end-. _test_end: ret .size _start, .-_start diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index f3ad8b6d4b8c..584c000519b2 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -823,9 +823,10 @@ static bool relaxableFixupNeedsRelocation(const MCFixupKind Kind) { default: break; case RISCV::fixup_riscv_rvc_jump: + case RISCV::fixup_riscv_branch: case RISCV::fixup_riscv_rvc_branch: + case RISCV::fixup_riscv_qc_e_branch: case RISCV::fixup_riscv_rvc_imm: - case RISCV::fixup_riscv_jal: return false; } return true; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp index fd460e457a41..5cf1f296d4f7 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp @@ -344,8 +344,11 @@ void RISCVMCCodeEmitter::expandLongCondBr(const MCInst &MI, // Drop any fixup added so we can add the correct one. Fixups.resize(FixupStartIndex); - if (SrcSymbol.isExpr()) + if (SrcSymbol.isExpr()) { addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal); + if (STI.hasFeature(RISCV::FeatureRelax)) + Fixups.back().setLinkerRelaxable(); + } } // Expand PseudoLongQC_(E_)Bxxx to an inverted conditional branch and an @@ -392,8 +395,11 @@ void RISCVMCCodeEmitter::expandQCLongCondBrImm(const MCInst &MI, support::endian::write(CB, JBinary, llvm::endianness::little); // Drop any fixup added so we can add the correct one. Fixups.resize(FixupStartIndex); - if (SrcSymbol.isExpr()) + if (SrcSymbol.isExpr()) { addFixup(Fixups, Offset, SrcSymbol.getExpr(), RISCV::fixup_riscv_jal); + if (STI.hasFeature(RISCV::FeatureRelax)) + Fixups.back().setLinkerRelaxable(); + } } void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, @@ -602,8 +608,8 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, // The actual emission of `R_RISCV_RELAX` will be handled in // `RISCVAsmBackend::applyFixup`. bool RelaxCandidate = false; - auto AsmRelaxToLinkerRelaxableWithFeature = [&](unsigned Feature) -> void { - if (!STI.hasFeature(RISCV::FeatureExactAssembly) && STI.hasFeature(Feature)) + auto AsmRelaxToLinkerRelaxable = [&]() -> void { + if (!STI.hasFeature(RISCV::FeatureExactAssembly)) RelaxCandidate = true; }; @@ -658,9 +664,6 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, llvm_unreachable("VK_TPREL_LO used with unexpected instruction format"); RelaxCandidate = true; break; - case ELF::R_RISCV_TPREL_HI20: - RelaxCandidate = true; - break; case ELF::R_RISCV_CALL_PLT: FixupKind = RISCV::fixup_riscv_call_plt; RelaxCandidate = true; @@ -669,32 +672,40 @@ uint64_t RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo, FixupKind = RISCV::fixup_riscv_qc_abs20_u; RelaxCandidate = true; break; + case ELF::R_RISCV_GOT_HI20: + case ELF::R_RISCV_TPREL_HI20: + case ELF::R_RISCV_TLSDESC_HI20: + RelaxCandidate = true; + break; } } else if (Kind == MCExpr::SymbolRef || Kind == MCExpr::Binary) { // FIXME: Sub kind binary exprs have chance of underflow. if (MIFrm == RISCVII::InstFormatJ) { FixupKind = RISCV::fixup_riscv_jal; - AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb); + RelaxCandidate = true; } else if (MIFrm == RISCVII::InstFormatB) { FixupKind = RISCV::fixup_riscv_branch; - // This might be assembler relaxed to `b; jal` but we cannot relax - // the `jal` again in the assembler. + // Relaxes to B; JAL, with fixup_riscv_jal + AsmRelaxToLinkerRelaxable(); } else if (MIFrm == RISCVII::InstFormatCJ) { FixupKind = RISCV::fixup_riscv_rvc_jump; - AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcilb); + // Relaxes to JAL with fixup_riscv_jal + AsmRelaxToLinkerRelaxable(); } else if (MIFrm == RISCVII::InstFormatCB) { FixupKind = RISCV::fixup_riscv_rvc_branch; - // This might be assembler relaxed to `b; jal` but we cannot relax - // the `jal` again in the assembler. + // Relaxes to B; JAL, with fixup_riscv_jal + AsmRelaxToLinkerRelaxable(); } else if (MIFrm == RISCVII::InstFormatCI) { FixupKind = RISCV::fixup_riscv_rvc_imm; - AsmRelaxToLinkerRelaxableWithFeature(RISCV::FeatureVendorXqcili); + // Relaxes to `QC.E.LI` with fixup_riscv_qc_e_32 + if (STI.hasFeature(RISCV::FeatureVendorXqcili)) + AsmRelaxToLinkerRelaxable(); } else if (MIFrm == RISCVII::InstFormatI) { FixupKind = RISCV::fixup_riscv_12_i; } else if (MIFrm == RISCVII::InstFormatQC_EB) { FixupKind = RISCV::fixup_riscv_qc_e_branch; - // This might be assembler relaxed to `qc.e.b; jal` but we cannot - // relax the `jal` again in the assembler. + // Relaxes to QC.E.BI; JAL, with fixup_riscv_jal + AsmRelaxToLinkerRelaxable(); } else if (MIFrm == RISCVII::InstFormatQC_EAI) { FixupKind = RISCV::fixup_riscv_qc_e_32; RelaxCandidate = true; diff --git a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll index fd3d9435e22a..62178e11f871 100644 --- a/llvm/test/CodeGen/RISCV/option-relax-relocation.ll +++ b/llvm/test/CodeGen/RISCV/option-relax-relocation.ll @@ -1,32 +1,44 @@ -;; With +relax, J below needs a relocation to ensure the target is correct -;; after linker relaxation. See https://github.com/ClangBuiltLinux/linux/issues/1965 - ; RUN: llc -mtriple=riscv64 -mattr=-relax -filetype=obj < %s \ ; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,NORELAX ; RUN: llc -mtriple=riscv64 -mattr=+relax -filetype=obj < %s \ ; RUN: | llvm-objdump -d -r - | FileCheck %s --check-prefixes=CHECK,RELAX +;; With +relax, All `j` instructions below need a relocation to ensure the target is correct +;; after linker relaxation. See https://github.com/ClangBuiltLinux/linux/issues/1965 + ; CHECK: j {{.*}} ; RELAX-NEXT: R_RISCV_JAL {{.*}} +; RELAX-NOT: R_RISCV_RELAX ; CHECK-NEXT: auipc ra, 0x0 ; CHECK-NEXT: R_RISCV_CALL_PLT f ; RELAX-NEXT: R_RISCV_RELAX *ABS* ; CHECK-NEXT: jalr ra ; CHECK-NEXT: j {{.*}} +; RELAX-NEXT: R_RISCV_JAL {{.*}} +; RELAX-NOT: R_RISCV_RELAX ; CHECK-NEXT: j {{.*}} -; RELAX-NEXT: R_RISCV_JAL .L0 +; RELAX-NEXT: R_RISCV_JAL {{.*}} +; RELAX-NEXT: R_RISCV_RELAX *ABS* ; NORELAX-NEXT: li a0, 0x0 ; RELAX-EMPTY: define dso_local noundef signext i32 @main() local_unnamed_addr #0 { entry: - callbr void asm sideeffect ".option push\0A.option norelax\0Aj $0\0A.option pop\0A", "!i"() - to label %asm.fallthrough [label %label] + callbr void asm sideeffect " + .option push + .option norelax + j $0 + .option pop", + "!i"() to label %asm.fallthrough [label %label] asm.fallthrough: ; preds = %entry tail call void @f() - callbr void asm sideeffect ".option push\0A.option norelax\0Aj $0\0A.option pop\0A", "!i"() - to label %asm.fallthrough [label %label] + callbr void asm sideeffect " + .option push + .option norelax + j $0 + .option pop", + "!i"() to label %asm.fallthrough [label %label] br label %label label: ; preds = %asm.fallthrough, %entry diff --git a/llvm/test/MC/RISCV/Relocations/expr.s b/llvm/test/MC/RISCV/Relocations/expr.s index 7d4dfd30e3fb..af55462f6d55 100644 --- a/llvm/test/MC/RISCV/Relocations/expr.s +++ b/llvm/test/MC/RISCV/Relocations/expr.s @@ -10,10 +10,13 @@ ## This is linker-relaxable to avoid resolving the following fixups call relax +# CHECK-RELOC: R_RISCV_CALL_PLT +# CHECK-RELOC-NEXT: R_RISCV_RELAX jal zero, .LBB0+16 # CHECK-INSTR: jal zero, 0x10 -# CHECK-RELOC: R_RISCV_JAL +# CHECK-RELOC-NEXT: R_RISCV_JAL +# CHECK-RELOC-NEXT: R_RISCV_RELAX beq a0, a1, .LBB1+32 # CHECK-INSTR: beq a0, a1, 0x20 @@ -24,11 +27,12 @@ c.j .+32 c.j .LBB2+4 # CHECK-INSTR: c.j 0x22 -# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP +# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP c.beqz a0, .-2 # CHECK-INSTR: c.beqz a0, 0x12 call relax -# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT +# CHECK-RELOC-NEXT: R_RISCV_CALL_PLT +# CHECK-RELOC-NEXT: R_RISCV_RELAX .LBB2: diff --git a/llvm/test/MC/RISCV/Relocations/relocations.s b/llvm/test/MC/RISCV/Relocations/relocations.s index e1d56885aaf3..42cdfe338fe5 100644 --- a/llvm/test/MC/RISCV/Relocations/relocations.s +++ b/llvm/test/MC/RISCV/Relocations/relocations.s @@ -2,19 +2,25 @@ # RUN: | FileCheck -check-prefix=INSTR %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax %s \ +# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC-RELAX %s # Check prefixes: # RELOC - Check the relocation in the object. +# RELOC-RELAX - Check the relocation in the object with relaxations # INSTR - Check the instruction is handled properly by the ASMPrinter .long foo # RELOC: R_RISCV_32 foo +# RELOC-RELAX: R_RISCV_32 foo .quad foo # RELOC: R_RISCV_64 foo +# RELOC-RELAX: R_RISCV_64 foo lui t1, %hi(foo) # RELOC: R_RISCV_HI20 foo 0x0 +# RELOC # INSTR: lui t1, %hi(foo) lui t1, %hi(foo+4) diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s index 4d4d998c992f..92862d903ce1 100644 --- a/llvm/test/MC/RISCV/align.s +++ b/llvm/test/MC/RISCV/align.s @@ -137,8 +137,14 @@ data2: add a0, a0, a1 ## Branches crossing the linker-relaxable R_RISCV_ALIGN need relocations. -# RELAX-RELOC-NOT: .rela.text3 { -# C-OR-ZCA-EXT-RELAX-RELOC-NOT: .rela.text3 { +# RELAX-RELOC: .rela.text3 { +# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6 +# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: } +# C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3 { .section .text3, "ax" bnez t1, 1f bnez t2, 2f @@ -153,9 +159,11 @@ data2: # RELAX-RELOC: .rela.text3a { # RELAX-RELOC-NEXT: 0x0 R_RISCV_CALL_PLT foo 0x0 # RELAX-RELOC-NEXT: 0x0 R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: 0x8 R_RISCV_BRANCH .Ltmp[[#]] 0x0 # RELAX-RELOC-NEXT: 0xC R_RISCV_BRANCH .Ltmp[[#]] 0x0 # RELAX-RELOC-NEXT: 0x10 R_RISCV_ALIGN - 0x6 # RELAX-RELOC-NEXT: 0x16 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x1A R_RISCV_BRANCH .Ltmp[[#]] 0x0 # RELAX-RELOC-NEXT: } # C-OR-ZCA-EXT-NORELAX-RELOC: .rela.text3a # C-OR-ZCA-EXT-RELAX-RELOC: .rela.text3a @@ -171,8 +179,13 @@ bnez t1, 2b ## .text3 with a call at the end # RELAX-RELOC: .rela.text3b { -# RELAX-RELOC-NEXT: 0x10 R_RISCV_CALL_PLT foo 0x0 -# RELAX-RELOC-NEXT: 0x10 R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: 0x0 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x4 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x8 R_RISCV_ALIGN - 0x6 +# RELAX-RELOC-NEXT: 0xE R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x12 R_RISCV_BRANCH .Ltmp[[#]] 0x0 +# RELAX-RELOC-NEXT: 0x16 R_RISCV_CALL_PLT foo 0x0 +# RELAX-RELOC-NEXT: 0x16 R_RISCV_RELAX - 0x0 # RELAX-RELOC-NEXT: } .section .text3b, "ax" bnez t1, 1f diff --git a/llvm/test/MC/RISCV/compressed-relocations.s b/llvm/test/MC/RISCV/compressed-relocations.s index 82cb1a12c389..ba57507d0b4e 100644 --- a/llvm/test/MC/RISCV/compressed-relocations.s +++ b/llvm/test/MC/RISCV/compressed-relocations.s @@ -3,7 +3,7 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \ -# RUN: | llvm-readobj -r - | FileCheck -check-prefix=RELOC %s +# RUN: | llvm-readobj -r - | FileCheck -check-prefixes=RELOC,RELAX %s # Check prefixes: # RELOC - Check the relocation in the object. @@ -11,10 +11,12 @@ c.jal foo # A compressed jump (c.j) to an unresolved symbol will be relaxed to a (jal). # RELOC: R_RISCV_JAL +# RELAX-NEXT: R_RISCV_RELAX # INSTR: c.jal foo c.bnez a0, foo # A compressed branch (c.bnez) to an unresolved symbol will be relaxed to a (bnez). # The (bnez) to an unresolved symbol will in turn be relaxed to (beqz; jal) # RELOC-NEXT: R_RISCV_JAL +# RELAX-NEXT: R_RISCV_RELAX # INSTR: c.bnez a0, foo diff --git a/llvm/test/MC/RISCV/linker-relaxation.s b/llvm/test/MC/RISCV/linker-relaxation.s index 6b0685baaa69..c5c4e4877ff2 100644 --- a/llvm/test/MC/RISCV/linker-relaxation.s +++ b/llvm/test/MC/RISCV/linker-relaxation.s @@ -8,49 +8,57 @@ # RUN: | llvm-readobj -r - | FileCheck -check-prefix=NORELAX-RELOC %s .long foo +# NORELAX-RELOC: R_RISCV_32 foo 0x0 +# RELAX-RELOC: R_RISCV_32 foo 0x0 call foo -# NORELAX-RELOC: R_RISCV_CALL_PLT foo 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_CALL_PLT foo 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_CALL_PLT foo 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_CALL_PLT foo 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 + +jal foo +# NORELAX-RELOC-NEXT: R_RISCV_JAL foo 0x0 +# NORELAX-RELOC-NOT: R_RISCV_RELAX +# RELAX-RELOC-NEXT: R_RISCV_JAL foo 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 lui t1, %hi(foo) -# NORELAX-RELOC: R_RISCV_HI20 foo 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_HI20 foo 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_HI20 foo 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_HI20 foo 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 addi t1, t1, %lo(foo) -# NORELAX-RELOC: R_RISCV_LO12_I foo 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_LO12_I foo 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_LO12_I foo 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_LO12_I foo 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 sb t1, %lo(foo)(a2) -# NORELAX-RELOC: R_RISCV_LO12_S foo 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_LO12_S foo 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_LO12_S foo 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_LO12_S foo 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 1: auipc t1, %pcrel_hi(foo) -# NORELAX-RELOC: R_RISCV_PCREL_HI20 foo 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_PCREL_HI20 foo 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_PCREL_HI20 foo 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_PCREL_HI20 foo 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 addi t1, t1, %pcrel_lo(1b) -# NORELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp0 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp0 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 sb t1, %pcrel_lo(1b)(a2) -# NORELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp0 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_S .Ltmp0 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp0 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_S .Ltmp0 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 # Check behaviour when a locally defined symbol is referenced. @@ -63,64 +71,88 @@ call bar # NORELAX-RELOC-NOT: R_RISCV_CALL # NORELAX-RELOC-NOT: R_RISCV_RELAX # RELAX-RELOC-NEXT: R_RISCV_CALL_PLT bar 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 + +jal bar +# NORELAX-RELOC-NOT: R_RISCV_JAL +# NORELAX-RELOC-NOT: R_RISCV_RELAX +# RELAX-RELOC-NEXT: R_RISCV_JAL bar 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 beq s1, s1, bar # NORELAX-RELOC-NOT: R_RISCV_BRANCH # RELAX-RELOC-NEXT: R_RISCV_BRANCH bar 0x0 lui t1, %hi(bar) -# NORELAX-RELOC: R_RISCV_HI20 bar 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_HI20 bar 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_HI20 bar 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_HI20 bar 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 addi t1, t1, %lo(bar) -# NORELAX-RELOC: R_RISCV_LO12_I bar 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_LO12_I bar 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_LO12_I bar 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_LO12_I bar 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 sb t1, %lo(bar)(a2) -# NORELAX-RELOC: R_RISCV_LO12_S bar 0x0 +# NORELAX-RELOC-NEXT: R_RISCV_LO12_S bar 0x0 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_LO12_S bar 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_LO12_S bar 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 2: auipc t1, %pcrel_hi(bar) # NORELAX-RELOC-NOT: R_RISCV_PCREL_HI20 # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_PCREL_HI20 bar 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_PCREL_HI20 bar 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 addi t1, t1, %pcrel_lo(2b) # NORELAX-RELOC-NOT: R_RISCV_PCREL_LO12_I # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp1 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp1 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 sb t1, %pcrel_lo(2b)(a2) # NORELAX-RELOC-NOT: R_RISCV_PCREL_LO12_S # NORELAX-RELOC-NOT: R_RISCV_RELAX -# RELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp1 0x0 -# RELAX-RELOC: R_RISCV_RELAX - 0x0 +# RELAX-RELOC-NEXT: R_RISCV_PCREL_LO12_S .Ltmp1 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 + +auipc t1, %got_pcrel_hi(bar) +# NORELAX-RELOC-NEXT: R_RISCV_GOT_HI20 bar 0x0 +# NORELAX-RELOC-NOT: R_RISCV_RELAX +# RELAX-RELOC-NEXT: R_RISCV_GOT_HI20 bar 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 + +lui t1, %tprel_hi(baz) +# NORELAX-RELOC-NEXT: R_RISCV_TPREL_HI20 baz 0x0 +# NORELAX-RELOC-NOT: R_RISCV_RELAX +# RELAX-RELOC-NEXT: R_RISCV_TPREL_HI20 baz 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 + +auipc t1, %tlsdesc_hi(baz) +# NORELAX-RELOC-NEXT: R_RISCV_TLSDESC_HI20 baz 0x0 +# NORELAX-RELOC-NOT: R_RISCV_RELAX +# RELAX-RELOC-NEXT: R_RISCV_TLSDESC_HI20 baz 0x0 +# RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 ## %hi/%lo on an absolute symbol (not yet defined) leads to relocations when relaxation is enabled. lui t2, %hi(abs) # NORELAX-RELOC-NOT: R_RISCV_ -# RELAX-RELOC: R_RISCV_HI20 - 0x12345 +# RELAX-RELOC-NEXT: R_RISCV_HI20 - 0x12345 # RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 addi t2, t2, %lo(abs) # NORELAX-RELOC-NOT: R_RISCV_ -# RELAX-RELOC: R_RISCV_LO12_I - 0x12345 +# RELAX-RELOC-NEXT: R_RISCV_LO12_I - 0x12345 # RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 .set abs, 0x12345 lui t3, %hi(abs) -# RELAX-RELOC: R_RISCV_HI20 - 0x12345 +# RELAX-RELOC-NEXT: R_RISCV_HI20 - 0x12345 # RELAX-RELOC-NEXT: R_RISCV_RELAX - 0x0 # Check that a relocation is not emitted for a symbol difference which has diff --git a/llvm/test/MC/RISCV/long-conditional-jump.s b/llvm/test/MC/RISCV/long-conditional-jump.s index 5f10baed4982..db060bafccaa 100644 --- a/llvm/test/MC/RISCV/long-conditional-jump.s +++ b/llvm/test/MC/RISCV/long-conditional-jump.s @@ -1,8 +1,8 @@ # RUN: llvm-mc -filetype=obj -triple=riscv64 %s \ -# RUN: | llvm-objdump -d -M no-aliases - \ +# RUN: | llvm-objdump -dr -M no-aliases - \ # RUN: | FileCheck --check-prefix=CHECK-INST %s # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+c %s \ -# RUN: | llvm-objdump -d -M no-aliases - \ +# RUN: | llvm-objdump -dr -M no-aliases - \ # RUN: | FileCheck --check-prefix=CHECK-INST-C %s # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s \ # RUN: | llvm-objdump -dr -M no-aliases - \ @@ -21,9 +21,11 @@ test: # CHECK-INST-RELAX: beq a0, a1, 0x8 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} # CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L1 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: beq a0, a1, 0x8 # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} # CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L1 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* bne a0, a1, .L1 call relax .fill 1300-2, 4, 0 @@ -35,8 +37,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0x28b2 # CHECK-INST-RELAX: bne a0, a1, 0x1464 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L2 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: bne a0, a1, 0x1462 # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L2 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* beq a0, a1, .L2 .fill 1300, 4, 0 .L2: @@ -47,8 +53,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0x3d0c # CHECK-INST-RELAX: bge a0, a1, 0x28c0 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L3 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: bge a0, a1, 0x28bc # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L3 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* blt a0, a1, .L3 .fill 1300, 4, 0 .L3: @@ -59,8 +69,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0x5166 # CHECK-INST-RELAX: blt a0, a1, 0x3d1c # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L4 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: blt a0, a1, 0x3d16 # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L4 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* bge a0, a1, .L4 .fill 1300, 4, 0 .L4: @@ -71,8 +85,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0x65c0 # CHECK-INST-RELAX: bgeu a0, a1, 0x5178 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L5 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: bgeu a0, a1, 0x5170 # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L5 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* bltu a0, a1, .L5 .fill 1300, 4, 0 .L5: @@ -83,8 +101,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0x7a1a # CHECK-INST-RELAX: bltu a0, a1, 0x65d4 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L6 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: bltu a0, a1, 0x65ca # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L6 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* bgeu a0, a1, .L6 .fill 1300, 4, 0 .L6: @@ -95,8 +117,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0x8e72 # CHECK-INST-RELAX: bne a0, zero, 0x7a30 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L7 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: c.bnez a0, 0x7a22 # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L7 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* beqz a0, .L7 .fill 1300, 4, 0 .L7: @@ -107,8 +133,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0xa2ca # CHECK-INST-RELAX: bne zero, a0, 0x8e8c # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L8 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: c.bnez a0, 0x8e7a # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L8 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* beq x0, a0, .L8 .fill 1300, 4, 0 .L8: @@ -119,8 +149,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0xb722 # CHECK-INST-RELAX: beq a0, zero, 0xa2e8 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L9 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: c.beqz a0, 0xa2d2 # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L9 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* bnez a0, .L9 .fill 1300, 4, 0 .L9: @@ -131,8 +165,12 @@ test: # CHECK-INST-C-NEXT: jal zero, 0xcb7c # CHECK-INST-RELAX: beq a6, zero, 0xb744 # CHECK-INST-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-RELAX-NEXT: R_RISCV_JAL .L10 +# CHECK_INST-RELAX-NEXT: R_RISCV_RELAX *ABS* # CHECK-INST-C-RELAX: beq a6, zero, 0xb72c # CHECK-INST-C-RELAX-NEXT: jal zero, {{.*}} +# CHECK-INST-C-RELAX-NEXT: R_RISCV_JAL .L10 +# CHECK_INST-C-RELAX-NEXT: R_RISCV_RELAX *ABS* bnez x16, .L10 .fill 1300, 4, 0 .L10: diff --git a/llvm/test/MC/RISCV/option-relax.s b/llvm/test/MC/RISCV/option-relax.s index 55cdbeae01a4..e591c824eb43 100644 --- a/llvm/test/MC/RISCV/option-relax.s +++ b/llvm/test/MC/RISCV/option-relax.s @@ -39,6 +39,7 @@ call bar .dword .L2-.L1 # CHECK-RELOC-NEXT: R_RISCV_JAL +# CHECK-RELOC-NEXT: R_RISCV_RELAX jal zero, .L1 # CHECK-RELOC-NEXT: R_RISCV_BRANCH beq s1, s1, .L1 diff --git a/llvm/test/MC/RISCV/tlsdesc.s b/llvm/test/MC/RISCV/tlsdesc.s index 675b01ac0225..d66b0d3321ee 100644 --- a/llvm/test/MC/RISCV/tlsdesc.s +++ b/llvm/test/MC/RISCV/tlsdesc.s @@ -1,6 +1,10 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 < %s --defsym RV32=1 | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV32 # RUN: llvm-mc -filetype=obj -triple riscv64 < %s | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RV64 +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s --mattr=+relax --defsym RV32=1 | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RELAX,RV32 +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s --mattr=+relax | llvm-objdump -dr -M no-aliases - | FileCheck %s --check-prefixes=INST,RELAX,RV64 + + # RUN: not llvm-mc -triple riscv32 < %s --defsym RV32=1 --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR # RUN: not llvm-mc -triple riscv64 < %s --defsym ERR=1 2>&1 | FileCheck %s --check-prefixes=ERR @@ -10,9 +14,11 @@ start: # @start auipc a0, %tlsdesc_hi(a-4) # INST: auipc a0, 0x0 # INST-NEXT: R_RISCV_TLSDESC_HI20 a-0x4 + # RELAX-NEXT: R_RISCV_RELAX auipc a0, %tlsdesc_hi(unspecified) # INST-NEXT: auipc a0, 0x0 # INST-NEXT: R_RISCV_TLSDESC_HI20 unspecified + # RELAX-NEXT: R_RISCV_RELAX .ifdef RV32 lw a1, %tlsdesc_load_lo(.Ltlsdesc_hi0)(a0) # RV32: lw a1, 0x0(a0) diff --git a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s index 17cd3a309404..6122981f82e2 100644 --- a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s +++ b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s @@ -61,9 +61,9 @@ mid_jump_over_fixed: .space 0x1000 # CHECK-NEXT: ... j mid_jump_over_fixed -# CHECK-NEXT: jal zero, 0x24 -# CHECK-NOT: R_RISCV_JAL -# CHECK-NOT: R_RISCV_RELAX +# CHECK-NEXT: jal zero, 0x1026 +# CHECK-NEXT: R_RISCV_JAL mid_jump_over_fixed +# CHECK-NEXT: R_RISCV_RELAX *ABS* ret # CHECK-NEXT: c.jr ra @@ -79,6 +79,6 @@ mid_jump_over_relaxable: j mid_jump_over_relaxable # CHECK-NEXT: jal zero, 0x2034 # CHECK-NEXT: R_RISCV_JAL mid_jump_over_relaxable -# CHECK-NOT: R_RISCV_RELAX +# CHECK-NEXT: R_RISCV_RELAX ret # CHECK-NEXT: c.jr ra diff --git a/llvm/test/MC/RISCV/xqcibi-relocations.s b/llvm/test/MC/RISCV/xqcibi-relocations.s index 00857ef368e1..0ab860667fae 100644 --- a/llvm/test/MC/RISCV/xqcibi-relocations.s +++ b/llvm/test/MC/RISCV/xqcibi-relocations.s @@ -91,12 +91,14 @@ qc.e.bgeui s2, 24, same_section # OBJ: qc.beqi t1, 0xa, 0x42 # OBJ-NEXT: j 0x3e # OBJ-NEXT: R_RISCV_JAL undef{{$}} +# OBJ-NEXT: R_RISCV_RELAX *ABS*{{$}} qc.bnei t1, 10, undef # ASM: qc.e.bgeui s0, 40, undef # OBJ-NEXT: qc.e.bltui s0, 0x28, 0x4c # OBJ-NEXT: j 0x48 # OBJ-NEXT: R_RISCV_JAL undef{{$}} +# OBJ-NEXT: R_RISCV_RELAX *ABS*{{$}} qc.e.bgeui s0, 40, undef .section .text.second, "ax", @progbits