shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity

[RISCV] Extract vector from passthru when combining tuple_extract+vlseg. (#172743)

Browse Source 
The passthru operand is a tuple. We need to extract the correct field
vector from it.

Existing tests only handled the undef passthru case which accidentally
worked. Possibly due to IMPLICIT_DEF being converted to noreg.

Fixes #172628.
This commit is contained in:
Craig Topper 2025-12-17 22:45:47 -08:00 committed by GitHub
parent 8e648380a1
commit 50ea2d8551
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 26 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -21891,10 +21891,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
unsigned Stride = SEW / 8 * NF;
unsigned Offset = SEW / 8 * Idx;
SDValue Passthru = Tuple.getOperand(2);
if (Passthru.isUndef())
Passthru = DAG.getUNDEF(VT);
else
Passthru = DAG.getNode(RISCVISD::TUPLE_EXTRACT, DL, VT, Passthru,
N->getOperand(1));
SDValue Ops[] = {
/*Chain=*/Tuple.getOperand(0),
/*IntID=*/DAG.getTargetConstant(Intrinsic::riscv_vlse_mask, DL, XLenVT),
/*Passthru=*/Tuple.getOperand(2),
/*Passthru=*/Passthru,
/*Ptr=*/
DAG.getNode(ISD::ADD, DL, XLenVT, Tuple.getOperand(3),
DAG.getConstant(Offset, DL, XLenVT)),

18
llvm/test/CodeGen/RISCV/rvv/tuple-extract-vlseg.ll Normal file
View File

@ -0,0 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
define <vscale x 1 x i8> @test_vlseg3_mask_nxv16i8_triscv.vector.tuple_nxv1i8_3t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %passthru) {
; CHECK-LABEL: test_vlseg3_mask_nxv16i8_triscv.vector.tuple_nxv1i8_3t:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: addi a0, a0, 1
; CHECK-NEXT: li a2, 3
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vlse8.v v8, (a0), a2, v0.t
; CHECK-NEXT: ret
entry:
%0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv16i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %passthru, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 3)
%1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_3t(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, i32 1)
ret <vscale x 1 x i8> %1
}