[X86][MC] Fix offset for R_X86_64_CODE_6_GOTTPOFF fixup (#119496)
1. Fix the offset for R_X86_64_CODE_6_GOTTPOFF fixup, which is introduced by #117277. It should be biased with the size of the immediate field. Related tests are updated. 2. Rename reloc_riprel_6byte_relax to reloc_riprel_4byte_relax_evex as the number of bytes represents the size of fixup, and "evex" suffix is added as it's used for APX NDD/NF instructions with EVEX prefix. 3. Remove incorrectly setting R_X86_64_CODE_6_GOTTPOFF relocation type for APX NDD/NF instructions with GOTPCREL symbol reference modifier.
This commit is contained in:
Feng Zou
GitHub
parent
768754807f
commit
51001f87f1
@ -28,17 +28,17 @@
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// DISASM-NEXT: addq $-8, %r28
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// DISASM-NEXT: addq $-4, %r16
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# NDD
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// DISASM-NEXT: addq $-10, %r16, %r16
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// DISASM-NEXT: addq $-10, %r16, %r20
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// DISASM-NEXT: addq $-10, %r16, %rax
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// DISASM-NEXT: addq $-10, %rax, %r16
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// DISASM-NEXT: addq $-10, %r8, %r16
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// DISASM-NEXT: addq $-10, %rax, %r12
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// DISASM-NEXT: addq $-8, %r16, %r16
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// DISASM-NEXT: addq $-8, %r16, %r20
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// DISASM-NEXT: addq $-8, %r16, %rax
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// DISASM-NEXT: addq $-8, %rax, %r16
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// DISASM-NEXT: addq $-8, %r8, %r16
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// DISASM-NEXT: addq $-8, %rax, %r12
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# NDD + NF
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// DISASM-NEXT: {nf} addq $-10, %r8, %r16
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// DISASM-NEXT: {nf} addq $-10, %rax, %r12
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// DISASM-NEXT: {nf} addq $-8, %r8, %r16
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// DISASM-NEXT: {nf} addq $-8, %rax, %r12
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# NF
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// DISASM-NEXT: {nf} addq $-10, %r12
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// DISASM-NEXT: {nf} addq $-8, %r12
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// LD to LE:
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// DISASM-NEXT: movq %fs:0, %rax
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@ -17,21 +17,21 @@
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## &.got[1] - 0x1286 = 0x2380 - 0x1286 = 4346
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## &.got[2] - 0x128e = 0x2378 - 0x128e = 4330
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## &.got[3] - 0x1296 = 0x2380 - 0x1296 = 4330
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## &.got[0] - 0x12a0 = 0x2376 - 0x12a0 = 4310
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## &.got[1] - 0x12aa = 0x237e - 0x12aa = 4308
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## &.got[0] - 0x12b4 = 0x2376 - 0x12b4 = 4290
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## &.got[1] - 0x12be = 0x237e - 0x12be = 4288
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## &.got[0] - 0x12c8 = 0x2376 - 0x12c8 = 4270
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## &.got[0] - 0x12a0 = 0x2378 - 0x12a0 = 4312
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## &.got[1] - 0x12aa = 0x2380 - 0x12aa = 4310
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## &.got[0] - 0x12b4 = 0x2378 - 0x12b4 = 4292
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## &.got[1] - 0x12be = 0x2380 - 0x12be = 4290
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## &.got[0] - 0x12c8 = 0x2378 - 0x12c8 = 4272
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# CHECK: 1278: addq 4345(%rip), %rax
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# CHECK-NEXT: 127f: addq 4346(%rip), %rax
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# CHECK-NEXT: 1286: addq 4330(%rip), %r16
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# CHECK-NEXT: 128e: addq 4330(%rip), %r16
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# CHECK-NEXT: 1296: addq %r8, 4310(%rip), %r16
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# CHECK-NEXT: 12a0: addq 4308(%rip), %rax, %r12
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# CHECK-NEXT: 12aa: {nf} addq %r8, 4290(%rip), %r16
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# CHECK-NEXT: 12b4: {nf} addq 4288(%rip), %rax, %r12
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# CHECK-NEXT: 12be: {nf} addq 4270(%rip), %r12
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# CHECK-NEXT: 1296: addq %r8, 4312(%rip), %r16
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# CHECK-NEXT: 12a0: addq 4310(%rip), %rax, %r12
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# CHECK-NEXT: 12aa: {nf} addq %r8, 4292(%rip), %r16
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# CHECK-NEXT: 12b4: {nf} addq 4290(%rip), %rax, %r12
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# CHECK-NEXT: 12be: {nf} addq 4272(%rip), %r12
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addq foo@GOTTPOFF(%rip), %rax
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addq bar@GOTTPOFF(%rip), %rax
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@ -634,7 +634,7 @@ const MCFixupKindInfo &X86AsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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{"reloc_riprel_4byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_4byte_relax_rex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_4byte_relax_rex2", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_6byte_relax", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_riprel_4byte_relax_evex", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
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{"reloc_signed_4byte", 0, 32, 0},
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{"reloc_signed_4byte_relax", 0, 32, 0},
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{"reloc_global_offset_table", 0, 32, 0},
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@ -684,7 +684,7 @@ static unsigned getFixupKindSize(unsigned Kind) {
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case X86::reloc_riprel_4byte_relax_rex2:
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case X86::reloc_riprel_4byte_movq_load:
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case X86::reloc_riprel_4byte_movq_load_rex2:
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case X86::reloc_riprel_6byte_relax:
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case X86::reloc_riprel_4byte_relax_evex:
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case X86::reloc_signed_4byte:
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case X86::reloc_signed_4byte_relax:
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case X86::reloc_global_offset_table:
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@ -77,7 +77,7 @@ static X86_64RelType getType64(MCFixupKind Kind,
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case X86::reloc_riprel_4byte_relax_rex2:
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case X86::reloc_riprel_4byte_movq_load:
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case X86::reloc_riprel_4byte_movq_load_rex2:
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case X86::reloc_riprel_6byte_relax:
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case X86::reloc_riprel_4byte_relax_evex:
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return RT64_32;
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case X86::reloc_branch_4byte_pcrel:
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Modifier = MCSymbolRefExpr::VK_PLT;
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@ -203,7 +203,7 @@ static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
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if ((unsigned)Kind == X86::reloc_riprel_4byte_movq_load_rex2 ||
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(unsigned)Kind == X86::reloc_riprel_4byte_relax_rex2)
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return ELF::R_X86_64_CODE_4_GOTTPOFF;
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else if ((unsigned)Kind == X86::reloc_riprel_6byte_relax)
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else if ((unsigned)Kind == X86::reloc_riprel_4byte_relax_evex)
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return ELF::R_X86_64_CODE_6_GOTTPOFF;
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return ELF::R_X86_64_GOTTPOFF;
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case MCSymbolRefExpr::VK_TLSLD:
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@ -230,8 +230,6 @@ static unsigned getRelocType64(MCContext &Ctx, SMLoc Loc,
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case X86::reloc_riprel_4byte_relax_rex2:
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case X86::reloc_riprel_4byte_movq_load_rex2:
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return ELF::R_X86_64_CODE_4_GOTPCRELX;
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case X86::reloc_riprel_6byte_relax:
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return ELF::R_X86_64_CODE_6_GOTTPOFF;
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}
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llvm_unreachable("unexpected relocation type!");
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case MCSymbolRefExpr::VK_GOTPCREL_NORELAX:
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@ -24,8 +24,9 @@ enum Fixups {
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// instruction with rex prefix
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reloc_riprel_4byte_relax_rex2, // 32-bit rip-relative in relaxable
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// instruction with rex2 prefix
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reloc_riprel_6byte_relax, // 32-bit rip-relative in relaxable
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// instruction with APX NDD
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reloc_riprel_4byte_relax_evex, // 32-bit rip-relative in relaxable
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// instruction of APX NDD/NF with
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// EVEX prefix
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reloc_signed_4byte, // 32-bit signed. Unlike FK_Data_4
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// this will be sign extended at
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// runtime.
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@ -572,15 +572,15 @@ void X86MCCodeEmitter::emitImmediate(const MCOperand &DispOp, SMLoc Loc,
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax) ||
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex) ||
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_rex2) ||
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FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel)) {
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FixupKind == MCFixupKind(X86::reloc_branch_4byte_pcrel) ||
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FixupKind == MCFixupKind(X86::reloc_riprel_4byte_relax_evex)) {
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ImmOffset -= 4;
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// If this is a pc-relative load off _GLOBAL_OFFSET_TABLE_:
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// leaq _GLOBAL_OFFSET_TABLE_(%rip), %r15
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// this needs to be a GOTPC32 relocation.
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if (startsWithGlobalOffsetTable(Expr) != GOT_None)
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FixupKind = MCFixupKind(X86::reloc_global_offset_table);
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} else if (FixupKind == MCFixupKind(X86::reloc_riprel_6byte_relax))
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ImmOffset -= 6;
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}
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if (FixupKind == FK_PCRel_2)
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ImmOffset -= 2;
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@ -677,7 +677,7 @@ void X86MCCodeEmitter::emitMemModRMByte(
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case X86::ADD64mr_ND:
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case X86::ADD64mr_NF_ND:
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case X86::ADD64rm_NF_ND:
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return X86::reloc_riprel_6byte_relax;
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return X86::reloc_riprel_4byte_relax_evex;
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}
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}();
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@ -70,7 +70,7 @@ static bool isFixupKindRIPRel(unsigned Kind) {
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Kind == X86::reloc_riprel_4byte_relax ||
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Kind == X86::reloc_riprel_4byte_relax_rex ||
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Kind == X86::reloc_riprel_4byte_relax_rex2 ||
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Kind == X86::reloc_riprel_6byte_relax;
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Kind == X86::reloc_riprel_4byte_relax_evex;
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}
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static unsigned getFixupKindLog2Size(unsigned Kind) {
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@ -92,7 +92,7 @@ static unsigned getFixupKindLog2Size(unsigned Kind) {
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case X86::reloc_signed_4byte:
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case X86::reloc_signed_4byte_relax:
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case X86::reloc_branch_4byte_pcrel:
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case X86::reloc_riprel_6byte_relax:
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case X86::reloc_riprel_4byte_relax_evex:
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case FK_Data_4: return 2;
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case FK_Data_8: return 3;
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}
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@ -70,7 +70,7 @@ unsigned X86WinCOFFObjectWriter::getRelocType(MCContext &Ctx,
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case X86::reloc_riprel_4byte_relax:
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case X86::reloc_riprel_4byte_relax_rex:
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case X86::reloc_riprel_4byte_relax_rex2:
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case X86::reloc_riprel_6byte_relax:
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case X86::reloc_riprel_4byte_relax_evex:
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case X86::reloc_branch_4byte_pcrel:
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return COFF::IMAGE_REL_AMD64_REL32;
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case FK_Data_4:
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@ -90,11 +90,11 @@ weak_sym:
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// CHECK-NEXT: 0x2D R_X86_64_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x35 R_X86_64_CODE_4_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x3D R_X86_64_CODE_4_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x47 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
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// CHECK-NEXT: 0x51 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
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// CHECK-NEXT: 0x5B R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
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// CHECK-NEXT: 0x65 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
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// CHECK-NEXT: 0x6F R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFA
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// CHECK-NEXT: 0x47 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x51 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x5B R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x65 R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x6F R_X86_64_CODE_6_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x76 R_X86_64_TLSGD foo 0xFFFFFFFFFFFFFFFC
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// CHECK-NEXT: 0x7D R_X86_64_TPOFF32 foo 0x0
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// CHECK-NEXT: 0x84 R_X86_64_TLSLD foo 0xFFFFFFFFFFFFFFFC
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