[RISCV] Remove mask size restriction on single source and dual src shuffle costing (try 2)
Some callers pass in an empty mask to represent "unknown". We should use the generic costs for these cases. We can add VL=1 costing seperately if desired. Reapplying after revert. A new test had been added, and I'd missed updating it when rebasing before. This is a great happy accident as I hadn't figured out how to get SLP to exercise this case, I'd merely noticed it via inspection.
This commit is contained in:
Philip Reames
Philip Reames
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5eb44df1b6
commit
514b38cd7e
@ -324,36 +324,33 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
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return LT.first * getLMULCost(LT.second);
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}
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}
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// vrgather + cost of generating the mask constant.
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// We model this for an unknown mask with a single vrgather.
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if (LT.first == 1 &&
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(LT.second.getScalarSizeInBits() != 8 ||
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LT.second.getVectorNumElements() <= 256)) {
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VectorType *IdxTy = getVRGatherIndexType(LT.second, *ST, Tp->getContext());
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InstructionCost IndexCost = getConstantPoolLoadCost(IdxTy, CostKind);
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return IndexCost + getVRGatherVVCost(LT.second);
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}
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}
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// vrgather + cost of generating the mask constant.
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// We model this for an unknown mask with a single vrgather.
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if (LT.second.isFixedLengthVector() && LT.first == 1 &&
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(LT.second.getScalarSizeInBits() != 8 ||
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LT.second.getVectorNumElements() <= 256)) {
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VectorType *IdxTy = getVRGatherIndexType(LT.second, *ST, Tp->getContext());
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InstructionCost IndexCost = getConstantPoolLoadCost(IdxTy, CostKind);
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return IndexCost + getVRGatherVVCost(LT.second);
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}
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[[fallthrough]];
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}
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case TTI::SK_Transpose:
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case TTI::SK_PermuteTwoSrc: {
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if (Mask.size() >= 2 && LT.second.isFixedLengthVector()) {
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// 2 x (vrgather + cost of generating the mask constant) + cost of mask
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// register for the second vrgather. We model this for an unknown
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// (shuffle) mask.
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if (LT.first == 1 &&
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(LT.second.getScalarSizeInBits() != 8 ||
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LT.second.getVectorNumElements() <= 256)) {
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auto &C = Tp->getContext();
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auto EC = Tp->getElementCount();
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VectorType *IdxTy = getVRGatherIndexType(LT.second, *ST, C);
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VectorType *MaskTy = VectorType::get(IntegerType::getInt1Ty(C), EC);
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InstructionCost IndexCost = getConstantPoolLoadCost(IdxTy, CostKind);
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InstructionCost MaskCost = getConstantPoolLoadCost(MaskTy, CostKind);
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return 2 * IndexCost + 2 * getVRGatherVVCost(LT.second) + MaskCost;
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}
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// 2 x (vrgather + cost of generating the mask constant) + cost of mask
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// register for the second vrgather. We model this for an unknown
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// (shuffle) mask.
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if (LT.second.isFixedLengthVector() && LT.first == 1 &&
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(LT.second.getScalarSizeInBits() != 8 ||
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LT.second.getVectorNumElements() <= 256)) {
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auto &C = Tp->getContext();
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auto EC = Tp->getElementCount();
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VectorType *IdxTy = getVRGatherIndexType(LT.second, *ST, C);
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VectorType *MaskTy = VectorType::get(IntegerType::getInt1Ty(C), EC);
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InstructionCost IndexCost = getConstantPoolLoadCost(IdxTy, CostKind);
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InstructionCost MaskCost = getConstantPoolLoadCost(MaskTy, CostKind);
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return 2 * IndexCost + 2 * getVRGatherVVCost(LT.second) + MaskCost;
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}
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[[fallthrough]];
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}
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@ -1,13 +1,13 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \
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; RUN: -riscv-v-vector-bits-min=128 -riscv-v-slp-max-vf=0 -S \
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; RUN: | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \
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; RUN: -riscv-v-vector-bits-min=256 -riscv-v-slp-max-vf=0 -S \
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; RUN: | FileCheck %s --check-prefixes=CHECK
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; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v \
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; RUN: -riscv-v-vector-bits-min=512 -riscv-v-slp-max-vf=0 -S \
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; RUN: | FileCheck %s --check-prefixes=CHECK
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; RUN: -riscv-v-slp-max-vf=0 -S \
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; RUN: | FileCheck %s --check-prefixes=CHECK,ZVL128
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; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v,+zvl256b \
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; RUN: -riscv-v-slp-max-vf=0 -S \
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; RUN: | FileCheck %s --check-prefixes=CHECK,ZVL256
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; RUN: opt < %s -passes=slp-vectorizer -mtriple=riscv64 -mattr=+v,+zvl512b \
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; RUN: -riscv-v-slp-max-vf=0 -S \
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; RUN: | FileCheck %s --check-prefixes=CHECK,ZVL512
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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@ -274,20 +274,47 @@ entry:
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}
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define void @reduce_or_2() {
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; CHECK-LABEL: @reduce_or_2(
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; CHECK-NEXT: [[TMP1:%.*]] = shl i64 0, 0
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; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP1]], i32 15
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <16 x i64> [[TMP2]], zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP1]], i32 6
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; CHECK-NEXT: [[TMP5:%.*]] = icmp ult <16 x i64> [[TMP4]], zeroinitializer
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; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
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; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP5]])
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; CHECK-NEXT: [[OP_RDX:%.*]] = or i1 [[TMP6]], [[TMP7]]
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; CHECK-NEXT: br i1 [[OP_RDX]], label [[TMP9:%.*]], label [[TMP8:%.*]]
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; CHECK: 8:
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; CHECK-NEXT: ret void
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; CHECK: 9:
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; CHECK-NEXT: ret void
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; ZVL128-LABEL: @reduce_or_2(
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; ZVL128-NEXT: [[TMP1:%.*]] = shl i64 0, 0
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; ZVL128-NEXT: [[TMP2:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP1]], i32 15
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; ZVL128-NEXT: [[TMP3:%.*]] = icmp ult <16 x i64> [[TMP2]], zeroinitializer
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; ZVL128-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP1]], i32 6
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; ZVL128-NEXT: [[TMP5:%.*]] = icmp ult <16 x i64> [[TMP4]], zeroinitializer
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; ZVL128-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
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; ZVL128-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP5]])
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; ZVL128-NEXT: [[OP_RDX:%.*]] = or i1 [[TMP6]], [[TMP7]]
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; ZVL128-NEXT: br i1 [[OP_RDX]], label [[TMP9:%.*]], label [[TMP8:%.*]]
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; ZVL128: 8:
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; ZVL128-NEXT: ret void
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; ZVL128: 9:
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; ZVL128-NEXT: ret void
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;
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; ZVL256-LABEL: @reduce_or_2(
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; ZVL256-NEXT: [[TMP1:%.*]] = shl i64 0, 0
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; ZVL256-NEXT: [[TMP2:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP1]], i32 15
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; ZVL256-NEXT: [[TMP3:%.*]] = icmp ult <16 x i64> [[TMP2]], zeroinitializer
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; ZVL256-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP1]], i32 6
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; ZVL256-NEXT: [[TMP5:%.*]] = icmp ult <16 x i64> [[TMP4]], zeroinitializer
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; ZVL256-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
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; ZVL256-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP5]])
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; ZVL256-NEXT: [[OP_RDX:%.*]] = or i1 [[TMP6]], [[TMP7]]
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; ZVL256-NEXT: br i1 [[OP_RDX]], label [[TMP9:%.*]], label [[TMP8:%.*]]
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; ZVL256: 8:
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; ZVL256-NEXT: ret void
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; ZVL256: 9:
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; ZVL256-NEXT: ret void
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;
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; ZVL512-LABEL: @reduce_or_2(
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; ZVL512-NEXT: [[TMP1:%.*]] = shl i64 0, 0
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; ZVL512-NEXT: [[TMP2:%.*]] = insertelement <32 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP1]], i32 15
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; ZVL512-NEXT: [[TMP3:%.*]] = shufflevector <32 x i64> [[TMP2]], <32 x i64> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 15, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
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; ZVL512-NEXT: [[TMP4:%.*]] = icmp ult <32 x i64> [[TMP3]], zeroinitializer
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; ZVL512-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> [[TMP4]])
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; ZVL512-NEXT: br i1 [[TMP5]], label [[TMP7:%.*]], label [[TMP6:%.*]]
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; ZVL512: 6:
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; ZVL512-NEXT: ret void
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; ZVL512: 7:
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; ZVL512-NEXT: ret void
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;
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%1 = shl i64 0, 0
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%2 = icmp ult i64 0, 0
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