diff --git a/llvm/test/TableGen/MacroFusion.td b/llvm/test/TableGen/MacroFusion.td
index 5732c6c655d7..e4034bfa108c 100644
--- a/llvm/test/TableGen/MacroFusion.td
+++ b/llvm/test/TableGen/MacroFusion.td
@@ -268,7 +268,7 @@ def TestFirstSameRegFusion: Fusion<"test-first-same-reg-fusion", "HasTestFirstSa
 // CHECK-SUBTARGET: { "test-single-fusion", "Test SingleFusion", Test::TestSingleFusion
 
 // Check that we have generated `getMacroFusions()` function.
-// CHECK-SUBTARGET:      std::vector<MacroFusionPredTy> getMacroFusions() const override;
+// CHECK-SUBTARGET:      std::vector<MacroFusionPredTy> getMacroFusions() const final;
 
 // CHECK-SUBTARGET:      std::vector<MacroFusionPredTy> TestGenSubtargetInfo::getMacroFusions() const {
 // CHECK-SUBTARGET-NEXT:   std::vector<MacroFusionPredTy> Fusions;
diff --git a/llvm/test/TableGen/ResolveSchedClass.td b/llvm/test/TableGen/ResolveSchedClass.td
index c7c31869b82e..665f5db85f22 100644
--- a/llvm/test/TableGen/ResolveSchedClass.td
+++ b/llvm/test/TableGen/ResolveSchedClass.td
@@ -80,7 +80,7 @@ def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
 
 // CHECK: unsigned resolveVariantSchedClass(unsigned SchedClass,
 // CHECK-NEXT:    const MCInst *MI, const MCInstrInfo *MCII,
-// CHECK-NEXT:    unsigned CPUID) const override {
+// CHECK-NEXT:    unsigned CPUID) const final {
 // CHECK-NEXT:   return TestTarget_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);
 // CHECK-NEXT: }
 
diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp
index 27299fdda3e0..8ec9794b6181 100644
--- a/llvm/utils/TableGen/SubtargetEmitter.cpp
+++ b/llvm/utils/TableGen/SubtargetEmitter.cpp
@@ -2009,17 +2009,17 @@ void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
      << "                      WPR, WL, RA, IS, OC, FP) { }\n\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
      << "      const MCInst *MI, const MCInstrInfo *MCII,\n"
-     << "      unsigned CPUID) const override {\n"
+     << "      unsigned CPUID) const final {\n"
      << "    return " << Target << "_MC"
      << "::resolveVariantSchedClassImpl(SchedClass, MI, MCII, *this, CPUID);\n";
   OS << "  }\n";
   if (TGT.getHwModes().getNumModeIds() > 1) {
-    OS << "  unsigned getHwModeSet() const override;\n";
+    OS << "  unsigned getHwModeSet() const final;\n";
     OS << "  unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
-          "override;\n";
+          "final;\n";
   }
   if (Target == "AArch64")
-    OS << "  bool isCPUStringValid(StringRef CPU) const override {\n"
+    OS << "  bool isCPUStringValid(StringRef CPU) const final {\n"
        << "    CPU = AArch64::resolveCPUAlias(CPU);\n"
        << "    return MCSubtargetInfo::isCPUStringValid(CPU);\n"
        << "  }\n";
@@ -2137,10 +2137,10 @@ void SubtargetEmitter::emitHeader(raw_ostream &OS) {
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
-     << " const TargetSchedModel *SchedModel) const override;\n"
+     << " const TargetSchedModel *SchedModel) const final;\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,"
      << " const MCInst *MI, const MCInstrInfo *MCII,"
-     << " unsigned CPUID) const override;\n"
+     << " unsigned CPUID) const final;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
      << " const;\n";
 
@@ -2163,13 +2163,13 @@ void SubtargetEmitter::emitHeader(raw_ostream &OS) {
     }
     OS << "  };\n";
 
-    OS << "  unsigned getHwModeSet() const override;\n";
+    OS << "  unsigned getHwModeSet() const final;\n";
     OS << "  unsigned getHwMode(enum HwModeType type = HwMode_Default) const "
-          "override;\n";
+          "final;\n";
   }
   if (TGT.hasMacroFusion())
     OS << "  std::vector<MacroFusionPredTy> getMacroFusions() const "
-          "override;\n";
+          "final;\n";
 
   STIPredicateExpander PE(Target);
   PE.setByRef(false);