From 52c2e45c11ee37d8efcf87cbfa5c9f23cbdd566b Mon Sep 17 00:00:00 2001 From: Rahul Joshi Date: Fri, 23 May 2025 08:30:29 -0700 Subject: [PATCH] [NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101) --- llvm/include/llvm/CodeGen/PeepholeOptimizer.h | 3 +-- llvm/lib/Passes/PassBuilder.cpp | 27 +++++++++---------- .../Target/AArch64/AArch64A53Fix835769.cpp | 3 +-- .../AArch64/AArch64A57FPLoadBalancing.cpp | 3 +-- llvm/lib/Target/AArch64/AArch64CollectLOH.cpp | 3 +-- .../AArch64/AArch64CompressJumpTables.cpp | 3 +-- .../Target/AArch64/AArch64FalkorHWPFFix.cpp | 3 +-- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 +- .../AArch64/AArch64LoadStoreOptimizer.cpp | 3 +-- .../AArch64LowerHomogeneousPrologEpilog.cpp | 4 +-- .../AArch64RedundantCopyElimination.cpp | 3 +-- .../Target/AArch64/AArch64RegisterInfo.cpp | 3 +-- .../GISel/AArch64O0PreLegalizerCombiner.cpp | 3 +-- .../GISel/AArch64PostLegalizerCombiner.cpp | 7 ++--- .../GISel/AArch64PostLegalizerLowering.cpp | 7 ++--- .../GISel/AArch64PostSelectOptimize.cpp | 7 ++--- .../GISel/AArch64PreLegalizerCombiner.cpp | 3 +-- .../AMDGPU/AMDGPUPostLegalizerCombiner.cpp | 3 +-- .../AMDGPU/AMDGPUPreLegalizerCombiner.cpp | 3 +-- .../Target/AMDGPU/AMDGPURegBankCombiner.cpp | 3 +-- .../Target/AMDGPU/AMDGPURegBankLegalize.cpp | 6 ++--- .../lib/Target/AMDGPU/AMDGPURegBankSelect.cpp | 6 ++--- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 3 +-- llvm/lib/Target/AMDGPU/GCNDPPCombine.h | 3 +-- .../AMDGPU/R600MachineCFGStructurizer.cpp | 3 +-- .../AMDGPU/R600OptimizeVectorRegisters.cpp | 3 +-- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 3 +-- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 3 +-- llvm/lib/Target/AMDGPU/SIFoldOperands.h | 3 +-- .../lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 3 +-- .../Target/AMDGPU/SILoadStoreOptimizer.cpp | 3 +-- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h | 3 +-- llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 3 +-- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 4 +-- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h | 4 +-- .../Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp | 6 ++--- .../Target/AMDGPU/SIOptimizeVGPRLiveRange.h | 6 ++--- .../Target/AMDGPU/SIShrinkInstructions.cpp | 10 +++---- llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 3 +-- llvm/lib/Target/AMDGPU/SIWholeQuadMode.h | 3 +-- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 3 +-- llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 3 +-- .../ARM/ARMFixCortexA57AES1742098Pass.cpp | 3 +-- llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +- llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 3 +-- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 6 ++--- .../Target/ARM/ARMOptimizeBarriersPass.cpp | 3 +-- llvm/lib/Target/ARM/MVEVPTBlockPass.cpp | 3 +-- llvm/lib/Target/ARM/Thumb1FrameLowering.cpp | 2 +- llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp | 3 +-- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 3 +-- .../Target/CSKY/CSKYConstantIslandPass.cpp | 3 +-- .../Target/Hexagon/HexagonCFGOptimizer.cpp | 3 +-- .../Target/Hexagon/HexagonCopyToCombine.cpp | 3 +-- .../Target/Hexagon/HexagonFixupHwLoops.cpp | 3 +-- .../Target/Hexagon/HexagonFrameLowering.cpp | 3 +-- llvm/lib/Target/Hexagon/HexagonGenMux.cpp | 3 +-- .../Target/Hexagon/HexagonNewValueJump.cpp | 3 +-- llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp | 3 +-- .../Hexagon/HexagonSplitConst32AndConst64.cpp | 3 +-- .../Target/Hexagon/HexagonVLIWPacketizer.cpp | 6 ++--- .../lib/Target/Lanai/LanaiDelaySlotFiller.cpp | 3 +-- llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp | 3 +-- .../LoongArch/LoongArchISelLowering.cpp | 2 +- .../LoongArch/LoongArchMergeBaseOffset.cpp | 3 +-- llvm/lib/Target/M68k/M68kExpandPseudo.cpp | 3 +-- .../Target/MSP430/MSP430BranchSelector.cpp | 3 +-- llvm/lib/Target/Mips/MipsBranchExpansion.cpp | 3 +-- .../Target/Mips/MipsConstantIslandPass.cpp | 3 +-- llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 3 +-- llvm/lib/Target/Mips/MipsExpandPseudo.cpp | 3 +-- llvm/lib/Target/Mips/MipsMulMulBugPass.cpp | 3 +-- .../Target/Mips/MipsPostLegalizerCombiner.cpp | 3 +-- .../Target/Mips/MipsPreLegalizerCombiner.cpp | 3 +-- llvm/lib/Target/PowerPC/PPCBranchSelector.cpp | 3 +-- llvm/lib/Target/PowerPC/PPCCTRLoops.cpp | 3 +-- llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp | 3 +-- .../lib/Target/PowerPC/PPCPreEmitPeephole.cpp | 3 +-- .../GISel/RISCVO0PreLegalizerCombiner.cpp | 3 +-- .../GISel/RISCVPostLegalizerCombiner.cpp | 7 ++--- .../RISCV/GISel/RISCVPreLegalizerCombiner.cpp | 3 +-- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- .../Target/RISCV/RISCVLoadStoreOptimizer.cpp | 3 +-- .../lib/Target/RISCV/RISCVMergeBaseOffset.cpp | 3 +-- .../RISCV/RISCVRedundantCopyElimination.cpp | 3 +-- .../lib/Target/RISCV/RISCVVMV0Elimination.cpp | 3 +-- llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 3 +-- llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp | 2 +- .../SPIRV/SPIRVPreLegalizerCombiner.cpp | 3 +-- llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp | 3 +-- llvm/lib/Target/Sparc/DelaySlotFiller.cpp | 3 +-- .../lib/Target/SystemZ/SystemZElimCompare.cpp | 3 +-- .../Target/SystemZ/SystemZISelLowering.cpp | 4 +-- llvm/lib/Target/SystemZ/SystemZLongBranch.cpp | 3 +-- .../lib/Target/SystemZ/SystemZShortenInst.cpp | 3 +-- .../WebAssemblyOptimizeLiveIntervals.cpp | 3 +-- llvm/lib/Target/X86/X86CmovConversion.cpp | 2 +- llvm/lib/Target/X86/X86CompressEVEX.cpp | 3 +-- llvm/lib/Target/X86/X86ExpandPseudo.cpp | 3 +-- llvm/lib/Target/X86/X86FastTileConfig.cpp | 3 +-- llvm/lib/Target/X86/X86FixupBWInsts.cpp | 3 +-- llvm/lib/Target/X86/X86FixupInstTuning.cpp | 3 +-- llvm/lib/Target/X86/X86FixupLEAs.cpp | 3 +-- .../Target/X86/X86FixupVectorConstants.cpp | 3 +-- llvm/lib/Target/X86/X86FloatingPoint.cpp | 3 +-- llvm/lib/Target/X86/X86PadShortFunction.cpp | 3 +-- llvm/lib/Target/X86/X86TileConfig.cpp | 3 +-- llvm/lib/Target/X86/X86VZeroUpper.cpp | 3 +-- .../XCore/XCoreFrameToArgsOffsetElim.cpp | 3 +-- llvm/tools/llvm-exegesis/lib/Assembler.cpp | 6 ++--- .../llvm-exegesis/lib/SnippetRepetitor.cpp | 3 +-- llvm/unittests/MI/LiveIntervalTest.cpp | 2 +- llvm/unittests/MIR/MachineMetadata.cpp | 6 ++--- .../Target/RISCV/RISCVInstrInfoTest.cpp | 2 +- 114 files changed, 141 insertions(+), 267 deletions(-) diff --git a/llvm/include/llvm/CodeGen/PeepholeOptimizer.h b/llvm/include/llvm/CodeGen/PeepholeOptimizer.h index f3968ebb59bc..7f57e6dc3577 100644 --- a/llvm/include/llvm/CodeGen/PeepholeOptimizer.h +++ b/llvm/include/llvm/CodeGen/PeepholeOptimizer.h @@ -19,8 +19,7 @@ public: MachineFunctionAnalysisManager &MFAM); MachineFunctionProperties getRequiredProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index aa2ca77d1798..49b49e288baa 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -448,7 +448,7 @@ public: // Intentionally create a virtual register and set NoVRegs property. auto &MRI = MF.getRegInfo(); MRI.createGenericVirtualRegister(LLT::scalar(8)); - MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); + MF.getProperties().setNoVRegs(); return PreservedAnalyses::all(); } @@ -466,19 +466,18 @@ public: } static MachineFunctionProperties getRequiredProperties() { - MachineFunctionProperties MFProps; - MFProps.set(MachineFunctionProperties::Property::FailedISel); - MFProps.set(MachineFunctionProperties::Property::FailsVerification); - MFProps.set(MachineFunctionProperties::Property::IsSSA); - MFProps.set(MachineFunctionProperties::Property::Legalized); - MFProps.set(MachineFunctionProperties::Property::NoPHIs); - MFProps.set(MachineFunctionProperties::Property::NoVRegs); - MFProps.set(MachineFunctionProperties::Property::RegBankSelected); - MFProps.set(MachineFunctionProperties::Property::Selected); - MFProps.set(MachineFunctionProperties::Property::TiedOpsRewritten); - MFProps.set(MachineFunctionProperties::Property::TracksDebugUserValues); - MFProps.set(MachineFunctionProperties::Property::TracksLiveness); - return MFProps; + return MachineFunctionProperties() + .setFailedISel() + .setFailsVerification() + .setIsSSA() + .setLegalized() + .setNoPHIs() + .setNoVRegs() + .setRegBankSelected() + .setSelected() + .setTiedOpsRewritten() + .setTracksDebugUserValues() + .setTracksLiveness(); } static StringRef name() { return "RequireAllMachineFunctionPropertiesPass"; } }; diff --git a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp index 2760355ae610..a51f63073403 100644 --- a/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp +++ b/llvm/lib/Target/AArch64/AArch64A53Fix835769.cpp @@ -86,8 +86,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp index 87bc925c6dc1..b816f11508be 100644 --- a/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ b/llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -117,8 +117,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp index c3370cd6e946..64f21c4cb229 100644 --- a/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp +++ b/llvm/lib/Target/AArch64/AArch64CollectLOH.cpp @@ -132,8 +132,7 @@ struct AArch64CollectLOH : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return AARCH64_COLLECT_LOH_NAME; } diff --git a/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp b/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp index 6621a1f2fc76..37ad308e4287 100644 --- a/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp +++ b/llvm/lib/Target/AArch64/AArch64CompressJumpTables.cpp @@ -52,8 +52,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "AArch64 Compress Jump Tables"; diff --git a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp index 9a88240de181..83804b4b09bc 100644 --- a/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp +++ b/llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp @@ -188,8 +188,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 22ecf99b12de..61055a66e885 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -1121,7 +1121,7 @@ let RecomputePerFunction = 1 in { // SelectionDAG's behaviour. // FIXME: One day there will probably be a nicer way to check for this, but // today is not that day. - def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasProperty(MachineFunctionProperties::Property::FailedISel) || !MF->getProperties().hasProperty(MachineFunctionProperties::Property::Legalized)">; + def OptimizedGISelOrOtherSelector : Predicate<"!MF->getFunction().hasOptNone() || MF->getProperties().hasFailedISel() || !MF->getProperties().hasLegalized()">; } include "AArch64InstrFormats.td" diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp index dc866486fb95..b7da07a95c7b 100644 --- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -233,8 +233,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; } diff --git a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp index 7cdcd5416cfc..66f14b67a31f 100644 --- a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp +++ b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp @@ -173,9 +173,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M, MachineFunction &MF = MMI->getOrCreateMachineFunction(*F); // Remove unnecessary register liveness and set NoVRegs. - MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness); - MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); - MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); + MF.getProperties().resetTracksLiveness().resetIsSSA().setNoVRegs(); MF.getRegInfo().freezeReservedRegs(); // Create entry block. diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index 9c1ab06e1c1c..84015e506176 100644 --- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -92,8 +92,7 @@ public: bool optimizeBlock(MachineBasicBlock *MBB); bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "AArch64 Redundant Copy Elimination"; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 1dc7318f5899..8caa49de0af4 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -544,8 +544,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { // the pipeline since it prevents other infrastructure from reasoning about // it's liveness. We use the NoVRegs property instead of IsSSA because // IsSSA is removed before VirtRegRewriter runs. - if (!MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs)) + if (!MF.getProperties().hasNoVRegs()) markSuperRegs(Reserved, AArch64::LR); } diff --git a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp index cca0adc84f6f..b5047a88fbaf 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp @@ -147,8 +147,7 @@ AArch64O0PreLegalizerCombiner::AArch64O0PreLegalizerCombiner() } bool AArch64O0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto &TPC = getAnalysis(); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp index 1c3d2b416630..fa7bb6ecc35e 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp @@ -654,12 +654,9 @@ AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone) } bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; - assert(MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Legalized) && - "Expected a legalized function?"); + assert(MF.getProperties().hasLegalized() && "Expected a legalized function?"); auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); bool EnableOpt = diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp index 81ee525ed050..1f547de8c052 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp @@ -1257,12 +1257,9 @@ AArch64PostLegalizerLowering::AArch64PostLegalizerLowering() } bool AArch64PostLegalizerLowering::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; - assert(MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Legalized) && - "Expected a legalized function?"); + assert(MF.getProperties().hasLegalized() && "Expected a legalized function?"); auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp index 913a8870565d..4bd025da636c 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp @@ -292,12 +292,9 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) { } bool AArch64PostSelectOptimize::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; - assert(MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected) && - "Expected a selected MF"); + assert(MF.getProperties().hasSelected() && "Expected a selected MF"); bool Changed = false; for (auto &BB : MF) { diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp index 37a7d2206b18..1cd94531c362 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp @@ -836,8 +836,7 @@ AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner() } bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto &TPC = getAnalysis(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp index 0c6122cce78e..e86b4738bed1 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -478,8 +478,7 @@ AMDGPUPostLegalizerCombiner::AMDGPUPostLegalizerCombiner(bool IsOptNone) } bool AMDGPUPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp index 4aec2ba35ae5..6e54737065d2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp @@ -253,8 +253,7 @@ AMDGPUPreLegalizerCombiner::AMDGPUPreLegalizerCombiner(bool IsOptNone) } bool AMDGPUPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp index f08502fb3d92..ee324a5e93f0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -462,8 +462,7 @@ AMDGPURegBankCombiner::AMDGPURegBankCombiner(bool IsOptNone) } bool AMDGPURegBankCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp index ad6a0772fe8b..4d8d3022b808 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp @@ -58,8 +58,7 @@ public: // If there were no phis and we do waterfall expansion machine verifier would // fail. MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } }; @@ -250,8 +249,7 @@ public: } bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; // Setup the instruction builder with CSE. diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp index fe73aac0763e..493b7541cdd8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankSelect.cpp @@ -53,8 +53,7 @@ public: // This pass assigns register banks to all virtual registers, and we maintain // this property in subsequent passes MachineFunctionProperties getSetProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::RegBankSelected); + return MachineFunctionProperties().setRegBankSelected(); } }; @@ -199,8 +198,7 @@ static Register getVReg(MachineOperand &Op) { } bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; // Setup the instruction builder with CSE. diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp index 0d8113da275b..f9a907a64437 100644 --- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp +++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp @@ -98,8 +98,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties() - .set(MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.h b/llvm/lib/Target/AMDGPU/GCNDPPCombine.h index ac45e578157e..cc8979b858b9 100644 --- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.h +++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.h @@ -18,8 +18,7 @@ public: MachineFunctionAnalysisManager &MAM); MachineFunctionProperties getRequiredProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp b/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp index b3dd68b6a143..d9902e121f9c 100644 --- a/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp +++ b/llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp @@ -121,8 +121,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override { // FIXME: This pass causes verification failures. - MF.getProperties().set( - MachineFunctionProperties::Property::FailsVerification); + MF.getProperties().setFailsVerification(); TII = MF.getSubtarget().getInstrInfo(); TRI = &TII->getRegisterInfo(); diff --git a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp index 17f724c3173d..824bbcfb48cf 100644 --- a/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp +++ b/llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp @@ -111,8 +111,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties() - .set(MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 6f89a3a207f9..2cf00b4e5cc6 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -618,8 +618,7 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, bool SIFixSGPRCopies::run(MachineFunction &MF) { // Only need to run this in SelectionDAG path. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected)) + if (MF.getProperties().hasSelected()) return false; const GCNSubtarget &ST = MF.getSubtarget(); diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index d81f25c57af6..8b12eeba1561 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -191,8 +191,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.h b/llvm/lib/Target/AMDGPU/SIFoldOperands.h index c419ec0911e2..2477707538c8 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.h +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.h @@ -19,8 +19,7 @@ public: MachineFunctionAnalysisManager &MFAM); MachineFunctionProperties getRequiredProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp index 752474783346..fb5ef5824e76 100644 --- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp +++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp @@ -78,8 +78,7 @@ public: } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp index 39359d24cff0..b0d6fd95cd27 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp @@ -323,8 +323,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties() - .set(MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h index 33188c6ebb67..317dd8c208b1 100644 --- a/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h +++ b/llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.h @@ -20,8 +20,7 @@ public: MachineFunctionAnalysisManager &MFAM); MachineFunctionProperties getRequiredProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp index 6a1fff7aeb3a..96131bd591a1 100644 --- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp @@ -859,8 +859,7 @@ void Vreg1LoweringHelper::constrainAsLaneMask(Incoming &In) {} static bool runFixI1Copies(MachineFunction &MF, MachineDominatorTree &MDT, MachinePostDominatorTree &MPDT) { // Only need to run this in SelectionDAG path. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Selected)) + if (MF.getProperties().hasSelected()) return false; Vreg1LoweringHelper Helper(&MF, &MDT, &MPDT); diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index f707b8b77bb7..9f61bf8eaa3a 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -81,9 +81,7 @@ public: MachineFunctionProperties getClearedProperties() const override { // SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs. - return MachineFunctionProperties() - .set(MachineFunctionProperties::Property::IsSSA) - .set(MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setIsSSA().setNoVRegs(); } }; diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h index a9ffb5705d09..64ba3029f1c5 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h @@ -19,9 +19,7 @@ public: MachineFunctionProperties getClearedProperties() const { // SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs. - return MachineFunctionProperties() - .set(MachineFunctionProperties::Property::IsSSA) - .set(MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setIsSSA().setNoVRegs(); } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp index ff0b9b4a7574..0e2ac495d2d9 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp @@ -166,13 +166,11 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } }; diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h index 1139a9c18581..c771df379cb3 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h +++ b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.h @@ -19,13 +19,11 @@ public: MachineFunctionAnalysisManager &MFAM); MachineFunctionProperties getRequiredProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } MachineFunctionProperties getClearedProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } }; } // namespace llvm diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 8b8583d9a1c9..412f0432e85c 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -417,8 +417,7 @@ void SIShrinkInstructions::shrinkMadFma(MachineInstr &MI) const { return; // There is no advantage to doing this pre-RA. - if (!MF->getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs)) + if (!MF->getProperties().hasNoVRegs()) return; if (TII->hasAnyModifiersSet(MI)) @@ -951,8 +950,7 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { if (TII->isMIMG(MI.getOpcode()) && ST->getGeneration() >= AMDGPUSubtarget::GFX10 && - MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs)) { + MF.getProperties().hasNoVRegs()) { shrinkMIMG(MI); continue; } @@ -1063,9 +1061,7 @@ bool SIShrinkInstructions::run(MachineFunction &MF) { // fold an immediate into the shrunk instruction as a literal operand. In // GFX10 VOP3 instructions can take a literal operand anyway, so there is // no advantage to doing this. - if (ST->hasVOP3Literal() && - !MF.getProperties().hasProperty( - MachineFunctionProperties::Property::NoVRegs)) + if (ST->hasVOP3Literal() && !MF.getProperties().hasNoVRegs()) continue; if (ST->hasTrue16BitInsts() && AMDGPU::isTrue16Inst(MI.getOpcode()) && diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 57ae7d63218d..1198bbc310da 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -256,8 +256,7 @@ public: } MachineFunctionProperties getClearedProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; } // end anonymous namespace diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h index e30b46721841..87350b810bba 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h @@ -18,8 +18,7 @@ public: MachineFunctionAnalysisManager &MFAM); MachineFunctionProperties getClearedProperties() const { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; } // namespace llvm diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index 2972316fcee0..56511ce20a16 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -234,8 +234,7 @@ namespace { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 59b4923c0c5b..52302241fe36 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -51,8 +51,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp index 7d18242d8c16..6611ae8ee6ba 100644 --- a/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp +++ b/llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp @@ -75,8 +75,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index afbf1b4c55e7..1f7ab8ce3a0e 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -12157,7 +12157,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, OpDestReg, OpSizeReg, TotalIterationsReg, IsMemcpy); // Required to avoid conflict with the MachineVerifier during testing. - Properties.reset(MachineFunctionProperties::Property::NoPHIs); + Properties.resetNoPHIs(); // Connect the blocks TpEntry->addSuccessor(TpLoopBody); diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index f8790dd063ae..eea0cb61af2b 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -119,8 +119,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; } diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index e7c53b748714..06f362b26744 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -489,9 +489,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs).set( - MachineFunctionProperties::Property::TracksLiveness); + return MachineFunctionProperties().setNoVRegs().setTracksLiveness(); } StringRef getPassName() const override { @@ -1293,7 +1291,7 @@ bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &mf) { MLI = &getAnalysis().getLI(); RDA = &getAnalysis(); - MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness); + MF->getProperties().setTracksLiveness(); MRI = &MF->getRegInfo(); TII = static_cast(ST.getInstrInfo()); TRI = ST.getRegisterInfo(); diff --git a/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp b/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp index ccaedf79b3c6..b2708ec1437d 100644 --- a/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp +++ b/llvm/lib/Target/ARM/ARMOptimizeBarriersPass.cpp @@ -26,8 +26,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "optimise barriers pass"; } diff --git a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp index 09810152ef89..d896d10a7758 100644 --- a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp +++ b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp @@ -41,8 +41,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp index b04e20a0b670..806dbb132dba 100644 --- a/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp +++ b/llvm/lib/Target/ARM/Thumb1FrameLowering.cpp @@ -467,7 +467,7 @@ void Thumb1FrameLowering::emitPrologue(MachineFunction &MF, // In some cases, virtual registers have been introduced, e.g. by uses of // emitThumbRegPlusImmInReg. - MF.getProperties().reset(MachineFunctionProperties::Property::NoVRegs); + MF.getProperties().resetNoVRegs(); } void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index 0c519d99785d..4980910a4952 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -52,8 +52,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index c527bf5ce8b0..18e41297b173 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -167,8 +167,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp index e21f4ea45b59..e55d9b227d1c 100644 --- a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp +++ b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp @@ -218,8 +218,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void doInitialPlacement(std::vector &CPEMIs); diff --git a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp index 1aa669033236..75f2e1b5605d 100644 --- a/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -40,8 +40,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index ab03433160d3..c86fa2b2b198 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -75,8 +75,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index d55bc833c2e2..882a44a07b34 100644 --- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -38,8 +38,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index bad451eff1d8..b75c8863b699 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -207,8 +207,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index e942cf0537db..74e5abe2599c 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -73,8 +73,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp index b0b60fa6ef8c..5a1d5bc66916 100644 --- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -80,8 +80,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp index 52e839420c27..54f5608d460a 100644 --- a/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ b/llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -70,8 +70,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } static char ID; diff --git a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp index b0327df57883..9e3b0133c052 100644 --- a/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -40,8 +40,7 @@ namespace { } bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; } diff --git a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 753b584f766d..bc486cd562bf 100644 --- a/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -101,8 +101,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: @@ -198,8 +197,7 @@ static MachineBasicBlock::iterator moveInstrOut(MachineInstr &MI, bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) { // FIXME: This pass causes verification failures. - MF.getProperties().set( - MachineFunctionProperties::Property::FailsVerification); + MF.getProperties().setFailsVerification(); auto &HST = MF.getSubtarget(); HII = HST.getInstrInfo(); diff --git a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp index a10124c2d5c1..c1aa1221ea13 100644 --- a/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ b/llvm/lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -57,8 +57,7 @@ struct Filler : public MachineFunctionPass { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void insertDefsUses(MachineBasicBlock::instr_iterator MI, diff --git a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp index 9fd1ff60587c..086c7f7d5e5c 100644 --- a/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ b/llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -61,8 +61,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp index 50ec0b2e3ca7..9f5c94ddea44 100644 --- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp @@ -5729,7 +5729,7 @@ emitSelectPseudo(MachineInstr &MI, MachineBasicBlock *BB, SelectMBBI = Next; } - F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + F->getProperties().resetNoPHIs(); return TailMBB; } diff --git a/llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp b/llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp index 2aae498e1f2d..f62753356a4d 100644 --- a/llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp +++ b/llvm/lib/Target/LoongArch/LoongArchMergeBaseOffset.cpp @@ -58,8 +58,7 @@ public: LoongArchMergeBaseOffsetOpt() : MachineFunctionPass(ID) {} MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp index 1ba265a60c3d..83659c2ef99d 100644 --- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp +++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp @@ -53,8 +53,7 @@ public: bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp index ce5affdc25b0..75cceaf72b89 100644 --- a/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp +++ b/llvm/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -53,8 +53,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "MSP430 Branch Selector"; } diff --git a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp index 8089972642bd..6e897fe87668 100644 --- a/llvm/lib/Target/Mips/MipsBranchExpansion.cpp +++ b/llvm/lib/Target/Mips/MipsBranchExpansion.cpp @@ -145,8 +145,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 760be36b7667..8067dbc54170 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -364,8 +364,7 @@ namespace { bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void doInitialPlacement(std::vector &CPEMIs); diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index 9d07512b7d8a..e45fee52a2d3 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -228,8 +228,7 @@ namespace { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp index 199474fbd82d..34ff41f6e02d 100644 --- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp @@ -41,8 +41,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/Mips/MipsMulMulBugPass.cpp b/llvm/lib/Target/Mips/MipsMulMulBugPass.cpp index 5251c86d105b..8ca6d07def59 100644 --- a/llvm/lib/Target/Mips/MipsMulMulBugPass.cpp +++ b/llvm/lib/Target/Mips/MipsMulMulBugPass.cpp @@ -40,8 +40,7 @@ public: StringRef getPassName() const override { return "Mips VR4300 mulmul bugfix"; } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp index 166a2501e3f0..d28129663e72 100644 --- a/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/Mips/MipsPostLegalizerCombiner.cpp @@ -122,8 +122,7 @@ MipsPostLegalizerCombiner::MipsPostLegalizerCombiner(bool IsOptNone) } bool MipsPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); diff --git a/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp b/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp index 278dcb143d33..e7686bff1b34 100644 --- a/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp @@ -113,8 +113,7 @@ MipsPreLegalizerCombiner::MipsPreLegalizerCombiner() : MachineFunctionPass(ID) {} bool MipsPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto *TPC = &getAnalysis(); diff --git a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp index cc844f341779..5cb64e3c03ae 100644 --- a/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/llvm/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -58,8 +58,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "PowerPC Branch Selector"; } diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp index 1033f0ce68f8..7a5f91113d99 100644 --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -253,8 +253,7 @@ void PPCCTRLoops::expandNormalLoops(MachineLoop *ML, MachineInstr *Start, MRI->createVirtualRegister(Is64Bit ? &PPC::G8RC_and_G8RC_NOX0RegClass : &PPC::GPRC_and_GPRC_NOR0RegClass); - Start->getParent()->getParent()->getProperties().reset( - MachineFunctionProperties::Property::NoPHIs); + Start->getParent()->getParent()->getProperties().resetNoPHIs(); // Generate "PHI" in the header block. auto PHIMIB = BuildMI(*ML->getHeader(), ML->getHeader()->getFirstNonPHI(), diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp index 8339c00aa975..bb4178ba95da 100644 --- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp +++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -181,8 +181,7 @@ public: } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp index 0d408a7c6bd6..e5f3ed8fc319 100644 --- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp @@ -102,8 +102,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } // This function removes any redundant load immediates. It has two level diff --git a/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp index d57479c80297..895c3dbcb2c1 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVO0PreLegalizerCombiner.cpp @@ -115,8 +115,7 @@ RISCVO0PreLegalizerCombiner::RISCVO0PreLegalizerCombiner() } bool RISCVO0PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto &TPC = getAnalysis(); diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp index 1e4c598d3adf..67b510dc80f1 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVPostLegalizerCombiner.cpp @@ -123,12 +123,9 @@ RISCVPostLegalizerCombiner::RISCVPostLegalizerCombiner() } bool RISCVPostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; - assert(MF.getProperties().hasProperty( - MachineFunctionProperties::Property::Legalized) && - "Expected a legalized function?"); + assert(MF.getProperties().hasLegalized() && "Expected a legalized function?"); auto *TPC = &getAnalysis(); const Function &F = MF.getFunction(); bool EnableOpt = diff --git a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp index e6e8147f3118..d955205d066d 100644 --- a/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/RISCV/GISel/RISCVPreLegalizerCombiner.cpp @@ -121,8 +121,7 @@ RISCVPreLegalizerCombiner::RISCVPreLegalizerCombiner() } bool RISCVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto &TPC = getAnalysis(); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 7320f0afdc0a..bce468546a9f 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21180,7 +21180,7 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI, SelectMBBI = Next; } - F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + F->getProperties().resetNoPHIs(); return TailMBB; } diff --git a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp index 9097fb538799..c81a20ba8c88 100644 --- a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp @@ -48,8 +48,7 @@ struct RISCVLoadStoreOpt : public MachineFunctionPass { RISCVLoadStoreOpt() : MachineFunctionPass(ID) {} MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp index 60ebd0fdff2a..87f0c8f15a90 100644 --- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp +++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp @@ -47,8 +47,7 @@ public: RISCVMergeBaseOffsetOpt() : MachineFunctionPass(ID) {} MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp index 167db9f50bcb..811db793ba0e 100644 --- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp +++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp @@ -48,8 +48,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp b/llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp index 6dbae5bf525d..d72d27c983ad 100644 --- a/llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp +++ b/llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp @@ -58,8 +58,7 @@ public: // TODO: We could move this closer to regalloc, out of SSA, which would // allow scheduling past mask operands. We would need to preserve live // intervals. - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } }; diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index 721b0bf425e9..6bb026378274 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -51,8 +51,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + return MachineFunctionProperties().setIsSSA(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp index a4f95ea11d07..2fdd54fdfc39 100644 --- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp @@ -2052,7 +2052,7 @@ static void patchPhis(const Module &M, SPIRVGlobalRegistry *GR, } } - MF->getProperties().set(MachineFunctionProperties::Property::NoPHIs); + MF->getProperties().setNoPHIs(); } } diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp index d378f2b0d1ff..1e19c0a7c5c9 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizerCombiner.cpp @@ -201,8 +201,7 @@ SPIRVPreLegalizerCombiner::SPIRVPreLegalizerCombiner() } bool SPIRVPreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) { - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::FailedISel)) + if (MF.getProperties().hasFailedISel()) return false; auto &TPC = getAnalysis(); diff --git a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp index f90b7af2b2ad..b51df25e48a7 100644 --- a/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp @@ -274,8 +274,7 @@ namespace { class SPIRVInstructionSelect : public InstructionSelect { // We don't use register banks, so unset the requirement for them MachineFunctionProperties getRequiredProperties() const override { - return InstructionSelect::getRequiredProperties().reset( - MachineFunctionProperties::Property::RegBankSelected); + return InstructionSelect::getRequiredProperties().resetRegBankSelected(); } }; } // namespace diff --git a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp index 7c84c4ac1b46..6c19049a001c 100644 --- a/llvm/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/llvm/lib/Target/Sparc/DelaySlotFiller.cpp @@ -58,8 +58,7 @@ namespace { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void insertCallDefsUses(MachineBasicBlock::iterator MI, diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index 81f0014dd83f..bbe1821e7b8f 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -71,8 +71,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 8eb2c84be9b6..3b86a9bc5879 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -9606,7 +9606,7 @@ static void createPHIsForSelects(SmallVector &Selects, RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); } - MF->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + MF->getProperties().resetNoPHIs(); } MachineBasicBlock * @@ -10560,7 +10560,7 @@ SystemZTargetLowering::emitMemMemWrapper(MachineInstr &MI, MBB->addLiveIn(SystemZ::CC); } } - MF.getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + MF.getProperties().resetNoPHIs(); } // Handle any remaining bytes with straight-line code. diff --git a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp index b327c1be69d1..54e1eb095494 100644 --- a/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp +++ b/llvm/lib/Target/SystemZ/SystemZLongBranch.cpp @@ -140,8 +140,7 @@ public: bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp index 5d71c25348d9..96a41487c87e 100644 --- a/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp +++ b/llvm/lib/Target/SystemZ/SystemZShortenInst.cpp @@ -31,8 +31,7 @@ public: bool processBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp index b59a3d85e302..0c561622e634 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp @@ -50,8 +50,7 @@ class WebAssemblyOptimizeLiveIntervals final : public MachineFunctionPass { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::TracksLiveness); + return MachineFunctionProperties().setTracksLiveness(); } bool runOnMachineFunction(MachineFunction &MF) override; diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp index e389ce9a296b..e25d7551e389 100644 --- a/llvm/lib/Target/X86/X86CmovConversion.cpp +++ b/llvm/lib/Target/X86/X86CmovConversion.cpp @@ -872,7 +872,7 @@ void X86CmovConverterPass::convertCmovInstsToBranches( // Reset the NoPHIs property if a PHI was inserted to prevent a conflict with // the MachineVerifier during testing. if (MIItBegin != MIItEnd) - F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); + F->getProperties().resetNoPHIs(); // Now remove the CMOV(s). MBB->erase(MIItBegin, MIItEnd); diff --git a/llvm/lib/Target/X86/X86CompressEVEX.cpp b/llvm/lib/Target/X86/X86CompressEVEX.cpp index 84f63f312a76..fe593aa307df 100644 --- a/llvm/lib/Target/X86/X86CompressEVEX.cpp +++ b/llvm/lib/Target/X86/X86CompressEVEX.cpp @@ -75,8 +75,7 @@ public: // This pass runs after regalloc and doesn't support VReg operands. MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } }; diff --git a/llvm/lib/Target/X86/X86ExpandPseudo.cpp b/llvm/lib/Target/X86/X86ExpandPseudo.cpp index 8ba6ed357d14..7f06e0f3a38b 100644 --- a/llvm/lib/Target/X86/X86ExpandPseudo.cpp +++ b/llvm/lib/Target/X86/X86ExpandPseudo.cpp @@ -51,8 +51,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/X86/X86FastTileConfig.cpp b/llvm/lib/Target/X86/X86FastTileConfig.cpp index c2305b24d6e5..11d331b11737 100644 --- a/llvm/lib/Target/X86/X86FastTileConfig.cpp +++ b/llvm/lib/Target/X86/X86FastTileConfig.cpp @@ -62,8 +62,7 @@ public: bool runOnMachineFunction(MachineFunction &MFunc) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } static char ID; diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp index fe2c8fff5775..6274cb446219 100644 --- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp +++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp @@ -123,8 +123,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/X86/X86FixupInstTuning.cpp b/llvm/lib/Target/X86/X86FixupInstTuning.cpp index 8c10a0780468..6bb7600dedca 100644 --- a/llvm/lib/Target/X86/X86FixupInstTuning.cpp +++ b/llvm/lib/Target/X86/X86FixupInstTuning.cpp @@ -49,8 +49,7 @@ public: // This pass runs after regalloc and doesn't support VReg operands. MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp index 146591ae135f..385a6fb6602e 100644 --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -134,8 +134,7 @@ public: // This pass runs after regalloc and doesn't support VReg operands. MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } void getAnalysisUsage(AnalysisUsage &AU) const override { diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp index a415a4577598..11f6a6d4de2d 100644 --- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp +++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp @@ -45,8 +45,7 @@ public: // This pass runs after regalloc and doesn't support VReg operands. MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } private: diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index e36fd3ee60ba..e0991aaee3d4 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -76,8 +76,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "X86 FP Stackifier"; } diff --git a/llvm/lib/Target/X86/X86PadShortFunction.cpp b/llvm/lib/Target/X86/X86PadShortFunction.cpp index e4cc4fdcb3ab..170ca2a93250 100644 --- a/llvm/lib/Target/X86/X86PadShortFunction.cpp +++ b/llvm/lib/Target/X86/X86PadShortFunction.cpp @@ -60,8 +60,7 @@ namespace { } MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/lib/Target/X86/X86TileConfig.cpp b/llvm/lib/Target/X86/X86TileConfig.cpp index c054b2672785..17a44dde6480 100644 --- a/llvm/lib/Target/X86/X86TileConfig.cpp +++ b/llvm/lib/Target/X86/X86TileConfig.cpp @@ -58,8 +58,7 @@ struct X86TileConfig : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &mf) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoPHIs); + return MachineFunctionProperties().setNoPHIs(); } static char ID; diff --git a/llvm/lib/Target/X86/X86VZeroUpper.cpp b/llvm/lib/Target/X86/X86VZeroUpper.cpp index 9d119b945585..f6f7e92d9857 100644 --- a/llvm/lib/Target/X86/X86VZeroUpper.cpp +++ b/llvm/lib/Target/X86/X86VZeroUpper.cpp @@ -55,8 +55,7 @@ namespace { bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { return "X86 vzeroupper inserter"; } diff --git a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp index aa6bf50d9973..e56bf675205e 100644 --- a/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ b/llvm/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -25,8 +25,7 @@ namespace { bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::NoVRegs); + return MachineFunctionProperties().setNoVRegs(); } StringRef getPassName() const override { diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp index 67f3d75a5e87..fd7924db0844 100644 --- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp +++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp @@ -257,9 +257,7 @@ Error assembleToStream(const ExegesisTarget &ET, // We need to instruct the passes that we're done with SSA and virtual // registers. auto &Properties = MF.getProperties(); - Properties.set(MachineFunctionProperties::Property::NoVRegs); - Properties.reset(MachineFunctionProperties::Property::IsSSA); - Properties.set(MachineFunctionProperties::Property::NoPHIs); + Properties.setNoVRegs().resetIsSSA().setNoPHIs(); for (const MCRegister Reg : LiveIns) MF.getRegInfo().addLiveIn(Reg); @@ -300,7 +298,7 @@ Error assembleToStream(const ExegesisTarget &ET, // means that we won't know what values are in the registers. // FIXME: this should probably be an assertion. if (!IsSnippetSetupComplete) - Properties.reset(MachineFunctionProperties::Property::TracksLiveness); + Properties.resetTracksLiveness(); Fill(Sink); diff --git a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp index e4fe27f010c2..80f5ce4a2f1d 100644 --- a/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp +++ b/llvm/tools/llvm-exegesis/lib/SnippetRepetitor.cpp @@ -97,8 +97,7 @@ public: Entry.MBB->addSuccessor(Loop.MBB, BranchProbability::getOne()); Loop.MBB->addSuccessor(Loop.MBB, BranchProbability::getOne()); // If the snippet setup completed, then we can track liveness. - if (Loop.MF.getProperties().hasProperty( - MachineFunctionProperties::Property::TracksLiveness)) { + if (Loop.MF.getProperties().hasTracksLiveness()) { // The live ins are: the loop counter, the registers that were setup by // the entry block, and entry block live ins. Loop.MBB->addLiveIn(LoopCounter); diff --git a/llvm/unittests/MI/LiveIntervalTest.cpp b/llvm/unittests/MI/LiveIntervalTest.cpp index 85a5085ece5f..45b8aeb72b59 100644 --- a/llvm/unittests/MI/LiveIntervalTest.cpp +++ b/llvm/unittests/MI/LiveIntervalTest.cpp @@ -160,7 +160,7 @@ static void testHandleMoveIntoNewBundle(MachineFunction &MF, LiveIntervals &LIS, // Build bundle finalizeBundle(MBB, I, std::next(ToInstr.getIterator())); - MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); + MF.getProperties().resetIsSSA(); // Update LiveIntervals MachineBasicBlock::instr_iterator BundleStart = std::prev(I); diff --git a/llvm/unittests/MIR/MachineMetadata.cpp b/llvm/unittests/MIR/MachineMetadata.cpp index 25025bdeec71..0f038d9dc223 100644 --- a/llvm/unittests/MIR/MachineMetadata.cpp +++ b/llvm/unittests/MIR/MachineMetadata.cpp @@ -564,8 +564,7 @@ body: | ASSERT_TRUE(M); auto *MF = MMI.getMachineFunction(*M->getFunction("foo")); MachineFunctionProperties &Properties = MF->getProperties(); - ASSERT_TRUE(Properties.hasProperty( - MachineFunctionProperties::Property::TiedOpsRewritten)); + ASSERT_TRUE(Properties.hasTiedOpsRewritten()); } TEST_F(MachineMetadataTest, NoTiedOpsRewritten) { @@ -595,6 +594,5 @@ body: | ASSERT_TRUE(M); auto *MF = MMI.getMachineFunction(*M->getFunction("foo")); MachineFunctionProperties &Properties = MF->getProperties(); - ASSERT_FALSE(Properties.hasProperty( - MachineFunctionProperties::Property::TiedOpsRewritten)); + ASSERT_FALSE(Properties.hasTiedOpsRewritten()); } diff --git a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp index 4881f193f34b..0e6c1172ee9b 100644 --- a/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp +++ b/llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp @@ -294,7 +294,7 @@ TEST_P(RISCVInstrInfoTest, DescribeLoadedValue) { DebugLoc DL; MachineBasicBlock *MBB = MF->CreateMachineBasicBlock(); - MF->getProperties().set(MachineFunctionProperties::Property::NoVRegs); + MF->getProperties().setNoVRegs(); // Register move. auto *MI1 = BuildMI(*MBB, MBB->begin(), DL, TII->get(RISCV::ADDI), RISCV::X1)