[lldb] [ABI/AArch64] Add pseudo-regs if missing
Create pseudo-registers on the AArch64 target if they are not provided by the remote server. This is the case for gdbserver. The created registers are: - 32-bit wN partials for 64-bit xN registers - double precision floating-point dN registers (overlapping with vN) - single precision floating-point sN registers (overlapping with vN) Differential Revision: https://reviews.llvm.org/D109876
This commit is contained in:
Michał Górny
parent
1afda54f19
commit
583f67cb4e
@ -13,6 +13,8 @@
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Target/Process.h"
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#include <bitset>
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LLDB_PLUGIN_DEFINE(ABIAArch64)
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void ABIAArch64::Initialize() {
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@ -71,14 +73,81 @@ uint32_t ABIAArch64::GetGenericNum(llvm::StringRef name) {
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.Default(LLDB_INVALID_REGNUM);
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}
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static void addPartialRegisters(
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std::vector<lldb_private::DynamicRegisterInfo::Register> ®s,
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llvm::ArrayRef<llvm::Optional<uint32_t>> full_reg_indices,
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uint32_t full_reg_size, const char *partial_reg_format,
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uint32_t partial_reg_size, lldb::Encoding encoding, lldb::Format format) {
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for (auto it : llvm::enumerate(full_reg_indices)) {
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llvm::Optional<uint32_t> full_reg_index = it.value();
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if (!full_reg_index ||
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regs[full_reg_index.getValue()].byte_size != full_reg_size)
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return;
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lldb_private::DynamicRegisterInfo::Register partial_reg{
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lldb_private::ConstString(
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llvm::formatv(partial_reg_format, it.index()).str()),
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lldb_private::ConstString(),
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lldb_private::ConstString("supplementary registers"),
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partial_reg_size,
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LLDB_INVALID_INDEX32,
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encoding,
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format,
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LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM,
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{full_reg_index.getValue()},
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{}};
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addSupplementaryRegister(regs, partial_reg);
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}
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}
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void ABIAArch64::AugmentRegisterInfo(
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std::vector<lldb_private::DynamicRegisterInfo::Register> ®s) {
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lldb_private::MCBasedABI::AugmentRegisterInfo(regs);
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lldb_private::ConstString sp_string{"sp"};
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for (lldb_private::DynamicRegisterInfo::Register &info : regs) {
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std::array<llvm::Optional<uint32_t>, 32> x_regs;
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std::array<llvm::Optional<uint32_t>, 32> v_regs;
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std::bitset<32> have_w_regs;
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std::bitset<32> have_s_regs;
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std::bitset<32> have_d_regs;
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for (auto it : llvm::enumerate(regs)) {
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lldb_private::DynamicRegisterInfo::Register &info = it.value();
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// GDB sends x31 as "sp". Add the "x31" alt_name for convenience.
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if (info.name == sp_string && !info.alt_name)
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info.alt_name.SetCString("x31");
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unsigned int reg_num;
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auto get_reg = [&info, ®_num](const char *prefix) {
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llvm::StringRef reg_name = info.name.GetStringRef();
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llvm::StringRef alt_name = info.alt_name.GetStringRef();
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return (reg_name.consume_front(prefix) &&
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llvm::to_integer(reg_name, reg_num, 10) && reg_num < 32) ||
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(alt_name.consume_front(prefix) &&
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llvm::to_integer(alt_name, reg_num, 10) && reg_num < 32);
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};
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if (get_reg("x"))
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x_regs[reg_num] = it.index();
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if (get_reg("v"))
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v_regs[reg_num] = it.index();
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if (get_reg("w"))
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have_w_regs[reg_num] = true;
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if (get_reg("s"))
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have_s_regs[reg_num] = true;
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if (get_reg("d"))
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have_d_regs[reg_num] = true;
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}
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// Create aliases for partial registers: wN for xN, and sN/dN for vN.
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addPartialRegisters(regs, x_regs, 8, "w{0}", 4, lldb::eEncodingUint,
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lldb::eFormatHex);
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addPartialRegisters(regs, v_regs, 16, "s{0}", 4, lldb::eEncodingIEEE754,
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lldb::eFormatFloat);
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addPartialRegisters(regs, v_regs, 16, "d{0}", 8, lldb::eEncodingIEEE754,
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lldb::eFormatFloat);
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}
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@ -270,27 +270,27 @@ class TestGDBServerTargetXML(GDBRemoteTestBase):
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@skipIfLLVMTargetMissing("AArch64")
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def test_aarch64_regs(self):
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"""Test grabbing various aarch64 registers from gdbserver."""
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reg_data = [
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"0102030405060708", # x0
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"1112131415161718", # x1
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] + 27 * [
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"2122232425262728", # x2..x28
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] + [
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"3132333435363738", # x29 (fp)
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"4142434445464748", # x30 (lr)
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"5152535455565758", # x31 (sp)
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"6162636465666768", # pc
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"71727374", # cpsr
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"8182838485868788898a8b8c8d8e8f90", # v0
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"9192939495969798999a9b9c9d9e9fa0", # v1
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] + 30 * [
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"a1a2a3a4a5a6a7a8a9aaabacadaeafb0", # v2..v31
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] + [
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"00000000", # fpsr
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"00000000", # fpcr
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]
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class MyResponder(MockGDBServerResponder):
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reg_data = (
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"0102030405060708" # x0
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"1112131415161718" # x1
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) + 27 * (
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"2122232425262728" # x2..x28
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) + (
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"3132333435363738" # x29 (fp)
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"4142434445464748" # x30 (lr)
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"5152535455565758" # x31 (sp)
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"6162636465666768" # pc
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"71727374" # cpsr
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"8182838485868788898a8b8c8d8e8f90" # v0
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"9192939495969798999a9b9c9d9e9fa0" # v1
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) + 30 * (
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"a1a2a3a4a5a6a7a8a9aaabacadaeafb0" # v2..v31
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) + (
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"00000000" # fpsr
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"00000000" # fpcr
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)
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def qXferRead(self, obj, annex, offset, length):
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if annex == "target.xml":
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return """<?xml version="1.0"?>
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@ -377,9 +377,10 @@ class TestGDBServerTargetXML(GDBRemoteTestBase):
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return ""
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def readRegisters(self):
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return "".join(reg_data)
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return self.reg_data
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def writeRegisters(self, reg_hex):
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self.reg_data = reg_hex
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return "OK"
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def haltReason(self):
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@ -429,3 +430,43 @@ class TestGDBServerTargetXML(GDBRemoteTestBase):
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["v0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"])
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self.match("register read v31",
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["v31 = {0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0}"])
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# test partial registers
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self.match("register read w0",
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["w0 = 0x04030201"])
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self.runCmd("register write w0 0xfffefdfc")
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self.match("register read x0",
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["x0 = 0x08070605fffefdfc"])
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self.match("register read w1",
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["w1 = 0x14131211"])
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self.runCmd("register write w1 0xefeeedec")
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self.match("register read x1",
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["x1 = 0x18171615efeeedec"])
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self.match("register read w30",
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["w30 = 0x44434241"])
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self.runCmd("register write w30 0xdfdedddc")
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self.match("register read x30",
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["x30 = 0x48474645dfdedddc"])
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self.match("register read w31",
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["w31 = 0x54535251"])
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self.runCmd("register write w31 0xcfcecdcc")
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self.match("register read x31",
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["sp = 0x58575655cfcecdcc"])
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# test FPU registers (overlapping with vector registers)
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self.runCmd("register write d0 16")
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self.match("register read v0",
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["v0 = {0x00 0x00 0x00 0x00 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"])
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self.runCmd("register write v31 '{0x00 0x00 0x00 0x00 0x00 0x00 0x50 0x40 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'")
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self.match("register read d31",
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["d31 = 64"])
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self.runCmd("register write s0 32")
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self.match("register read v0",
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["v0 = {0x00 0x00 0x00 0x42 0x00 0x00 0x30 0x40 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"])
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self.runCmd("register write v31 '{0x00 0x00 0x00 0x43 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff}'")
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self.match("register read s31",
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["s31 = 128"])
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