From 595d5f36f4f9cebccca9efaf0db4bc20cc44ea2f Mon Sep 17 00:00:00 2001 From: WANG Rui Date: Mon, 24 Jul 2023 13:24:07 +0800 Subject: [PATCH] [DAGCombine] Canonicalize operands for visitANDLike During the construction of SelectionDAG, there are no explicit canonicalization rules to adjust the order of operands for AND nodes. This may prevent the optimization in DAGCombiner::visitANDLike from being triggered. This patch canonicalizes the operands before matches, which can be observed to improve optimization on the RISC-V target architecture. Canonicalize: ``` and(x, add) -> and(add, x) ``` Signed-off-by: WANG Rui Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D154760 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 5 +++++ llvm/test/CodeGen/RISCV/and-add-lsr.ll | 8 ++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 63b7506e4b39..0cbf7bd9bd47 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -6195,6 +6195,11 @@ SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) { if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL)) return V; + // Canonicalize: + // and(x, add) -> and(add, x) + if (N1.getOpcode() == ISD::ADD) + std::swap(N0, N1); + // TODO: Rewrite this to return a new 'AND' instead of using CombineTo. if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && VT.getSizeInBits() <= 64 && N0->hasOneUse()) { diff --git a/llvm/test/CodeGen/RISCV/and-add-lsr.ll b/llvm/test/CodeGen/RISCV/and-add-lsr.ll index e25072775e5a..c2c7a4999b2f 100644 --- a/llvm/test/CodeGen/RISCV/and-add-lsr.ll +++ b/llvm/test/CodeGen/RISCV/and-add-lsr.ll @@ -7,18 +7,14 @@ define i32 @and_add_lsr(i32 %x, i32 %y) { ; RV32I-LABEL: and_add_lsr: ; RV32I: # %bb.0: -; RV32I-NEXT: lui a2, 1 -; RV32I-NEXT: addi a2, a2, -1 -; RV32I-NEXT: add a0, a0, a2 +; RV32I-NEXT: addi a0, a0, -1 ; RV32I-NEXT: srli a1, a1, 20 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: ret ; ; RV64I-LABEL: and_add_lsr: ; RV64I: # %bb.0: -; RV64I-NEXT: lui a2, 1 -; RV64I-NEXT: addiw a2, a2, -1 -; RV64I-NEXT: addw a0, a0, a2 +; RV64I-NEXT: addiw a0, a0, -1 ; RV64I-NEXT: srliw a1, a1, 20 ; RV64I-NEXT: and a0, a1, a0 ; RV64I-NEXT: ret