From 59762a0ecf64cbf6ac20c41ae75666cd87519f26 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames@rivosinc.com>
Date: Thu, 29 Aug 2024 12:08:33 -0700
Subject: [PATCH] [RISCV] Add coverage for <3 x float> reduction with neutral
 start

We can do slightly better on the neutral value when we have nsz.
---
 .../RISCV/rvv/fixed-vectors-reduction-fp.ll   | 237 +++++++++++-------
 1 file changed, 141 insertions(+), 96 deletions(-)

diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
index 566c9070eab5..5d5807cbadba 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
@@ -489,6 +489,51 @@ define float @vreduce_ord_fadd_v7f32(ptr %x, float %s) {
   ret float %red
 }
 
+define float @vreduce_fadd_v7f32_neutralstart(ptr %x) {
+; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vfredusum.vs v8, v8, v10
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %v = load <7 x float>, ptr %x
+  %red = call reassoc float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)
+  ret float %red
+}
+
+define float @vreduce_fadd_v7f32_neutralstart_nsz(ptr %x) {
+; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart_nsz:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vfredosum.vs v8, v8, v10
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %v = load <7 x float>, ptr %x
+  %red = call nsz float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)
+  ret float %red
+}
+
+define float @vreduce_fadd_v7f32_neutralstart_fast(ptr %x) {
+; CHECK-LABEL: vreduce_fadd_v7f32_neutralstart_fast:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 7, e32, m2, ta, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    lui a0, 524288
+; CHECK-NEXT:    vmv.s.x v10, a0
+; CHECK-NEXT:    vfredusum.vs v8, v8, v10
+; CHECK-NEXT:    vfmv.f.s fa0, v8
+; CHECK-NEXT:    ret
+  %v = load <7 x float>, ptr %x
+  %red = call fast float @llvm.vector.reduce.fadd.v7f32(float -0.0, <7 x float> %v)
+  ret float %red
+}
+
 
 declare float @llvm.vector.reduce.fadd.v8f32(float, <8 x float>)
 
@@ -1683,12 +1728,12 @@ define float @vreduce_fminimum_v2f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v9, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v9
-; CHECK-NEXT:    beqz a0, .LBB104_2
+; CHECK-NEXT:    beqz a0, .LBB107_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB104_2:
+; CHECK-NEXT:  .LBB107_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -1719,12 +1764,12 @@ define float @vreduce_fminimum_v4f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v9, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v9
-; CHECK-NEXT:    beqz a0, .LBB106_2
+; CHECK-NEXT:    beqz a0, .LBB109_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB106_2:
+; CHECK-NEXT:  .LBB109_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -1758,12 +1803,12 @@ define float @vreduce_fminimum_v7f32(ptr %x) {
 ; CHECK-NEXT:    vsetivli zero, 7, e32, m2, ta, ma
 ; CHECK-NEXT:    vmfne.vv v10, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v10, v0.t
-; CHECK-NEXT:    beqz a0, .LBB108_2
+; CHECK-NEXT:    beqz a0, .LBB111_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB108_2:
+; CHECK-NEXT:  .LBB111_2:
 ; CHECK-NEXT:    lui a0, 522240
 ; CHECK-NEXT:    vmv.s.x v10, a0
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v10
@@ -1798,12 +1843,12 @@ define float @vreduce_fminimum_v8f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v10, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v10
-; CHECK-NEXT:    beqz a0, .LBB110_2
+; CHECK-NEXT:    beqz a0, .LBB113_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB110_2:
+; CHECK-NEXT:  .LBB113_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -1834,12 +1879,12 @@ define float @vreduce_fminimum_v16f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v12, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v12
-; CHECK-NEXT:    beqz a0, .LBB112_2
+; CHECK-NEXT:    beqz a0, .LBB115_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB112_2:
+; CHECK-NEXT:  .LBB115_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -1871,12 +1916,12 @@ define float @vreduce_fminimum_v32f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB114_2
+; CHECK-NEXT:    beqz a0, .LBB117_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB114_2:
+; CHECK-NEXT:  .LBB117_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -1926,15 +1971,15 @@ define float @vreduce_fminimum_v64f32(ptr %x) {
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB116_2
+; CHECK-NEXT:    beqz a0, .LBB119_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
-; CHECK-NEXT:    j .LBB116_3
-; CHECK-NEXT:  .LBB116_2:
+; CHECK-NEXT:    j .LBB119_3
+; CHECK-NEXT:  .LBB119_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB116_3:
+; CHECK-NEXT:  .LBB119_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add sp, sp, a0
@@ -2048,15 +2093,15 @@ define float @vreduce_fminimum_v128f32(ptr %x) {
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB118_2
+; CHECK-NEXT:    beqz a0, .LBB121_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
-; CHECK-NEXT:    j .LBB118_3
-; CHECK-NEXT:  .LBB118_2:
+; CHECK-NEXT:    j .LBB121_3
+; CHECK-NEXT:  .LBB121_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB118_3:
+; CHECK-NEXT:  .LBB121_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    mv a1, a0
@@ -2102,12 +2147,12 @@ define double @vreduce_fminimum_v2f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v9, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v9
-; CHECK-NEXT:    beqz a0, .LBB120_2
+; CHECK-NEXT:    beqz a0, .LBB123_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI120_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI120_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI123_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI123_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB120_2:
+; CHECK-NEXT:  .LBB123_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2138,12 +2183,12 @@ define double @vreduce_fminimum_v4f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v10, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v10
-; CHECK-NEXT:    beqz a0, .LBB122_2
+; CHECK-NEXT:    beqz a0, .LBB125_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI122_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI122_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI125_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI125_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB122_2:
+; CHECK-NEXT:  .LBB125_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2174,12 +2219,12 @@ define double @vreduce_fminimum_v8f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v12, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v12
-; CHECK-NEXT:    beqz a0, .LBB124_2
+; CHECK-NEXT:    beqz a0, .LBB127_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI124_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI124_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI127_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI127_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB124_2:
+; CHECK-NEXT:  .LBB127_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2210,12 +2255,12 @@ define double @vreduce_fminimum_v16f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB126_2
+; CHECK-NEXT:    beqz a0, .LBB129_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI126_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI126_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI129_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI129_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB126_2:
+; CHECK-NEXT:  .LBB129_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2263,15 +2308,15 @@ define double @vreduce_fminimum_v32f64(ptr %x) {
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB128_2
+; CHECK-NEXT:    beqz a0, .LBB131_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI128_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI128_0)(a0)
-; CHECK-NEXT:    j .LBB128_3
-; CHECK-NEXT:  .LBB128_2:
+; CHECK-NEXT:    lui a0, %hi(.LCPI131_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI131_0)(a0)
+; CHECK-NEXT:    j .LBB131_3
+; CHECK-NEXT:  .LBB131_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB128_3:
+; CHECK-NEXT:  .LBB131_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add sp, sp, a0
@@ -2383,15 +2428,15 @@ define double @vreduce_fminimum_v64f64(ptr %x) {
 ; CHECK-NEXT:    vfmin.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB130_2
+; CHECK-NEXT:    beqz a0, .LBB133_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI130_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI130_0)(a0)
-; CHECK-NEXT:    j .LBB130_3
-; CHECK-NEXT:  .LBB130_2:
+; CHECK-NEXT:    lui a0, %hi(.LCPI133_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI133_0)(a0)
+; CHECK-NEXT:    j .LBB133_3
+; CHECK-NEXT:  .LBB133_2:
 ; CHECK-NEXT:    vfredmin.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB130_3:
+; CHECK-NEXT:  .LBB133_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    mv a1, a0
@@ -2436,12 +2481,12 @@ define float @vreduce_fmaximum_v2f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v9, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v9
-; CHECK-NEXT:    beqz a0, .LBB132_2
+; CHECK-NEXT:    beqz a0, .LBB135_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB132_2:
+; CHECK-NEXT:  .LBB135_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2472,12 +2517,12 @@ define float @vreduce_fmaximum_v4f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v9, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v9
-; CHECK-NEXT:    beqz a0, .LBB134_2
+; CHECK-NEXT:    beqz a0, .LBB137_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB134_2:
+; CHECK-NEXT:  .LBB137_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2511,12 +2556,12 @@ define float @vreduce_fmaximum_v7f32(ptr %x) {
 ; CHECK-NEXT:    vsetivli zero, 7, e32, m2, ta, ma
 ; CHECK-NEXT:    vmfne.vv v10, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v10, v0.t
-; CHECK-NEXT:    beqz a0, .LBB136_2
+; CHECK-NEXT:    beqz a0, .LBB139_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB136_2:
+; CHECK-NEXT:  .LBB139_2:
 ; CHECK-NEXT:    lui a0, 1046528
 ; CHECK-NEXT:    vmv.s.x v10, a0
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v10
@@ -2551,12 +2596,12 @@ define float @vreduce_fmaximum_v8f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v10, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v10
-; CHECK-NEXT:    beqz a0, .LBB138_2
+; CHECK-NEXT:    beqz a0, .LBB141_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB138_2:
+; CHECK-NEXT:  .LBB141_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2587,12 +2632,12 @@ define float @vreduce_fmaximum_v16f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v12, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v12
-; CHECK-NEXT:    beqz a0, .LBB140_2
+; CHECK-NEXT:    beqz a0, .LBB143_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB140_2:
+; CHECK-NEXT:  .LBB143_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2624,12 +2669,12 @@ define float @vreduce_fmaximum_v32f32(ptr %x) {
 ; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB142_2
+; CHECK-NEXT:    beqz a0, .LBB145_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB142_2:
+; CHECK-NEXT:  .LBB145_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2679,15 +2724,15 @@ define float @vreduce_fmaximum_v64f32(ptr %x) {
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB144_2
+; CHECK-NEXT:    beqz a0, .LBB147_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
-; CHECK-NEXT:    j .LBB144_3
-; CHECK-NEXT:  .LBB144_2:
+; CHECK-NEXT:    j .LBB147_3
+; CHECK-NEXT:  .LBB147_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB144_3:
+; CHECK-NEXT:  .LBB147_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add sp, sp, a0
@@ -2801,15 +2846,15 @@ define float @vreduce_fmaximum_v128f32(ptr %x) {
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB146_2
+; CHECK-NEXT:    beqz a0, .LBB149_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    lui a0, 523264
 ; CHECK-NEXT:    fmv.w.x fa0, a0
-; CHECK-NEXT:    j .LBB146_3
-; CHECK-NEXT:  .LBB146_2:
+; CHECK-NEXT:    j .LBB149_3
+; CHECK-NEXT:  .LBB149_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB146_3:
+; CHECK-NEXT:  .LBB149_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    mv a1, a0
@@ -2855,12 +2900,12 @@ define double @vreduce_fmaximum_v2f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v9, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v9
-; CHECK-NEXT:    beqz a0, .LBB148_2
+; CHECK-NEXT:    beqz a0, .LBB151_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI148_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI148_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI151_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI151_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB148_2:
+; CHECK-NEXT:  .LBB151_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2891,12 +2936,12 @@ define double @vreduce_fmaximum_v4f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v10, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v10
-; CHECK-NEXT:    beqz a0, .LBB150_2
+; CHECK-NEXT:    beqz a0, .LBB153_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI150_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI150_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI153_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI153_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB150_2:
+; CHECK-NEXT:  .LBB153_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2927,12 +2972,12 @@ define double @vreduce_fmaximum_v8f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v12, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v12
-; CHECK-NEXT:    beqz a0, .LBB152_2
+; CHECK-NEXT:    beqz a0, .LBB155_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI152_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI152_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI155_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI155_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB152_2:
+; CHECK-NEXT:  .LBB155_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -2963,12 +3008,12 @@ define double @vreduce_fmaximum_v16f64(ptr %x) {
 ; CHECK-NEXT:    vle64.v v8, (a0)
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB154_2
+; CHECK-NEXT:    beqz a0, .LBB157_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI154_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI154_0)(a0)
+; CHECK-NEXT:    lui a0, %hi(.LCPI157_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI157_0)(a0)
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB154_2:
+; CHECK-NEXT:  .LBB157_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
@@ -3016,15 +3061,15 @@ define double @vreduce_fmaximum_v32f64(ptr %x) {
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB156_2
+; CHECK-NEXT:    beqz a0, .LBB159_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI156_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI156_0)(a0)
-; CHECK-NEXT:    j .LBB156_3
-; CHECK-NEXT:  .LBB156_2:
+; CHECK-NEXT:    lui a0, %hi(.LCPI159_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI159_0)(a0)
+; CHECK-NEXT:    j .LBB159_3
+; CHECK-NEXT:  .LBB159_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB156_3:
+; CHECK-NEXT:  .LBB159_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    add sp, sp, a0
@@ -3136,15 +3181,15 @@ define double @vreduce_fmaximum_v64f64(ptr %x) {
 ; CHECK-NEXT:    vfmax.vv v8, v8, v16
 ; CHECK-NEXT:    vmfne.vv v16, v8, v8
 ; CHECK-NEXT:    vcpop.m a0, v16
-; CHECK-NEXT:    beqz a0, .LBB158_2
+; CHECK-NEXT:    beqz a0, .LBB161_2
 ; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    lui a0, %hi(.LCPI158_0)
-; CHECK-NEXT:    fld fa0, %lo(.LCPI158_0)(a0)
-; CHECK-NEXT:    j .LBB158_3
-; CHECK-NEXT:  .LBB158_2:
+; CHECK-NEXT:    lui a0, %hi(.LCPI161_0)
+; CHECK-NEXT:    fld fa0, %lo(.LCPI161_0)(a0)
+; CHECK-NEXT:    j .LBB161_3
+; CHECK-NEXT:  .LBB161_2:
 ; CHECK-NEXT:    vfredmax.vs v8, v8, v8
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
-; CHECK-NEXT:  .LBB158_3:
+; CHECK-NEXT:  .LBB161_3:
 ; CHECK-NEXT:    csrr a0, vlenb
 ; CHECK-NEXT:    slli a0, a0, 3
 ; CHECK-NEXT:    mv a1, a0