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AMDGPU: Replace undef with poison in tests using insertvalue (#130895)

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perl -p -i -e 's/insertvalue (.*) undef/insertvalue \1 poison/g'
This commit is contained in:
Matt Arsenault 2025-03-12 16:11:11 +07:00 committed by GitHub
parent 5daba3dfd9
commit 5a0a2f8239
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GPG Key ID: B5690EEEBB952194
31 changed files with 178 additions and 176 deletions
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22
llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll
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@ -64,7 +64,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i32 %src1, -1
%and = and i32 %src0, %not.src1
%insert.0 = insertvalue { i32, i32 } undef, i32 %and, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %and, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 1
ret { i32, i32 } %insert.1
}
@ -90,7 +90,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_foldable_use(i32 inreg %src0, i
%not.src2 = xor i32 %src2, -1
%and0 = and i32 %src0, %not.src2
%and1 = and i32 %src1, %not.src2
%insert.0 = insertvalue { i32, i32 } undef, i32 %and0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %and0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %and1, 1
ret { i32, i32 } %insert.1
}
@ -211,7 +211,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i
%not.src2 = xor i64 %src2, -1
%and0 = and i64 %src0, %not.src2
%and1 = and i64 %src1, %not.src2
%insert.0 = insertvalue { i64, i64 } undef, i64 %and0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %and0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %and1, 1
ret { i64, i64 } %insert.1
}
@ -238,7 +238,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_use(i64 inreg %src0, i64 inreg
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i64 %src1, -1
%and = and i64 %src0, %not.src1
%insert.0 = insertvalue { i64, i64 } undef, i64 %and, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %and, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1
ret { i64, i64 } %insert.1
}
@ -408,7 +408,7 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1
%insert.0 = insertvalue { i16, i16 } undef, i16 %and, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %and, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
ret { i16, i16 } %insert.1
}
@ -434,7 +434,7 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i
%not.src2 = xor i16 %src2, -1
%and0 = and i16 %src0, %not.src2
%and1 = and i16 %src1, %not.src2
%insert.0 = insertvalue { i16, i16 } undef, i16 %and0, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %and0, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %and1, 1
ret { i16, i16 } %insert.1
}
@ -601,7 +601,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2
%cast.0 = bitcast <2 x i16> %and to i32
%cast.1 = bitcast <2 x i16> %not.src1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
@ -646,7 +646,7 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg
%cast.0 = bitcast <2 x i16> %and0 to i32
%cast.1 = bitcast <2 x i16> %and1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
@ -857,7 +857,7 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
%and = and <3 x i16> %src0, %not.src1
%cast.0 = bitcast <3 x i16> %and to i48
%cast.1 = bitcast <3 x i16> %not.src1 to i48
%insert.0 = insertvalue { i48, i48 } undef, i48 %cast.0, 0
%insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0
%insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1
ret { i48, i48 } %insert.1
}
@ -1028,7 +1028,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_use(<4 x i16> inreg %src0, <4
%cast.0 = bitcast <4 x i16> %and to i64
%cast.1 = bitcast <4 x i16> %not.src1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}
@ -1082,7 +1082,7 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_foldable_use(<4 x i16> inreg
%cast.0 = bitcast <4 x i16> %and0 to i64
%cast.1 = bitcast <4 x i16> %and1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}

6
llvm/test/CodeGen/AMDGPU/GlobalISel/function-returns.ll
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@ -1061,6 +1061,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@ -1083,7 +1084,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
%insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
%insert.3 = insertvalue { <3 x i32>, i32 } undef, <3 x i32> %insert.2, 0
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
%insert.4 = insertvalue { <3 x i32>, i32 } %insert.3, i32 %load3, 1
ret { <3 x i32>, i32 } %insert.4
}
@ -1096,6 +1097,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY [[DEF1]](<3 x s32>)
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p3) :: (volatile load (s32) from `ptr addrspace(3) undef`, addrspace 3)
@ -1118,7 +1120,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
%insert.0 = insertelement <3 x float> undef, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
%insert.3 = insertvalue { <3 x float>, i32 } undef, <3 x float> %insert.2, 0
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
%insert.4 = insertvalue { <3 x float>, i32 } %insert.3, i32 %load3, 1
ret { <3 x float>, i32 } %insert.4
}

2
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll
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@ -104,7 +104,7 @@ define amdgpu_ps { i32, i32 } @sgpr_struct_return_i32_i32(i32 %vgpr0, i32 %vgpr1
; CHECK-NEXT: [[INTRINSIC_CONVERGENT1:%[0-9]+]]:_(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32)
; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
%insertvalue0 = insertvalue { i32, i32 } undef, i32 %vgpr0, 0
%insertvalue0 = insertvalue { i32, i32 } poison, i32 %vgpr0, 0
%value = insertvalue { i32, i32 } %insertvalue0, i32 %vgpr1, 1
ret { i32, i32 } %value
}

2
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll
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@ -88,7 +88,7 @@ define amdgpu_vs <{ i32, i32 }> @ret_struct(i32 inreg %arg0, i32 inreg %arg1) {
; CHECK-NEXT: $sgpr1 = COPY [[INTRINSIC_CONVERGENT1]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
main_body:
%tmp0 = insertvalue <{ i32, i32 }> undef, i32 %arg0, 0
%tmp0 = insertvalue <{ i32, i32 }> poison, i32 %arg0, 0
%tmp1 = insertvalue <{ i32, i32 }> %tmp0, i32 %arg1, 1
ret <{ i32, i32 }> %tmp1
}

22
llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll
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@ -64,7 +64,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg %
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i32 %src1, -1
%or = or i32 %src0, %not.src1
%insert.0 = insertvalue { i32, i32 } undef, i32 %or, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %or, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %not.src1, 1
ret { i32, i32 } %insert.1
}
@ -90,7 +90,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_foldable_use(i32 inreg %src0, i3
%not.src2 = xor i32 %src2, -1
%or0 = or i32 %src0, %not.src2
%or1 = or i32 %src1, %not.src2
%insert.0 = insertvalue { i32, i32 } undef, i32 %or0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %or0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %or1, 1
ret { i32, i32 } %insert.1
}
@ -211,7 +211,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i6
%not.src2 = xor i64 %src2, -1
%or0 = or i64 %src0, %not.src2
%or1 = or i64 %src1, %not.src2
%insert.0 = insertvalue { i64, i64 } undef, i64 %or0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %or0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %or1, 1
ret { i64, i64 } %insert.1
}
@ -238,7 +238,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_use(i64 inreg %src0, i64 inreg %
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i64 %src1, -1
%or = or i64 %src0, %not.src1
%insert.0 = insertvalue { i64, i64 } undef, i64 %or, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %or, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %not.src1, 1
ret { i64, i64 } %insert.1
}
@ -408,7 +408,7 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %
; GFX11-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1
%or = or i16 %src0, %not.src1
%insert.0 = insertvalue { i16, i16 } undef, i16 %or, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %or, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
ret { i16, i16 } %insert.1
}
@ -434,7 +434,7 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i1
%not.src2 = xor i16 %src2, -1
%or0 = or i16 %src0, %not.src2
%or1 = or i16 %src1, %not.src2
%insert.0 = insertvalue { i16, i16 } undef, i16 %or0, 0
%insert.0 = insertvalue { i16, i16 } poison, i16 %or0, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %or1, 1
ret { i16, i16 } %insert.1
}
@ -601,7 +601,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2
%cast.0 = bitcast <2 x i16> %or to i32
%cast.1 = bitcast <2 x i16> %not.src1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
@ -646,7 +646,7 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg %
%cast.0 = bitcast <2 x i16> %or0 to i32
%cast.1 = bitcast <2 x i16> %or1 to i32
%insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
%insert.0 = insertvalue { i32, i32 } poison, i32 %cast.0, 0
%insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1
ret { i32, i32 } %insert.1
}
@ -856,7 +856,7 @@ define amdgpu_ps { i48, i48 } @s_orn2_v3i16_multi_use(<3 x i16> inreg %src0, <3
%or = or <3 x i16> %src0, %not.src1
%cast.0 = bitcast <3 x i16> %or to i48
%cast.1 = bitcast <3 x i16> %not.src1 to i48
%insert.0 = insertvalue { i48, i48 } undef, i48 %cast.0, 0
%insert.0 = insertvalue { i48, i48 } poison, i48 %cast.0, 0
%insert.1 = insertvalue { i48, i48 } %insert.0, i48 %cast.1, 1
ret { i48, i48 } %insert.1
}
@ -1027,7 +1027,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_use(<4 x i16> inreg %src0, <4
%cast.0 = bitcast <4 x i16> %or to i64
%cast.1 = bitcast <4 x i16> %not.src1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}
@ -1081,7 +1081,7 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_foldable_use(<4 x i16> inreg %
%cast.0 = bitcast <4 x i16> %or0 to i64
%cast.1 = bitcast <4 x i16> %or1 to i64
%insert.0 = insertvalue { i64, i64 } undef, i64 %cast.0, 0
%insert.0 = insertvalue { i64, i64 } poison, i64 %cast.0, 0
%insert.1 = insertvalue { i64, i64 } %insert.0, i64 %cast.1, 1
ret { i64, i64 } %insert.1
}

8
llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll
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@ -476,7 +476,7 @@ define amdgpu_ps { i32, i32 } @s_shl4_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 4
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
@ -489,7 +489,7 @@ define amdgpu_ps { i32, i32 } @s_shl3_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 3
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
@ -502,7 +502,7 @@ define amdgpu_ps { i32, i32 } @s_shl2_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 2
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}
@ -516,7 +516,7 @@ define amdgpu_ps { i32, i32 } @s_shl1_add_u32_multi_use(i32 inreg %src0, i32 inr
; GCN-NEXT: ; return to shader part epilog
%shl = shl i32 %src0, 1
%add = add i32 %shl, %src1
%insert0 = insertvalue { i32, i32 } undef, i32 %shl, 0
%insert0 = insertvalue { i32, i32 } poison, i32 %shl, 0
%insert1 = insertvalue { i32, i32 } %insert0, i32 %add, 1
ret { i32, i32 } %insert1
}

2
llvm/test/CodeGen/AMDGPU/cc-sgpr-limit.ll
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@ -62,7 +62,7 @@ define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
%56 = add i32 %55, %27
%57 = add i32 %56, %28
%58 = add i32 %57, %29
%59 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } undef, i32 %30, 0
%59 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %30, 0
%60 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %59, i32 %31, 1
%61 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %60, i32 %32, 2
%62 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %61, i32 %33, 3

2
llvm/test/CodeGen/AMDGPU/cc-sgpr-over-limit.ll
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@ -50,7 +50,7 @@ define amdgpu_gs { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i
%88 = add i32 %87, %43
%89 = add i32 %88, %44
%90 = add i32 %89, %45
%91 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } undef, i32 %46, 0
%91 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } poison, i32 %46, 0
%92 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %91, i32 %47, 1
%93 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %92, i32 %48, 2
%94 = insertvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %93, i32 %49, 3

4
llvm/test/CodeGen/AMDGPU/constant-address-space-32bit.ll
View File

@ -247,7 +247,7 @@ main_body:
%34 = extractelement <4 x float> %31, i32 2
%35 = extractelement <4 x float> %31, i32 3
%36 = bitcast float %4 to i32
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, i32 %36, 4
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7
@ -279,7 +279,7 @@ main_body:
%34 = extractelement <4 x float> %31, i32 2
%35 = extractelement <4 x float> %31, i32 3
%36 = bitcast float %4 to i32
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %36, 4
%37 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, i32 %36, 4
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %37, float %32, 5
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 6
%40 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %39, float %34, 7

2
llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
View File

@ -168,7 +168,7 @@ bb1:
%val1 = extractvalue { <4 x i32>, <4 x half> } %split.ret.type, 1
%extract0 = extractelement <4 x i32> %val0, i32 0
%extract1 = extractelement <4 x half> %val1, i32 0
%ins0 = insertvalue { i32, half } undef, i32 %extract0, 0
%ins0 = insertvalue { i32, half } poison, i32 %extract0, 0
%ins1 = insertvalue { i32, half } %ins0, half %extract1, 1
ret { i32, half } %ins1
}

2
llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
View File

@ -30,7 +30,7 @@ bb:
%tmp3 = fsub fast double %arg2, %arg
%tmp4 = fadd fast double %tmp3, %tmp
%tmp5 = fsub fast double %tmp, %tmp3
%tmp6 = insertvalue { double, double } undef, double %tmp4, 0
%tmp6 = insertvalue { double, double } poison, double %tmp4, 0
%tmp7 = insertvalue { double, double } %tmp6, double %tmp5, 1
ret { double, double } %tmp7
}

4
llvm/test/CodeGen/AMDGPU/function-returns.ll
View File

@ -2210,7 +2210,7 @@ define { <3 x i32>, i32 } @v3i32_struct_func_void_wasted_reg() #0 {
%insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
%insert.1 = insertelement <3 x i32> %insert.0, i32 %load1, i32 1
%insert.2 = insertelement <3 x i32> %insert.1, i32 %load2, i32 2
%insert.3 = insertvalue { <3 x i32>, i32 } undef, <3 x i32> %insert.2, 0
%insert.3 = insertvalue { <3 x i32>, i32 } poison, <3 x i32> %insert.2, 0
%insert.4 = insertvalue { <3 x i32>, i32 } %insert.3, i32 %load3, 1
ret { <3 x i32>, i32 } %insert.4
}
@ -2269,7 +2269,7 @@ define { <3 x float>, i32 } @v3f32_struct_func_void_wasted_reg() #0 {
%insert.0 = insertelement <3 x float> undef, float %load0, i32 0
%insert.1 = insertelement <3 x float> %insert.0, float %load1, i32 1
%insert.2 = insertelement <3 x float> %insert.1, float %load2, i32 2
%insert.3 = insertvalue { <3 x float>, i32 } undef, <3 x float> %insert.2, 0
%insert.3 = insertvalue { <3 x float>, i32 } poison, <3 x float> %insert.2, 0
%insert.4 = insertvalue { <3 x float>, i32 } %insert.3, i32 %load3, 1
ret { <3 x float>, i32 } %insert.4
}

162
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.load.2dmsaa.ll
View File

@ -11,7 +11,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask1(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -25,7 +25,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask1(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -36,7 +36,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -51,7 +51,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask2(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 2, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 2, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 2, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -65,7 +65,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask2(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -76,7 +76,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 2, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 2, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 2, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -91,7 +91,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask4(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 4, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 4, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 4, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -105,7 +105,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask4(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -116,7 +116,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 4, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 4, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 4, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -131,7 +131,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask8(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 8, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 8, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 8, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -145,7 +145,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask8(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -156,7 +156,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 8, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 8, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 8, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -171,7 +171,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_reverse(<8 x i32> inreg %rsrc, i
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -185,7 +185,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_reverse(<8 x i32> inreg %rsrc, i
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -196,7 +196,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -212,7 +212,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_vaddr(<8 x i32> inreg %rsrc, i32
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S1]], i32 [[T1]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S2]], i32 [[T2]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S3]], i32 [[T3]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -225,7 +225,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_vaddr(<8 x i32> inreg %rsrc, i32
; MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S1]], i32 [[T1]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S2]], i32 [[T2]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S3]], i32 [[T3]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -236,7 +236,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s1, i32 %t1, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s2, i32 %t2, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s3, i32 %t3, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -255,7 +255,7 @@ define amdgpu_ps [8 x float] @load_2dmsaa_v8f32(<8 x i32> inreg %rsrc, i32 %s, i
; NO-MSAA-NEXT: [[I5:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I6:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I7:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I8:%.*]] = insertvalue [8 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I8:%.*]] = insertvalue [8 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I9:%.*]] = insertvalue [8 x float] [[I8]], float [[I1]], 1
; NO-MSAA-NEXT: [[I10:%.*]] = insertvalue [8 x float] [[I9]], float [[I2]], 2
; NO-MSAA-NEXT: [[I11:%.*]] = insertvalue [8 x float] [[I10]], float [[I3]], 3
@ -277,7 +277,7 @@ define amdgpu_ps [8 x float] @load_2dmsaa_v8f32(<8 x i32> inreg %rsrc, i32 %s, i
; MSAA-NEXT: [[I5:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I6:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I7:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I8:%.*]] = insertvalue [8 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I8:%.*]] = insertvalue [8 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I9:%.*]] = insertvalue [8 x float] [[I8]], float [[I1]], 1
; MSAA-NEXT: [[I10:%.*]] = insertvalue [8 x float] [[I9]], float [[I2]], 2
; MSAA-NEXT: [[I11:%.*]] = insertvalue [8 x float] [[I10]], float [[I3]], 3
@ -296,7 +296,7 @@ main_body:
%i5 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i6 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i7 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i8 = insertvalue [8 x float] undef, float %i, 0
%i8 = insertvalue [8 x float] poison, float %i, 0
%i9 = insertvalue [8 x float] %i8, float %i1, 1
%i10 = insertvalue [8 x float] %i9, float %i2, 2
%i11 = insertvalue [8 x float] %i10, float %i3, 3
@ -312,7 +312,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_interleaved(<8 x i32> inreg %rsr
; NO-MSAA-SAME: <8 x i32> inreg [[RSRC:%.*]], i32 [[S:%.*]], i32 [[T:%.*]]) #[[ATTR0]] {
; NO-MSAA-NEXT: main_body:
; NO-MSAA-NEXT: [[I:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I1:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I1:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = insertvalue [4 x float] [[I1]], float [[I2]], 1
; NO-MSAA-NEXT: [[I4:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
@ -329,7 +329,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_interleaved(<8 x i32> inreg %rsr
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I4:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I6:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I1:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I1:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I3:%.*]] = insertvalue [4 x float] [[I1]], float [[I2]], 1
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I3]], float [[I4]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I5]], float [[I6]], 3
@ -337,7 +337,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_interleaved(<8 x i32> inreg %rsr
;
main_body:
%i = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
%i1 = insertvalue [4 x float] undef, float %i, 0
%i1 = insertvalue [4 x float] poison, float %i, 0
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = insertvalue [4 x float] %i1, float %i2, 1
%i4 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
@ -353,7 +353,7 @@ define amdgpu_ps [2 x float] @load_2dmsaa_v2f32_fragId01(<8 x i32> inreg %rsrc,
; NO-MSAA-NEXT: main_body:
; NO-MSAA-NEXT: [[I:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I3:%.*]] = insertvalue [2 x float] [[I2]], float [[I1]], 1
; NO-MSAA-NEXT: ret [2 x float] [[I3]]
;
@ -363,14 +363,14 @@ define amdgpu_ps [2 x float] @load_2dmsaa_v2f32_fragId01(<8 x i32> inreg %rsrc,
; MSAA-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I:%.*]] = extractelement <4 x float> [[TMP0]], i64 0
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I3:%.*]] = insertvalue [2 x float] [[I2]], float [[I1]], 1
; MSAA-NEXT: ret [2 x float] [[I3]]
;
main_body:
%i = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = insertvalue [2 x float] undef, float %i, 0
%i2 = insertvalue [2 x float] poison, float %i, 0
%i3 = insertvalue [2 x float] %i2, float %i1, 1
ret [2 x float] %i3
}
@ -381,7 +381,7 @@ define amdgpu_ps [2 x float] @load_2dmsaa_v2f32_fragId23(<8 x i32> inreg %rsrc,
; NO-MSAA-NEXT: main_body:
; NO-MSAA-NEXT: [[I:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I3:%.*]] = insertvalue [2 x float] [[I2]], float [[I1]], 1
; NO-MSAA-NEXT: ret [2 x float] [[I3]]
;
@ -391,14 +391,14 @@ define amdgpu_ps [2 x float] @load_2dmsaa_v2f32_fragId23(<8 x i32> inreg %rsrc,
; MSAA-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I3:%.*]] = insertvalue [2 x float] [[I2]], float [[I1]], 1
; MSAA-NEXT: ret [2 x float] [[I3]]
;
main_body:
%i = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = insertvalue [2 x float] undef, float %i, 0
%i2 = insertvalue [2 x float] poison, float %i, 0
%i3 = insertvalue [2 x float] %i2, float %i1, 1
ret [2 x float] %i3
}
@ -411,7 +411,7 @@ define amdgpu_ps [2 x <2 x float>] @load_2dmsaa_v2v2f32_dmask3(<8 x i32> inreg %
; NO-MSAA-NEXT: main_body:
; NO-MSAA-NEXT: [[I:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [2 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [2 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [2 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: ret [2 x <2 x float>] [[I5]]
;
@ -420,14 +420,14 @@ define amdgpu_ps [2 x <2 x float>] @load_2dmsaa_v2v2f32_dmask3(<8 x i32> inreg %
; MSAA-NEXT: main_body:
; MSAA-NEXT: [[I:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I4:%.*]] = insertvalue [2 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [2 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [2 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: ret [2 x <2 x float>] [[I5]]
;
main_body:
%i = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [2 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [2 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [2 x <2 x float>] %i4, <2 x float> %i1, 1
ret [2 x <2 x float>] %i5
}
@ -443,7 +443,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask3(<8 x i32> inreg %
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -470,7 +470,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask3(<8 x i32> inreg %
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -481,7 +481,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -499,7 +499,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask5(<8 x i32> inreg %
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 5, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 5, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 5, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -526,7 +526,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask5(<8 x i32> inreg %
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -537,7 +537,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 5, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 5, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 5, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -555,7 +555,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask6(<8 x i32> inreg %
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 6, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 6, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 6, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -582,7 +582,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask6(<8 x i32> inreg %
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -593,7 +593,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 6, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 6, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 6, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -611,7 +611,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask9(<8 x i32> inreg %
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 9, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 9, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 9, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -638,7 +638,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask9(<8 x i32> inreg %
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -649,7 +649,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 9, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 9, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 9, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -667,7 +667,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask10(<8 x i32> inreg
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 10, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 10, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 10, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -694,7 +694,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask10(<8 x i32> inreg
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -705,7 +705,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 10, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 10, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 10, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -723,7 +723,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask12(<8 x i32> inreg
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 12, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 12, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 12, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -750,7 +750,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2dmsaa_v4v2f32_dmask12(<8 x i32> inreg
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -761,7 +761,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 12, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 12, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2dmsaa.v2f32.i32.v8i32(i32 12, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -774,7 +774,7 @@ define amdgpu_ps [2 x half] @load_2dmsaa_v2f16_fragId01(<8 x i32> inreg %rsrc, i
; NO-MSAA-NEXT: main_body:
; NO-MSAA-NEXT: [[I:%.*]] = call half @llvm.amdgcn.image.load.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I1:%.*]] = call half @llvm.amdgcn.image.load.2dmsaa.f16.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x half] undef, half [[I]], 0
; NO-MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x half] poison, half [[I]], 0
; NO-MSAA-NEXT: [[I3:%.*]] = insertvalue [2 x half] [[I2]], half [[I1]], 1
; NO-MSAA-NEXT: ret [2 x half] [[I3]]
;
@ -784,14 +784,14 @@ define amdgpu_ps [2 x half] @load_2dmsaa_v2f16_fragId01(<8 x i32> inreg %rsrc, i
; MSAA-NEXT: [[TMP0:%.*]] = call <4 x half> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f16.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I:%.*]] = extractelement <4 x half> [[TMP0]], i64 0
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x half> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x half] undef, half [[I]], 0
; MSAA-NEXT: [[I2:%.*]] = insertvalue [2 x half] poison, half [[I]], 0
; MSAA-NEXT: [[I3:%.*]] = insertvalue [2 x half] [[I2]], half [[I1]], 1
; MSAA-NEXT: ret [2 x half] [[I3]]
;
main_body:
%i = call half @llvm.amdgcn.image.load.2dmsaa.f16.i32.v8i32(i32 1, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
%i1 = call half @llvm.amdgcn.image.load.2dmsaa.f16.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = insertvalue [2 x half] undef, half %i, 0
%i2 = insertvalue [2 x half] poison, half %i, 0
%i3 = insertvalue [2 x half] %i2, half %i1, 1
ret [2 x half] %i3
}
@ -804,7 +804,7 @@ define amdgpu_ps [4 x float] @load_2darraymsaa_v4f32_dmask1(<8 x i32> inreg %rsr
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2darraymsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 [[SLICE]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2darraymsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 [[SLICE]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2darraymsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 [[SLICE]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -818,7 +818,7 @@ define amdgpu_ps [4 x float] @load_2darraymsaa_v4f32_dmask1(<8 x i32> inreg %rsr
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -829,7 +829,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2darraymsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2darraymsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2darraymsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 %slice, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -847,7 +847,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2darraymsaa_v4v2f32_dmask3(<8 x i32> in
; NO-MSAA-NEXT: [[I1:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2darraymsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 [[SLICE]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2darraymsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 [[SLICE]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <2 x float> @llvm.amdgcn.image.load.2darraymsaa.v2f32.i32.v8i32(i32 3, i32 [[S]], i32 [[T]], i32 [[SLICE]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -874,7 +874,7 @@ define amdgpu_ps [4 x <2 x float>] @load_2darraymsaa_v4v2f32_dmask3(<8 x i32> in
; MSAA-NEXT: [[TMP12:%.*]] = insertelement <2 x float> undef, float [[TMP11]], i64 0
; MSAA-NEXT: [[TMP13:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <2 x float> [[TMP12]], float [[TMP13]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] undef, <2 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <2 x float>] poison, <2 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <2 x float>] [[I4]], <2 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <2 x float>] [[I5]], <2 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <2 x float>] [[I6]], <2 x float> [[I3]], 3
@ -885,7 +885,7 @@ main_body:
%i1 = call <2 x float> @llvm.amdgcn.image.load.2darraymsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 %slice, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <2 x float> @llvm.amdgcn.image.load.2darraymsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 %slice, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <2 x float> @llvm.amdgcn.image.load.2darraymsaa.v2f32.i32.v8i32(i32 3, i32 %s, i32 %t, i32 %slice, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <2 x float>] undef, <2 x float> %i, 0
%i4 = insertvalue [4 x <2 x float>] poison, <2 x float> %i, 0
%i5 = insertvalue [4 x <2 x float>] %i4, <2 x float> %i1, 1
%i6 = insertvalue [4 x <2 x float>] %i5, <2 x float> %i2, 2
%i7 = insertvalue [4 x <2 x float>] %i6, <2 x float> %i3, 3
@ -905,7 +905,7 @@ define amdgpu_ps [4 x <3 x float>] @load_2dmsaa_v4v3f32_dmask7(<8 x i32> inreg %
; NO-MSAA-NEXT: [[I1:%.*]] = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] undef, <3 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] poison, <3 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <3 x float>] [[I4]], <3 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <3 x float>] [[I5]], <3 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <3 x float>] [[I6]], <3 x float> [[I3]], 3
@ -941,7 +941,7 @@ define amdgpu_ps [4 x <3 x float>] @load_2dmsaa_v4v3f32_dmask7(<8 x i32> inreg %
; MSAA-NEXT: [[TMP21:%.*]] = insertelement <3 x float> [[TMP19]], float [[TMP20]], i64 1
; MSAA-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <3 x float> [[TMP21]], float [[TMP22]], i64 2
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] undef, <3 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] poison, <3 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <3 x float>] [[I4]], <3 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <3 x float>] [[I5]], <3 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <3 x float>] [[I6]], <3 x float> [[I3]], 3
@ -952,7 +952,7 @@ main_body:
%i1 = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <3 x float>] undef, <3 x float> %i, 0
%i4 = insertvalue [4 x <3 x float>] poison, <3 x float> %i, 0
%i5 = insertvalue [4 x <3 x float>] %i4, <3 x float> %i1, 1
%i6 = insertvalue [4 x <3 x float>] %i5, <3 x float> %i2, 2
%i7 = insertvalue [4 x <3 x float>] %i6, <3 x float> %i3, 3
@ -972,7 +972,7 @@ define amdgpu_ps [4 x <3 x float>] @load_2dmsaa_v4v3f32_dmask7_group1(<8 x i32>
; NO-MSAA-NEXT: [[I1:%.*]] = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S]], i32 [[T]], i32 5, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S]], i32 [[T]], i32 6, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 [[S]], i32 [[T]], i32 7, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] undef, <3 x float> [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] poison, <3 x float> [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <3 x float>] [[I4]], <3 x float> [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <3 x float>] [[I5]], <3 x float> [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <3 x float>] [[I6]], <3 x float> [[I3]], 3
@ -1008,7 +1008,7 @@ define amdgpu_ps [4 x <3 x float>] @load_2dmsaa_v4v3f32_dmask7_group1(<8 x i32>
; MSAA-NEXT: [[TMP21:%.*]] = insertelement <3 x float> [[TMP19]], float [[TMP20]], i64 1
; MSAA-NEXT: [[TMP22:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
; MSAA-NEXT: [[I3:%.*]] = insertelement <3 x float> [[TMP21]], float [[TMP22]], i64 2
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] undef, <3 x float> [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x <3 x float>] poison, <3 x float> [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x <3 x float>] [[I4]], <3 x float> [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x <3 x float>] [[I5]], <3 x float> [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x <3 x float>] [[I6]], <3 x float> [[I3]], 3
@ -1019,7 +1019,7 @@ main_body:
%i1 = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 5, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 6, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call <3 x float> @llvm.amdgcn.image.load.2dmsaa.v3f32.i32.v8i32(i32 7, i32 %s, i32 %t, i32 7, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x <3 x float>] undef, <3 x float> %i, 0
%i4 = insertvalue [4 x <3 x float>] poison, <3 x float> %i, 0
%i5 = insertvalue [4 x <3 x float>] %i4, <3 x float> %i1, 1
%i6 = insertvalue [4 x <3 x float>] %i5, <3 x float> %i2, 2
%i7 = insertvalue [4 x <3 x float>] %i6, <3 x float> %i3, 3
@ -1035,7 +1035,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_sections(<8 x i32> inreg %rsrc,
; NO-MSAA-NEXT: call void @llvm.amdgcn.image.store.2dmsaa.f32.i32.v8i32(float [[VDATA]], i32 1, i32 [[S]], i32 [[T]], i32 [[FRAGID]], <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -1051,7 +1051,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_sections(<8 x i32> inreg %rsrc,
; MSAA-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC]], i32 0, i32 0)
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP1]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -1063,7 +1063,7 @@ main_body:
call void @llvm.amdgcn.image.store.2dmsaa.f32.i32(float %vdata, i32 1, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -1078,7 +1078,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_blocks(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -1089,7 +1089,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_blocks(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I10:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I11:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I12:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I13:%.*]] = insertvalue [4 x float] undef, float [[I9]], 0
; NO-MSAA-NEXT: [[I13:%.*]] = insertvalue [4 x float] poison, float [[I9]], 0
; NO-MSAA-NEXT: [[I14:%.*]] = insertvalue [4 x float] [[I13]], float [[I10]], 1
; NO-MSAA-NEXT: [[I15:%.*]] = insertvalue [4 x float] [[I14]], float [[I11]], 2
; NO-MSAA-NEXT: [[I16:%.*]] = insertvalue [4 x float] [[I15]], float [[I12]], 3
@ -1099,7 +1099,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_blocks(<8 x i32> inreg %rsrc, i3
; NO-MSAA-NEXT: [[I18:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I19:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 2, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I20:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 3, <8 x i32> [[RSRC]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I21:%.*]] = insertvalue [4 x float] undef, float [[I17]], 0
; NO-MSAA-NEXT: [[I21:%.*]] = insertvalue [4 x float] poison, float [[I17]], 0
; NO-MSAA-NEXT: [[I22:%.*]] = insertvalue [4 x float] [[I21]], float [[I18]], 1
; NO-MSAA-NEXT: [[I23:%.*]] = insertvalue [4 x float] [[I22]], float [[I19]], 2
; NO-MSAA-NEXT: [[I24:%.*]] = insertvalue [4 x float] [[I23]], float [[I20]], 3
@ -1116,7 +1116,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_blocks(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I1:%.*]] = extractelement <4 x float> [[TMP0]], i64 1
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP0]], i64 2
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP0]], i64 3
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -1128,7 +1128,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_blocks(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I10:%.*]] = extractelement <4 x float> [[TMP1]], i64 1
; MSAA-NEXT: [[I11:%.*]] = extractelement <4 x float> [[TMP1]], i64 2
; MSAA-NEXT: [[I12:%.*]] = extractelement <4 x float> [[TMP1]], i64 3
; MSAA-NEXT: [[I13:%.*]] = insertvalue [4 x float] undef, float [[I9]], 0
; MSAA-NEXT: [[I13:%.*]] = insertvalue [4 x float] poison, float [[I9]], 0
; MSAA-NEXT: [[I14:%.*]] = insertvalue [4 x float] [[I13]], float [[I10]], 1
; MSAA-NEXT: [[I15:%.*]] = insertvalue [4 x float] [[I14]], float [[I11]], 2
; MSAA-NEXT: [[I16:%.*]] = insertvalue [4 x float] [[I15]], float [[I12]], 3
@ -1139,7 +1139,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_blocks(<8 x i32> inreg %rsrc, i3
; MSAA-NEXT: [[I18:%.*]] = extractelement <4 x float> [[TMP2]], i64 1
; MSAA-NEXT: [[I19:%.*]] = extractelement <4 x float> [[TMP2]], i64 2
; MSAA-NEXT: [[I20:%.*]] = extractelement <4 x float> [[TMP2]], i64 3
; MSAA-NEXT: [[I21:%.*]] = insertvalue [4 x float] undef, float [[I17]], 0
; MSAA-NEXT: [[I21:%.*]] = insertvalue [4 x float] poison, float [[I17]], 0
; MSAA-NEXT: [[I22:%.*]] = insertvalue [4 x float] [[I21]], float [[I18]], 1
; MSAA-NEXT: [[I23:%.*]] = insertvalue [4 x float] [[I22]], float [[I19]], 2
; MSAA-NEXT: [[I24:%.*]] = insertvalue [4 x float] [[I23]], float [[I20]], 3
@ -1153,7 +1153,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3
@ -1164,7 +1164,7 @@ if_equal:
%i10 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i11 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i12 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i13 = insertvalue [4 x float] undef, float %i9, 0
%i13 = insertvalue [4 x float] poison, float %i9, 0
%i14 = insertvalue [4 x float] %i13, float %i10, 1
%i15 = insertvalue [4 x float] %i14, float %i11, 2
%i16 = insertvalue [4 x float] %i15, float %i12, 3
@ -1174,7 +1174,7 @@ if_unequal:
%i18 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc, i32 0, i32 0)
%i19 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 2, <8 x i32> %rsrc, i32 0, i32 0)
%i20 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 3, <8 x i32> %rsrc, i32 0, i32 0)
%i21 = insertvalue [4 x float] undef, float %i17, 0
%i21 = insertvalue [4 x float] poison, float %i17, 0
%i22 = insertvalue [4 x float] %i21, float %i18, 1
%i23 = insertvalue [4 x float] %i22, float %i19, 2
%i24 = insertvalue [4 x float] %i23, float %i20, 3
@ -1192,7 +1192,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask1_different_rsrc(<8 x i32>
; NO-MSAA-NEXT: [[I1:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC1]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I2:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC2]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I3:%.*]] = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 1, <8 x i32> [[RSRC2]], i32 0, i32 0)
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; NO-MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; NO-MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; NO-MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; NO-MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -1207,7 +1207,7 @@ define amdgpu_ps [4 x float] @load_2dmsaa_v4f32_dmask1_different_rsrc(<8 x i32>
; MSAA-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.amdgcn.image.msaa.load.2dmsaa.v4f32.i32.v8i32(i32 1, i32 [[S]], i32 [[T]], i32 0, <8 x i32> [[RSRC2]], i32 0, i32 0)
; MSAA-NEXT: [[I2:%.*]] = extractelement <4 x float> [[TMP1]], i64 0
; MSAA-NEXT: [[I3:%.*]] = extractelement <4 x float> [[TMP1]], i64 1
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] undef, float [[I]], 0
; MSAA-NEXT: [[I4:%.*]] = insertvalue [4 x float] poison, float [[I]], 0
; MSAA-NEXT: [[I5:%.*]] = insertvalue [4 x float] [[I4]], float [[I1]], 1
; MSAA-NEXT: [[I6:%.*]] = insertvalue [4 x float] [[I5]], float [[I2]], 2
; MSAA-NEXT: [[I7:%.*]] = insertvalue [4 x float] [[I6]], float [[I3]], 3
@ -1218,7 +1218,7 @@ main_body:
%i1 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc1, i32 0, i32 0)
%i2 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 0, <8 x i32> %rsrc2, i32 0, i32 0)
%i3 = call float @llvm.amdgcn.image.load.2dmsaa.f32.i32.v8i32(i32 1, i32 %s, i32 %t, i32 1, <8 x i32> %rsrc2, i32 0, i32 0)
%i4 = insertvalue [4 x float] undef, float %i, 0
%i4 = insertvalue [4 x float] poison, float %i, 0
%i5 = insertvalue [4 x float] %i4, float %i1, 1
%i6 = insertvalue [4 x float] %i5, float %i2, 2
%i7 = insertvalue [4 x float] %i6, float %i3, 3

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.format.ll
View File

@ -11,7 +11,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -30,7 +30,7 @@ main_body:
%fdata = bitcast <4 x i32> %data to <4 x float>
%fdata_glc = bitcast <4 x i32> %data_glc to <4 x float>
%fdata_slc = bitcast <4 x i32> %data_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %fdata, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %fdata, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %fdata_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %fdata_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

6
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
View File

@ -45,7 +45,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -90,7 +90,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 4)
%data_glc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 5)
%data_slc = call <4 x float> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 6)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -936,7 +936,7 @@ main_body:
%fdata = bitcast <4 x i32> %data to <4 x float>
%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
%fdata_slc = bitcast i32 %data_slc to float
%r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
%r0 = insertvalue {<4 x float>, <2 x float>, float} poison, <4 x float> %fdata, 0
%r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
%r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
ret {<4 x float>, <2 x float>, float} %r2

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.ll
View File

@ -11,7 +11,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

8
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.ll
View File

@ -34,7 +34,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -70,7 +70,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 4)
%data_glc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 5)
%data_slc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 6)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -106,7 +106,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 -2147483648)
%data_glc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 -2147483647)
%data_slc = call <4 x float> @llvm.amdgcn.raw.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 -2147483646)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -768,7 +768,7 @@ main_body:
%fdata = bitcast <4 x i32> %data to <4 x float>
%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
%fdata_slc = bitcast i32 %data_slc to float
%r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
%r0 = insertvalue {<4 x float>, <2 x float>, float} poison, <4 x float> %fdata, 0
%r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
%r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
ret {<4 x float>, <2 x float>, float} %r2

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.tbuffer.load.ll
View File

@ -41,7 +41,7 @@ main_body:
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
%r3 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r2, <4 x float> %vdata_f32, 3
@ -231,7 +231,7 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
View File

@ -53,7 +53,7 @@ main_body:
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
%r3 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r2, <4 x float> %vdata_f32, 3
@ -290,7 +290,7 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
View File

@ -58,7 +58,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.ll
View File

@ -11,7 +11,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.struct.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -138,7 +138,7 @@ main_body:
%fdata = bitcast <4 x i32> %data to <4 x float>
%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
%fdata_slc = bitcast i32 %data_slc to float
%r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
%r0 = insertvalue {<4 x float>, <2 x float>, float} poison, <4 x float> %fdata, 0
%r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
%r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
ret {<4 x float>, <2 x float>, float} %r2

2
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.format.ll
View File

@ -46,7 +46,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.format.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.buffer.load.ll
View File

@ -15,7 +15,7 @@ main_body:
%data = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 0)
%data_glc = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 1)
%data_slc = call <4 x float> @llvm.amdgcn.struct.ptr.buffer.load.v4f32(ptr addrspace(8) %0, i32 0, i32 0, i32 0, i32 2)
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %data, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2
@ -204,7 +204,7 @@ main_body:
%fdata = bitcast <4 x i32> %data to <4 x float>
%fdata_glc = bitcast <2 x i32> %data_glc to <2 x float>
%fdata_slc = bitcast i32 %data_slc to float
%r0 = insertvalue {<4 x float>, <2 x float>, float} undef, <4 x float> %fdata, 0
%r0 = insertvalue {<4 x float>, <2 x float>, float} poison, <4 x float> %fdata, 0
%r1 = insertvalue {<4 x float>, <2 x float>, float} %r0, <2 x float> %fdata_glc, 1
%r2 = insertvalue {<4 x float>, <2 x float>, float} %r1, float %fdata_slc, 2
ret {<4 x float>, <2 x float>, float} %r2

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.ptr.tbuffer.load.ll
View File

@ -44,7 +44,7 @@ main_body:
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
%r3 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r2, <4 x float> %vdata_f32, 3
@ -113,7 +113,7 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

4
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
View File

@ -57,7 +57,7 @@ main_body:
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
%r3 = insertvalue {<4 x float>, <4 x float>, <4 x float>, <4 x float>} %r2, <4 x float> %vdata_f32, 3
@ -144,7 +144,7 @@ define amdgpu_vs {<4 x float>, <4 x float>, <4 x float>} @tbuffer_load_immoffs_l
%vdata.f = bitcast <4 x i32> %vdata to <4 x float>
%vdata_glc.f = bitcast <4 x i32> %vdata_glc to <4 x float>
%vdata_slc.f = bitcast <4 x i32> %vdata_slc to <4 x float>
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %vdata.f, 0
%r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} poison, <4 x float> %vdata.f, 0
%r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %vdata_glc.f, 1
%r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %vdata_slc.f, 2
ret {<4 x float>, <4 x float>, <4 x float>} %r2

4
llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
View File

@ -337,7 +337,7 @@ define amdgpu_ps void @promote_double_aggr() #0 {
; CHECK-NEXT: [[FOO1:%.*]] = load double, ptr addrspace(1) [[FOO]], align 8
; CHECK-NEXT: [[FOO2:%.*]] = getelementptr { [4 x double], <2 x double>, <3 x double>, <4 x double> }, ptr addrspace(1) @tmp_g, i32 0, i32 0, i32 1
; CHECK-NEXT: [[FOO3:%.*]] = load double, ptr addrspace(1) [[FOO2]], align 8
; CHECK-NEXT: [[FOO4:%.*]] = insertvalue [2 x double] undef, double [[FOO1]], 0
; CHECK-NEXT: [[FOO4:%.*]] = insertvalue [2 x double] poison, double [[FOO1]], 0
; CHECK-NEXT: [[FOO5:%.*]] = insertvalue [2 x double] [[FOO4]], double [[FOO3]], 1
; CHECK-NEXT: [[FOO5_FCA_0_EXTRACT:%.*]] = extractvalue [2 x double] [[FOO5]], 0
; CHECK-NEXT: [[FOO5_FCA_1_EXTRACT:%.*]] = extractvalue [2 x double] [[FOO5]], 1
@ -356,7 +356,7 @@ define amdgpu_ps void @promote_double_aggr() #0 {
%foo1 = load double, ptr addrspace(1) %foo
%foo2 = getelementptr { [4 x double], <2 x double>, <3 x double>, <4 x double> }, ptr addrspace(1) @tmp_g, i32 0, i32 0, i32 1
%foo3 = load double, ptr addrspace(1) %foo2
%foo4 = insertvalue [2 x double] undef, double %foo1, 0
%foo4 = insertvalue [2 x double] poison, double %foo1, 0
%foo5 = insertvalue [2 x double] %foo4, double %foo3, 1
store [2 x double] %foo5, ptr addrspace(5) %s
%foo6 = getelementptr [2 x double], ptr addrspace(5) %s, i32 0, i32 1

26
llvm/test/CodeGen/AMDGPU/ps-shader-arg-count.ll
View File

@ -7,7 +7,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_1_arg(i32 inreg %arg, i32
.entry:
%i1 = extractelement <2 x float> %arg3, i32 1
%ret1 = insertelement <4 x float> undef, float %i1, i32 0
%ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1, 0
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1, 0
ret { <4 x float> } %ret2
}
@ -21,7 +21,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_3_arg(i32 inreg %arg, i32
%ret1 = insertelement <4 x float> undef, float %i1, i32 0
%ret1.1 = insertelement <4 x float> %ret1, float %i2, i32 1
%ret1.2 = insertelement <4 x float> %ret1.1, float %i3, i32 2
%ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1.2, 0
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1.2, 0
ret { <4 x float> } %ret2
}
@ -33,7 +33,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_gap(i32 inreg %arg,
%i3 = extractelement <2 x float> %arg5, i32 1
%ret1 = insertelement <4 x float> undef, float %i1, i32 0
%ret1.2 = insertelement <4 x float> %ret1, float %i3, i32 1
%ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1.2, 0
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1.2, 0
ret { <4 x float> } %ret2
}
@ -47,7 +47,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_2_arg_no_pack(i32 inreg %
%i3 = extractelement <2 x float> %arg5, i32 1
%ret1 = insertelement <4 x float> undef, float %i1, i32 0
%ret1.2 = insertelement <4 x float> %ret1, float %i3, i32 1
%ret2 = insertvalue { <4 x float> } undef, <4 x float> %ret1.2, 0
%ret2 = insertvalue { <4 x float> } poison, <4 x float> %ret1.2, 0
ret { <4 x float> } %ret2
}
@ -88,7 +88,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } poison, <4 x float> %ret1.3, 0
%ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
%ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
%ret.res = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
@ -134,7 +134,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg17.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg18.f, i32 3
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } poison, <4 x float> %ret1.3, 0
%ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
%ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
%ret.res = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
@ -183,7 +183,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg15_16.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg17_18.f, i32 3
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } poison, <4 x float> %ret1.3, 0
%ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
%ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
%ret.res = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
@ -215,7 +215,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used(i32
%ret4.1 = insertelement <4 x float> undef, float %extra_arg1, i32 0
%ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg2, i32 1
%ret.res = insertvalue { <4 x float> } undef, <4 x float> %ret4.2, 0
%ret.res = insertvalue { <4 x float> } poison, <4 x float> %ret4.2, 0
ret { <4 x float> } %ret.res
}
@ -228,7 +228,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_used(i3
%ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg1, i32 1
%ret4.3 = insertelement <4 x float> %ret4.2, float %extra_arg2, i32 2
%ret.res = insertvalue { <4 x float> } undef, <4 x float> %ret4.3, 0
%ret.res = insertvalue { <4 x float> } poison, <4 x float> %ret4.3, 0
ret { <4 x float> } %ret.res
}
@ -241,7 +241,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_part_unused_extra_unused(
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg13, i32 1
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg14, i32 2
%ret.res = insertvalue { <4 x float> } undef, <4 x float> %ret4.3, 0
%ret.res = insertvalue { <4 x float> } poison, <4 x float> %ret4.3, 0
ret { <4 x float> } %ret.res
}
@ -262,7 +262,7 @@ define dllexport amdgpu_ps { <4 x float> } @_amdgpu_ps_all_unused_extra_used_no_
%ret4.1 = insertelement <4 x float> undef, float %extra_arg1, i32 0
%ret4.2 = insertelement <4 x float> %ret4.1, float %extra_arg2, i32 1
%ret.res = insertvalue { <4 x float> } undef, <4 x float> %ret4.2, 0
%ret.res = insertvalue { <4 x float> } poison, <4 x float> %ret4.2, 0
ret { <4 x float> } %ret.res
}
@ -310,7 +310,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%ret4.2 = insertelement <4 x float> %ret4.1, float %arg15.f, i32 2
%ret4.3 = insertelement <4 x float> %ret4.2, float %arg16.f, i32 3
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } poison, <4 x float> %ret1.3, 0
%ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
%ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
%ret.res = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.3, 3
@ -349,7 +349,7 @@ define dllexport amdgpu_ps { <4 x float>, <4 x float>, <4 x float>, <4 x float>
%ret4 = insertelement <4 x float> undef, float %extra_arg1, i32 0
%ret4.1 = insertelement <4 x float> %ret4, float %extra_arg2, i32 1
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } undef, <4 x float> %ret1.3, 0
%ret.res1 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } poison, <4 x float> %ret1.3, 0
%ret.res2 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res1, <4 x float> %ret2.3, 1
%ret.res3 = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res2, <4 x float> %ret3.3, 2
%ret.res = insertvalue { < 4 x float>, <4 x float>, <4 x float>, <4 x float> } %ret.res3, <4 x float> %ret4.1, 3

16
llvm/test/CodeGen/AMDGPU/ret.ll
View File

@ -13,7 +13,7 @@ define amdgpu_vs { float, float } @vgpr(ptr addrspace(4) inreg %arg, i32 inreg %
bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
%x = fadd float %arg3, 1.000000e+00
%a = insertvalue { float, float } undef, float %x, 0
%a = insertvalue { float, float } poison, float %x, 0
%b = insertvalue { float, float } %a, float %arg3, 1
ret { float, float } %b
}
@ -54,7 +54,7 @@ bb:
%f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float
%r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
%r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0
%r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
%r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
%r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
@ -86,7 +86,7 @@ bb:
define amdgpu_ps { float, <2 x float> } @ps_input_ena_pos_w(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
bb:
%f = bitcast <2 x i32> %arg8 to <2 x float>
%s = insertvalue { float, <2 x float> } undef, float %arg14, 0
%s = insertvalue { float, <2 x float> } poison, float %arg14, 0
%s1 = insertvalue { float, <2 x float> } %s, <2 x float> %f, 1
ret { float, <2 x float> } %s1
}
@ -112,7 +112,7 @@ bb:
%f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float
%r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
%r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0
%r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
%r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
%r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
@ -141,7 +141,7 @@ bb:
%f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float
%r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
%r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0
%r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
%r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
%r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
@ -170,7 +170,7 @@ bb:
%f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float
%r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
%r0 = insertvalue { float, float, float, float, float } poison, float %f0, 0
%r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
%r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
%r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
@ -185,7 +185,7 @@ bb:
define amdgpu_vs { i32, i32, i32 } @sgpr(ptr addrspace(4) inreg %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb:
%x = add i32 %arg2, 2
%a = insertvalue { i32, i32, i32 } undef, i32 %x, 0
%a = insertvalue { i32, i32, i32 } poison, i32 %x, 0
%b = insertvalue { i32, i32, i32 } %a, i32 %arg1, 1
%c = insertvalue { i32, i32, i32 } %a, i32 %arg2, 2
ret { i32, i32, i32 } %c
@ -218,7 +218,7 @@ bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
%v = fadd float %arg3, 1.000000e+00
%s = add i32 %arg2, 2
%a0 = insertvalue { float, i32, float, i32, i32 } undef, float %v, 0
%a0 = insertvalue { float, i32, float, i32, i32 } poison, float %v, 0
%a1 = insertvalue { float, i32, float, i32, i32 } %a0, i32 %s, 1
%a2 = insertvalue { float, i32, float, i32, i32 } %a1, float %arg3, 2
%a3 = insertvalue { float, i32, float, i32, i32 } %a2, i32 %arg1, 3

4
llvm/test/CodeGen/AMDGPU/scratch-simple.ll
View File

@ -334,7 +334,7 @@ define amdgpu_hs <{i32, i32, i32, float}> @hs_ir_uses_scratch_offset(i32 inreg,
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%f = fadd float %v1, %v2
%r1 = insertvalue <{i32, i32, i32, float}> undef, i32 %swo, 2
%r1 = insertvalue <{i32, i32, i32, float}> poison, i32 %swo, 2
%r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3
ret <{i32, i32, i32, float}> %r2
}
@ -389,7 +389,7 @@ define amdgpu_gs <{i32, i32, i32, float}> @gs_ir_uses_scratch_offset(i32 inreg,
%v1 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0xBFEA477C60000000, float 0xBFEBE5DC60000000, float 0xBFEC71C720000000, float 0xBFEBE5DC60000000, float 0xBFEA477C60000000, float 0xBFE7A693C0000000, float 0xBFE41CFEA0000000, float 0x3FDF9B13E0000000, float 0x3FDF9B1380000000, float 0x3FD5C53B80000000, float 0x3FD5C53B00000000, float 0x3FC6326AC0000000, float 0x3FC63269E0000000, float 0xBEE05CEB00000000, float 0xBEE086A320000000, float 0xBFC63269E0000000, float 0xBFC6326AC0000000, float 0xBFD5C53B80000000, float 0xBFD5C53B80000000, float 0xBFDF9B13E0000000, float 0xBFDF9B1460000000, float 0xBFE41CFE80000000, float 0x3FE7A693C0000000, float 0x3FEA477C20000000, float 0x3FEBE5DC40000000, float 0x3FEC71C6E0000000, float 0x3FEBE5DC40000000, float 0x3FEA477C20000000, float 0x3FE7A693C0000000, float 0xBFE41CFE80000000>, i32 %idx
%v2 = extractelement <81 x float> <float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float undef, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFEA0000000, float 0xBFE7A693C0000000, float 0x3FE7A693C0000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFEBE5DC40000000, float 0x3FEBE5DC40000000, float 0xBFEC71C720000000, float 0x3FEC71C6E0000000, float 0xBFEBE5DC60000000, float 0x3FEBE5DC40000000, float 0xBFEA477C20000000, float 0x3FEA477C20000000, float 0xBFE7A693C0000000, float 0x3FE7A69380000000, float 0xBFE41CFEA0000000, float 0xBFDF9B13E0000000, float 0xBFD5C53B80000000, float 0xBFC6326AC0000000, float 0x3EE0789320000000, float 0x3FC6326AC0000000, float 0x3FD5C53B80000000, float 0x3FDF9B13E0000000, float 0x3FE41CFE80000000>, i32 %idx
%f = fadd float %v1, %v2
%r1 = insertvalue <{i32, i32, i32, float}> undef, i32 %swo, 2
%r1 = insertvalue <{i32, i32, i32, float}> poison, i32 %swo, 2
%r2 = insertvalue <{i32, i32, i32, float}> %r1, float %f, 3
ret <{i32, i32, i32, float}> %r2
}

8
llvm/test/CodeGen/AMDGPU/skip-promote-alloca-vector-users.ll
View File

@ -15,22 +15,22 @@ entry:
; CHECK-LABEL: @test_insertvalue(
; CHECK: %alloca = alloca i16
; CHECK-NEXT: insertvalue { ptr addrspace(5) } undef, ptr addrspace(5) %alloca, 0
; CHECK-NEXT: insertvalue { ptr addrspace(5) } poison, ptr addrspace(5) %alloca, 0
define amdgpu_kernel void @test_insertvalue() #0 {
entry:
%alloca = alloca i16, align 4, addrspace(5)
%in = insertvalue { ptr addrspace(5) } undef, ptr addrspace(5) %alloca, 0
%in = insertvalue { ptr addrspace(5) } poison, ptr addrspace(5) %alloca, 0
store { ptr addrspace(5) } %in, ptr undef, align 4
ret void
}
; CHECK-LABEL: @test_insertvalue_array(
; CHECK: %alloca = alloca i16
; CHECK-NEXT: insertvalue [2 x ptr addrspace(5)] undef, ptr addrspace(5) %alloca, 0
; CHECK-NEXT: insertvalue [2 x ptr addrspace(5)] poison, ptr addrspace(5) %alloca, 0
define amdgpu_kernel void @test_insertvalue_array() #0 {
entry:
%alloca = alloca i16, align 4, addrspace(5)
%in = insertvalue [2 x ptr addrspace(5)] undef, ptr addrspace(5) %alloca, 0
%in = insertvalue [2 x ptr addrspace(5)] poison, ptr addrspace(5) %alloca, 0
store [2 x ptr addrspace(5)] %in, ptr undef, align 4
ret void
}

8
llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
View File

@ -74,11 +74,11 @@ ENDIF25: ; preds = %IF29, %main_body
%tmp75 = fmul float %clamp.i, %clamp.i
%tmp76 = fmul float %tmp75, %tmp75
%tmp77 = fadd float %tmp76, %tmp76
%tmp78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, float %tmp77, 11
%tmp79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp78, float undef, 12
%tmp80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp79, float undef, 13
%tmp78 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> poison, float %tmp77, 11
%tmp79 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp78, float poison, 12
%tmp80 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp79, float poison, 13
%tmp81 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp80, float %tmp25, 14
%tmp82 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp81, float undef, 15
%tmp82 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp81, float poison, 15
%tmp83 = insertvalue <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp82, float %arg21, 24
ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %tmp83