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[X86] LowerShift - use getConstant directly to create vector splat constants. NFC.

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This commit is contained in:
Simon Pilgrim 2024-12-17 17:57:50 +00:00
parent 7477b61b24
commit 5d4e4b3503
1 changed files with 3 additions and 5 deletions
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8
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -30224,8 +30224,7 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
// another. The construction of this mask will be constant folded.
// The mask for a logical right shift is nearly identical, the only
// difference is that the all ones mask is shifted right instead of left.
SDValue CstFullMask = DAG.getAllOnesConstant(dl, NarrowScalarVT);
SDValue SplatFullMask = DAG.getSplat(VT, dl, CstFullMask);
SDValue SplatFullMask = DAG.getAllOnesConstant(dl, VT);
SDValue Mask = DAG.getNode(LogicalOpc, dl, VT, SplatFullMask, Amt);
Mask = DAG.getBitcast(WideVT, Mask);
// Finally, we mask the shifted vector with the SWAR mask.
@ -30258,9 +30257,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
//
// This is equal to Masked - 2*SignBitMask which will correctly sign
// extend our result.
SDValue CstHighBit =
DAG.getConstant(1ULL << (EltSizeInBits - 1), dl, NarrowScalarVT);
SDValue SplatHighBit = DAG.getSplat(VT, dl, CstHighBit);
SDValue SplatHighBit =
DAG.getConstant(APInt::getSignMask(EltSizeInBits), dl, VT);
// This does not induce recursion, all operands are constants.
SDValue SignBitMask = DAG.getNode(LogicalOpc, dl, VT, SplatHighBit, Amt);
SDValue FlippedSignBit =