[Pipelines] Perform mergefunc after constmerge (#92498)
Constmerge can fold switch jump tables, possibly making functions identical again. It can help mergefunc. On the other hand, the opposite seems unlikely. Fixes https://github.com/llvm/llvm-project/issues/92201.
This commit is contained in:
YAMAMOTO Takashi
GitHub
parent
b52c512ff0
commit
5d79110959
@ -1527,10 +1527,6 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level,
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if (EnableIROutliner)
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MPM.addPass(IROutlinerPass());
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// Merge functions if requested.
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if (PTO.MergeFunctions)
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MPM.addPass(MergeFunctionsPass());
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// Now we need to do some global optimization transforms.
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// FIXME: It would seem like these should come first in the optimization
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// pipeline and maybe be the bottom of the canonicalization pipeline? Weird
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@ -1538,6 +1534,11 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level,
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MPM.addPass(GlobalDCEPass());
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MPM.addPass(ConstantMergePass());
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// Merge functions if requested. It has a better chance to merge functions
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// after ConstantMerge folded jump tables.
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if (PTO.MergeFunctions)
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MPM.addPass(MergeFunctionsPass());
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if (PTO.CallGraphProfile && !LTOPreLink)
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MPM.addPass(CGProfilePass(LTOPhase == ThinOrFullLTOPhase::FullLTOPostLink ||
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LTOPhase == ThinOrFullLTOPhase::ThinLTOPostLink));
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@ -281,9 +281,9 @@
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; CHECK-HOT-COLD-SPLIT-NEXT: Running pass: HotColdSplittingPass
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; CHECK-IR-OUTLINER-NEXT: Running pass: IROutlinerPass
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; CHECK-IR-OUTLINER-NEXT: Running analysis: IRSimilarityAnalysis
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; CHECK-MERGE-FUNCS-NEXT: Running pass: MergeFunctionsPass
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; CHECK-O-NEXT: Running pass: GlobalDCEPass
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; CHECK-O-NEXT: Running pass: ConstantMergePass
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; CHECK-MERGE-FUNCS-NEXT: Running pass: MergeFunctionsPass
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; CHECK-DEFAULT-NEXT: Running pass: CGProfilePass
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; CHECK-DEFAULT-NEXT: Running pass: RelLookupTableConverterPass
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; CHECK-LTO-NOT: Running pass: RelLookupTableConverterPass
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76
llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
Normal file
76
llvm/test/Transforms/PhaseOrdering/X86/merge-functions2.ll
Normal file
@ -0,0 +1,76 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx12.0.0"
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define i32 @f(i32 noundef %x) {
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; CHECK-LABEL: define range(i32 0, 2) i32 @f(
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; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8
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; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]]
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; CHECK: [[SWITCH_LOOKUP]]:
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; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64
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; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 [[TMP1]]
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; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
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; CHECK-NEXT: br label %[[SW_EPILOG]]
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; CHECK: [[SW_EPILOG]]:
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; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: ret i32 [[X_ADDR_0]]
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;
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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switch i32 %0, label %sw.default [
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i32 0, label %sw.bb
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i32 2, label %sw.bb
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i32 4, label %sw.bb
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i32 6, label %sw.bb
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i32 7, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
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store i32 1, ptr %x.addr, align 4
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br label %sw.epilog
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sw.default: ; preds = %entry
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store i32 0, ptr %x.addr, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.default, %sw.bb
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%1 = load i32, ptr %x.addr, align 4
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ret i32 %1
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}
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define i32 @g(i32 noundef %x) {
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; CHECK-LABEL: define range(i32 0, 2) i32 @g(
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; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] {
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; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]]
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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entry:
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%x.addr = alloca i32, align 4
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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switch i32 %0, label %sw.default [
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i32 0, label %sw.bb
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i32 2, label %sw.bb
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i32 4, label %sw.bb
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i32 6, label %sw.bb
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i32 7, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry, %entry, %entry
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store i32 1, ptr %x.addr, align 4
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br label %sw.epilog
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sw.default: ; preds = %entry
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store i32 0, ptr %x.addr, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %sw.default, %sw.bb
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%1 = load i32, ptr %x.addr, align 4
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ret i32 %1
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}
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59
llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
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59
llvm/test/Transforms/PhaseOrdering/X86/merge-functions3.ll
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@ -0,0 +1,59 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes="default<O3>" -enable-merge-functions -S < %s | FileCheck %s
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx12.0.0"
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@switch.table.f = private unnamed_addr constant [8 x i32] [i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 1], align 4
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@switch.table.g = private unnamed_addr constant [8 x i32] [i32 1, i32 0, i32 1, i32 0, i32 1, i32 0, i32 1, i32 1], align 4
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define range(i32 0, 2) i32 @f(i32 noundef %x) local_unnamed_addr {
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; CHECK-LABEL: define range(i32 0, 2) i32 @f(
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; CHECK-SAME: i32 noundef [[X:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X]], 8
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; CHECK-NEXT: br i1 [[TMP0]], label %[[SWITCH_LOOKUP:.*]], label %[[SW_EPILOG:.*]]
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; CHECK: [[SWITCH_LOOKUP]]:
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; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[X]] to i64
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; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 [[TMP1]]
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; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, ptr [[SWITCH_GEP]], align 4
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; CHECK-NEXT: br label %[[SW_EPILOG]]
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; CHECK: [[SW_EPILOG]]:
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; CHECK-NEXT: [[X_ADDR_0:%.*]] = phi i32 [ [[SWITCH_LOAD]], %[[SWITCH_LOOKUP]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: ret i32 [[X_ADDR_0]]
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;
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entry:
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%0 = icmp ult i32 %x, 8
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br i1 %0, label %switch.lookup, label %sw.epilog
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switch.lookup: ; preds = %entry
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%1 = zext nneg i32 %x to i64
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%switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.f, i64 0, i64 %1
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%switch.load = load i32, ptr %switch.gep, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %switch.lookup
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%x.addr.0 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %entry ]
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ret i32 %x.addr.0
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}
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define range(i32 0, 2) i32 @g(i32 noundef %x) local_unnamed_addr {
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; CHECK-LABEL: define range(i32 0, 2) i32 @g(
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; CHECK-SAME: i32 noundef [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0]] {
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; CHECK-NEXT: [[TMP2:%.*]] = tail call range(i32 0, 2) i32 @f(i32 noundef [[TMP0]]) #[[ATTR0]]
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; CHECK-NEXT: ret i32 [[TMP2]]
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;
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entry:
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%0 = icmp ult i32 %x, 8
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br i1 %0, label %switch.lookup, label %sw.epilog
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switch.lookup: ; preds = %entry
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%1 = zext nneg i32 %x to i64
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%switch.gep = getelementptr inbounds [8 x i32], ptr @switch.table.g, i64 0, i64 %1
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%switch.load = load i32, ptr %switch.gep, align 4
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br label %sw.epilog
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sw.epilog: ; preds = %entry, %switch.lookup
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%x.addr.0 = phi i32 [ %switch.load, %switch.lookup ], [ 0, %entry ]
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ret i32 %x.addr.0
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}
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