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Move ExpandMemCmp and MergeIcmp to the middle end (#77370)

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Moving these into the middle-end pipeline will allow for additional
optimization of the expansion result, such as CSE of redundant loads
(c.f. https://godbolt.org/z/bEna4Md9r). For now, we conservatively place
the passes at the end of the middle-end pipeline, so we mostly don't
benefit from additional optimizations yet. The pipeline position will be
moved in a future change.

This builds on work done by legrosbuffle in
https://reviews.llvm.org/D60318.

---------

Co-authored-by: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
This commit is contained in:
Gabriel Baraldi 2026-04-02 04:57:00 -03:00 committed by GitHub
parent a599a06e7c
commit 5e0a06b34d
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
74 changed files with 262 additions and 378 deletions
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3
llvm/include/llvm/CodeGen/Passes.h
View File

@ -553,9 +553,6 @@ LLVM_ABI FunctionPass *createReplaceWithVeclibLegacyPass();
// Expands large div/rem and floating-point instructions.
LLVM_ABI FunctionPass *createExpandIRInstsPass(CodeGenOptLevel);
// This pass expands memcmp() to load/stores.
LLVM_ABI FunctionPass *createExpandMemCmpLegacyPass();
/// Creates Break False Dependencies pass. \see BreakFalseDeps.cpp
LLVM_ABI FunctionPass *createBreakFalseDeps();

2
llvm/include/llvm/InitializePasses.h
View File

@ -114,7 +114,6 @@ LLVM_ABI void initializeEarlyTailDuplicateLegacyPass(PassRegistry &);
LLVM_ABI void initializeEdgeBundlesWrapperLegacyPass(PassRegistry &);
LLVM_ABI void initializeEHContGuardTargetsPass(PassRegistry &);
LLVM_ABI void initializeExpandIRInstsLegacyPassPass(PassRegistry &);
LLVM_ABI void initializeExpandMemCmpLegacyPassPass(PassRegistry &);
LLVM_ABI void initializeExpandPostRALegacyPass(PassRegistry &);
LLVM_ABI void initializeExpandReductionsPass(PassRegistry &);
LLVM_ABI void initializeExpandVariadicsPass(PassRegistry &);
@ -234,7 +233,6 @@ LLVM_ABI void initializeMachineUniformityAnalysisPassPass(PassRegistry &);
LLVM_ABI void initializeMachineVerifierLegacyPassPass(PassRegistry &);
LLVM_ABI void initializeMemoryDependenceWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeMemorySSAWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeMergeICmpsLegacyPassPass(PassRegistry &);
LLVM_ABI void initializeModuleSummaryIndexWrapperPassPass(PassRegistry &);
LLVM_ABI void initializeModuloScheduleTestPass(PassRegistry &);
LLVM_ABI void initializeNaryReassociateLegacyPassPass(PassRegistry &);

2
llvm/include/llvm/LinkAllPasses.h
View File

@ -127,8 +127,6 @@ struct ForcePassLinking {
(void)llvm::createEarlyCSEPass();
(void)llvm::createGVNPass();
(void)llvm::createPostDomTree();
(void)llvm::createMergeICmpsLegacyPass();
(void)llvm::createExpandMemCmpLegacyPass();
std::string buf;
llvm::raw_string_ostream os(buf);
(void)llvm::createPrintModulePass(os);

11
llvm/include/llvm/Passes/CodeGenPassBuilder.h
View File

@ -29,7 +29,6 @@
#include "llvm/CodeGen/DetectDeadLanes.h"
#include "llvm/CodeGen/DwarfEHPrepare.h"
#include "llvm/CodeGen/ExpandIRInsts.h"
#include "llvm/CodeGen/ExpandMemCmp.h"
#include "llvm/CodeGen/ExpandPostRAPseudos.h"
#include "llvm/CodeGen/ExpandReductions.h"
#include "llvm/CodeGen/FEntryInserter.h"
@ -736,16 +735,6 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addIRPasses(
PMW);
}
if (getOptLevel() != CodeGenOptLevel::None) {
// The MergeICmpsPass tries to create memcmp calls by grouping sequences of
// loads and compares. ExpandMemCmpPass then tries to expand those calls
// into optimally-sized loads and compares. The transforms are enabled by a
// target lowering hook.
if (!Opt.DisableMergeICmps)
addFunctionPass(MergeICmpsPass(), PMW);
addFunctionPass(ExpandMemCmpPass(), PMW);
}
// Run GC lowering passes for builtin collectors
// TODO: add a pass insertion point here
addFunctionPass(GCLoweringPass(), PMW);

1
llvm/include/llvm/Target/CGPassBuilderOption.h
View File

@ -66,7 +66,6 @@ struct CGPassBuilderOption {
bool DisableLSR = false;
bool DisableCGP = false;
bool DisableMergeICmps = false;
bool DisablePartialLibcallInlining = false;
bool DisableConstantHoisting = false;
bool DisableSelectOptimize = true;

5
llvm/include/llvm/Transforms/Scalar.h
View File

@ -145,11 +145,6 @@ LLVM_ABI FunctionPass *createSinkingPass();
LLVM_ABI Pass *createLowerAtomicPass();
//===----------------------------------------------------------------------===//
//
// MergeICmps - Merge integer comparison chains into a memcmp
//
LLVM_ABI Pass *createMergeICmpsLegacyPass();
//===----------------------------------------------------------------------===//
//
// InferAddressSpaces - Modify users of addrspacecast instructions with values

8
llvm/include/llvm/CodeGen/ExpandMemCmp.h → llvm/include/llvm/Transforms/Scalar/ExpandMemCmp.h
View File

@ -6,15 +6,13 @@
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_EXPANDMEMCMP_H
#define LLVM_CODEGEN_EXPANDMEMCMP_H
#ifndef LLVM_TRANSFORMS_SCALAR_EXPANDMEMCMP_H
#define LLVM_TRANSFORMS_SCALAR_EXPANDMEMCMP_H
#include "llvm/IR/PassManager.h"
namespace llvm {
class TargetMachine;
class ExpandMemCmpPass : public PassInfoMixin<ExpandMemCmpPass> {
public:
PreservedAnalyses run(Function &F, FunctionAnalysisManager &FAM);
@ -22,4 +20,4 @@ public:
} // namespace llvm
#endif // LLVM_CODEGEN_EXPANDMEMCMP_H
#endif // LLVM_TRANSFORMS_SCALAR_EXPANDMEMCMP_H

1
llvm/lib/CodeGen/CMakeLists.txt
View File

@ -57,7 +57,6 @@ add_llvm_component_library(LLVMCodeGen
EHContGuardTargets.cpp
ExecutionDomainFix.cpp
ExpandIRInsts.cpp
ExpandMemCmp.cpp
ExpandPostRAPseudos.cpp
ExpandReductions.cpp
ExpandVectorPredication.cpp

1
llvm/lib/CodeGen/CodeGen.cpp
View File

@ -44,7 +44,6 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeEarlyMachineLICMPass(Registry);
initializeEarlyTailDuplicateLegacyPass(Registry);
initializeExpandIRInstsLegacyPassPass(Registry);
initializeExpandMemCmpLegacyPassPass(Registry);
initializeExpandPostRALegacyPass(Registry);
initializeExpandReductionsPass(Registry);
initializeFEntryInserterLegacyPass(Registry);

12
llvm/lib/CodeGen/TargetPassConfig.cpp
View File

@ -110,9 +110,6 @@ static cl::opt<bool> EnableImplicitNullChecks(
"enable-implicit-null-checks",
cl::desc("Fold null checks into faulting memory operations"),
cl::init(false), cl::Hidden);
static cl::opt<bool> DisableMergeICmps("disable-mergeicmps",
cl::desc("Disable MergeICmps Pass"),
cl::init(false), cl::Hidden);
static cl::opt<bool>
PrintISelInput("print-isel-input", cl::Hidden,
cl::desc("Print LLVM IR input to isel pass"));
@ -520,7 +517,6 @@ CGPassBuilderOption llvm::getCGPassBuilderOption() {
SET_BOOLEAN_OPTION(EnableImplicitNullChecks)
SET_BOOLEAN_OPTION(EnableMachineOutliner)
SET_BOOLEAN_OPTION(MISchedPostRA)
SET_BOOLEAN_OPTION(DisableMergeICmps)
SET_BOOLEAN_OPTION(DisableLSR)
SET_BOOLEAN_OPTION(DisableConstantHoisting)
SET_BOOLEAN_OPTION(DisableCGP)
@ -863,14 +859,6 @@ void TargetPassConfig::addIRPasses() {
if (EnableLoopTermFold)
addPass(createLoopTermFoldPass());
}
// The MergeICmpsPass tries to create memcmp calls by grouping sequences of
// loads and compares. ExpandMemCmpPass then tries to expand those calls
// into optimally-sized loads and compares. The transforms are enabled by a
// target lowering hook.
if (!DisableMergeICmps)
addPass(createMergeICmpsLegacyPass());
addPass(createExpandMemCmpLegacyPass());
}
// Run GC lowering passes for builtin collectors

2
llvm/lib/Passes/PassBuilder.cpp
View File

@ -91,7 +91,6 @@
#include "llvm/CodeGen/EarlyIfConversion.h"
#include "llvm/CodeGen/EdgeBundles.h"
#include "llvm/CodeGen/ExpandIRInsts.h"
#include "llvm/CodeGen/ExpandMemCmp.h"
#include "llvm/CodeGen/ExpandPostRAPseudos.h"
#include "llvm/CodeGen/ExpandReductions.h"
#include "llvm/CodeGen/FEntryInserter.h"
@ -281,6 +280,7 @@
#include "llvm/Transforms/Scalar/DivRemPairs.h"
#include "llvm/Transforms/Scalar/DropUnnecessaryAssumes.h"
#include "llvm/Transforms/Scalar/EarlyCSE.h"
#include "llvm/Transforms/Scalar/ExpandMemCmp.h"
#include "llvm/Transforms/Scalar/FlattenCFG.h"
#include "llvm/Transforms/Scalar/Float2Int.h"
#include "llvm/Transforms/Scalar/GVN.h"

12
llvm/lib/Passes/PassBuilderPipelines.cpp
View File

@ -97,6 +97,7 @@
#include "llvm/Transforms/Scalar/DivRemPairs.h"
#include "llvm/Transforms/Scalar/DropUnnecessaryAssumes.h"
#include "llvm/Transforms/Scalar/EarlyCSE.h"
#include "llvm/Transforms/Scalar/ExpandMemCmp.h"
#include "llvm/Transforms/Scalar/Float2Int.h"
#include "llvm/Transforms/Scalar/GVN.h"
#include "llvm/Transforms/Scalar/IndVarSimplify.h"
@ -124,6 +125,7 @@
#include "llvm/Transforms/Scalar/LowerExpectIntrinsic.h"
#include "llvm/Transforms/Scalar/LowerMatrixIntrinsics.h"
#include "llvm/Transforms/Scalar/MemCpyOptimizer.h"
#include "llvm/Transforms/Scalar/MergeICmps.h"
#include "llvm/Transforms/Scalar/MergedLoadStoreMotion.h"
#include "llvm/Transforms/Scalar/NewGVN.h"
#include "llvm/Transforms/Scalar/Reassociate.h"
@ -268,6 +270,10 @@ static cl::opt<bool>
EnableMatrix("enable-matrix", cl::init(false), cl::Hidden,
cl::desc("Enable lowering of the matrix intrinsics"));
static cl::opt<bool> EnableMergeICmps(
"enable-mergeicmps", cl::init(true), cl::Hidden,
cl::desc("Enable MergeICmps pass in the optimization pipeline"));
static cl::opt<bool> EnableConstraintElimination(
"enable-constraint-elimination", cl::init(true), cl::Hidden,
cl::desc(
@ -1605,6 +1611,12 @@ PassBuilder::buildModuleOptimizationPipeline(OptimizationLevel Level,
// flattening of blocks.
OptimizePM.addPass(DivRemPairsPass());
// Merge adjacent icmps into memcmp, then expand memcmp to loads/compares.
// TODO: move this furter up so that it can be optimized by GVN, etc.
if (EnableMergeICmps)
OptimizePM.addPass(MergeICmpsPass());
OptimizePM.addPass(ExpandMemCmpPass());
// Try to annotate calls that were created during optimization.
OptimizePM.addPass(
TailCallElimPass(/*UpdateFunctionEntryCount=*/isInstrumentedPGOUse()));

1
llvm/lib/Transforms/Scalar/CMakeLists.txt
View File

@ -13,6 +13,7 @@ add_llvm_component_library(LLVMScalarOpts
DivRemPairs.cpp
DropUnnecessaryAssumes.cpp
EarlyCSE.cpp
ExpandMemCmp.cpp
FlattenCFGPass.cpp
Float2Int.cpp
GuardWidening.cpp

68
llvm/lib/CodeGen/ExpandMemCmp.cpp → llvm/lib/Transforms/Scalar/ExpandMemCmp.cpp
View File

@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/ExpandMemCmp.h"
#include "llvm/Transforms/Scalar/ExpandMemCmp.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/DomTreeUpdater.h"
@ -20,13 +20,10 @@
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/ProfDataUtils.h"
#include "llvm/InitializePasses.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
#include "llvm/Transforms/Utils/SizeOpts.h"
@ -892,46 +889,6 @@ static PreservedAnalyses runImpl(Function &F, const TargetLibraryInfo *TLI,
ProfileSummaryInfo *PSI,
BlockFrequencyInfo *BFI, DominatorTree *DT);
class ExpandMemCmpLegacyPass : public FunctionPass {
public:
static char ID;
ExpandMemCmpLegacyPass() : FunctionPass(ID) {}
bool runOnFunction(Function &F) override {
if (skipFunction(F)) return false;
auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
if (!TPC) {
return false;
}
const TargetLibraryInfo *TLI =
&getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
const TargetTransformInfo *TTI =
&getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
auto *PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
auto *BFI = (PSI && PSI->hasProfileSummary()) ?
&getAnalysis<LazyBlockFrequencyInfoPass>().getBFI() :
nullptr;
DominatorTree *DT = nullptr;
if (auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>())
DT = &DTWP->getDomTree();
auto PA = runImpl(F, TLI, TTI, PSI, BFI, DT);
return !PA.areAllPreserved();
}
private:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetLibraryInfoWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
AU.addPreserved<DominatorTreeWrapperPass>();
LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
FunctionPass::getAnalysisUsage(AU);
}
};
bool runOnBlock(BasicBlock &BB, const TargetLibraryInfo *TLI,
const TargetTransformInfo *TTI, const DataLayout &DL,
ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI,
@ -985,6 +942,14 @@ PreservedAnalyses runImpl(Function &F, const TargetLibraryInfo *TLI,
PreservedAnalyses ExpandMemCmpPass::run(Function &F,
FunctionAnalysisManager &FAM) {
// Don't expand memcmp in sanitized functions — sanitizers intercept memcmp
// calls to check for memory errors, and expanding would bypass that.
if (F.hasFnAttribute(Attribute::SanitizeAddress) ||
F.hasFnAttribute(Attribute::SanitizeMemory) ||
F.hasFnAttribute(Attribute::SanitizeThread) ||
F.hasFnAttribute(Attribute::SanitizeHWAddress))
return PreservedAnalyses::all();
const auto &TLI = FAM.getResult<TargetLibraryAnalysis>(F);
const auto &TTI = FAM.getResult<TargetIRAnalysis>(F);
auto *PSI = FAM.getResult<ModuleAnalysisManagerFunctionProxy>(F)
@ -996,18 +961,3 @@ PreservedAnalyses ExpandMemCmpPass::run(Function &F,
return runImpl(F, &TLI, &TTI, PSI, BFI, DT);
}
char ExpandMemCmpLegacyPass::ID = 0;
INITIALIZE_PASS_BEGIN(ExpandMemCmpLegacyPass, DEBUG_TYPE,
"Expand memcmp() to load/stores", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass)
INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
INITIALIZE_PASS_END(ExpandMemCmpLegacyPass, DEBUG_TYPE,
"Expand memcmp() to load/stores", false, false)
FunctionPass *llvm::createExpandMemCmpLegacyPass() {
return new ExpandMemCmpLegacyPass();
}

50
llvm/lib/Transforms/Scalar/MergeICmps.cpp
View File

@ -43,8 +43,8 @@
#include "llvm/Transforms/Scalar/MergeICmps.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/DomTreeUpdater.h"
#include "llvm/Analysis/GlobalsModRef.h"
#include "llvm/Analysis/Loads.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/Analysis/TargetTransformInfo.h"
@ -53,9 +53,6 @@
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/ProfDataUtils.h"
#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/BuildLibCalls.h"
#include <algorithm>
@ -888,7 +885,7 @@ static bool processPhi(PHINode &Phi, const TargetLibraryInfo &TLI,
static bool runImpl(Function &F, const TargetLibraryInfo &TLI,
const TargetTransformInfo &TTI, AliasAnalysis &AA,
DominatorTree *DT) {
LLVM_DEBUG(dbgs() << "MergeICmpsLegacyPass: " << F.getName() << "\n");
LLVM_DEBUG(dbgs() << "MergeICmpsPass: " << F.getName() << "\n");
// We only try merging comparisons if the target wants to expand memcmp later.
// The rationale is to avoid turning small chains into memcmp calls.
@ -913,49 +910,6 @@ static bool runImpl(Function &F, const TargetLibraryInfo &TLI,
return MadeChange;
}
namespace {
class MergeICmpsLegacyPass : public FunctionPass {
public:
static char ID;
MergeICmpsLegacyPass() : FunctionPass(ID) {
initializeMergeICmpsLegacyPassPass(*PassRegistry::getPassRegistry());
}
bool runOnFunction(Function &F) override {
if (skipFunction(F)) return false;
const auto &TLI = getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(F);
const auto &TTI = getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
// MergeICmps does not need the DominatorTree, but we update it if it's
// already available.
auto *DTWP = getAnalysisIfAvailable<DominatorTreeWrapperPass>();
auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
return runImpl(F, TLI, TTI, AA, DTWP ? &DTWP->getDomTree() : nullptr);
}
private:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<TargetLibraryInfoWrapperPass>();
AU.addRequired<TargetTransformInfoWrapperPass>();
AU.addRequired<AAResultsWrapperPass>();
AU.addPreserved<GlobalsAAWrapperPass>();
AU.addPreserved<DominatorTreeWrapperPass>();
}
};
} // namespace
char MergeICmpsLegacyPass::ID = 0;
INITIALIZE_PASS_BEGIN(MergeICmpsLegacyPass, "mergeicmps",
"Merge contiguous icmps into a memcmp", false, false)
INITIALIZE_PASS_DEPENDENCY(TargetLibraryInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(MergeICmpsLegacyPass, "mergeicmps",
"Merge contiguous icmps into a memcmp", false, false)
Pass *llvm::createMergeICmpsLegacyPass() { return new MergeICmpsLegacyPass(); }
PreservedAnalyses MergeICmpsPass::run(Function &F,
FunctionAnalysisManager &AM) {
auto &TLI = AM.getResult<TargetLibraryAnalysis>(F);

1
llvm/lib/Transforms/Scalar/Scalar.cpp
View File

@ -34,7 +34,6 @@ void llvm::initializeScalarOpts(PassRegistry &Registry) {
initializeLoopTermFoldPass(Registry);
initializeLoopUnrollPass(Registry);
initializeLowerAtomicLegacyPassPass(Registry);
initializeMergeICmpsLegacyPassPass(Registry);
initializeNaryReassociateLegacyPassPass(Registry);
initializePartiallyInlineLibCallsLegacyPassPass(Registry);
initializeDSELegacyPassPass(Registry);

7
llvm/test/CodeGen/AArch64/O3-pipeline.ll
View File

@ -49,13 +49,6 @@
; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
; CHECK-NEXT: Induction Variable Users
; CHECK-NEXT: Loop Strength Reduction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Merge contiguous icmps into a memcmp
; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
; CHECK-NEXT: Expand memcmp() to load/stores
; CHECK-NEXT: Lower Garbage Collection Instructions
; CHECK-NEXT: Shadow Stack GC Lowering
; CHECK-NEXT: Remove unreachable blocks from the CFG

4
llvm/test/CodeGen/AArch64/bcmp-inline-small.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECKN
; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu -mattr=strict-align | FileCheck %s --check-prefix=CHECKS
; RUN: opt -passes=expand-memcmp -mtriple=aarch64-linux-gnu -S < %s | llc -O2 -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECKN
; RUN: opt -passes=expand-memcmp -mtriple=aarch64-linux-gnu -mattr=strict-align -S < %s | llc -O2 -mtriple=aarch64-linux-gnu -mattr=strict-align | FileCheck %s --check-prefix=CHECKS
declare i32 @bcmp(ptr, ptr, i64) nounwind readonly
declare i32 @memcmp(ptr, ptr, i64) nounwind readonly

2
llvm/test/CodeGen/AArch64/bcmp.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O2 < %s -mtriple=aarch64-linux-gnu | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=aarch64-linux-gnu -S < %s | llc -O2 -mtriple=aarch64-linux-gnu | FileCheck %s
declare i32 @bcmp(ptr, ptr, i64)

2
llvm/test/CodeGen/AArch64/dag-combine-setcc.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=aarch64-none-linux-gnu -mattr=+neon -S < %s | llc -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
define i1 @combine_setcc_eq_vecreduce_or_v8i1(<8 x i8> %a) {
; CHECK-LABEL: combine_setcc_eq_vecreduce_or_v8i1:

10
llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=aarch64-linux-gnu -S < %s | llc -mtriple=aarch64-linux-gnu | FileCheck %s
; One dimensional loop with load that can be hoisted outside of loop
; for (int i = 0; i < N; ++i)
@ -29,8 +29,8 @@ for.body: ; preds = %entry, %for.body
%i.06 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
%sum.05 = phi i64 [ %spec.select, %for.body ], [ 0, %entry ]
%arrayidx = getelementptr inbounds ptr, ptr %a, i64 %i.06
%0 = load ptr, ptr %arrayidx, align 8
%bcmp = tail call i32 @bcmp(ptr %0, ptr %b, i64 4)
%ptr = load ptr, ptr %arrayidx, align 8
%bcmp = tail call i32 @bcmp(ptr %ptr, ptr %b, i64 4)
%tobool = icmp eq i32 %bcmp, 0
%add = zext i1 %tobool to i64
%spec.select = add i64 %sum.05, %add
@ -387,8 +387,8 @@ for.body: ; preds = %for.body.preheader,
%indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
%sum.05 = phi i32 [ 0, %for.body.preheader ], [ %spec.select, %for.body ]
%arrayidx = getelementptr inbounds ptr, ptr %a, i64 %indvars.iv
%0 = load ptr, ptr %arrayidx, align 8
%bcmp = tail call i32 @bcmp(ptr %0, ptr %b, i64 4)
%ptr = load ptr, ptr %arrayidx, align 8
%bcmp = tail call i32 @bcmp(ptr %ptr, ptr %b, i64 4)
%tobool.not = icmp eq i32 %bcmp, 0
%add = zext i1 %tobool.not to i32
%spec.select = add nuw nsw i32 %sum.05, %add

2
llvm/test/CodeGen/AArch64/memcmp.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=aarch64-unknown-unknown -S < %s | llc -mtriple=aarch64-unknown-unknown | FileCheck %s
@.str = private constant [513 x i8] c"01234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678901\00", align 1

4
llvm/test/CodeGen/AMDGPU/llc-pipeline-npm.ll
View File

@ -127,8 +127,6 @@
; GCN-O2-NEXT: verify
; GCN-O2-NEXT: loop(canon-freeze
; GCN-O2-NEXT: loop-reduce)
; GCN-O2-NEXT: mergeicmps
; GCN-O2-NEXT: expand-memcmp
; GCN-O2-NEXT: unreachableblockelim
; GCN-O2-NEXT: consthoist
; GCN-O2-NEXT: replace-with-veclib
@ -298,8 +296,6 @@
; GCN-O3-NEXT: verify
; GCN-O3-NEXT: loop(canon-freeze
; GCN-O3-NEXT: loop-reduce)
; GCN-O3-NEXT: mergeicmps
; GCN-O3-NEXT: expand-memcmp
; GCN-O3-NEXT: unreachableblockelim
; GCN-O3-NEXT: consthoist
; GCN-O3-NEXT: replace-with-veclib

28
llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
View File

@ -225,13 +225,6 @@
; GCN-O1-NEXT: Canonicalize Freeze Instructions in Loops
; GCN-O1-NEXT: Induction Variable Users
; GCN-O1-NEXT: Loop Strength Reduction
; GCN-O1-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O1-NEXT: Function Alias Analysis Results
; GCN-O1-NEXT: Merge contiguous icmps into a memcmp
; GCN-O1-NEXT: Natural Loop Information
; GCN-O1-NEXT: Lazy Branch Probability Analysis
; GCN-O1-NEXT: Lazy Block Frequency Analysis
; GCN-O1-NEXT: Expand memcmp() to load/stores
; GCN-O1-NEXT: Remove unreachable blocks from the CFG
; GCN-O1-NEXT: Natural Loop Information
; GCN-O1-NEXT: Post-Dominator Tree Construction
@ -535,13 +528,6 @@
; GCN-O1-OPTS-NEXT: Canonicalize Freeze Instructions in Loops
; GCN-O1-OPTS-NEXT: Induction Variable Users
; GCN-O1-OPTS-NEXT: Loop Strength Reduction
; GCN-O1-OPTS-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O1-OPTS-NEXT: Function Alias Analysis Results
; GCN-O1-OPTS-NEXT: Merge contiguous icmps into a memcmp
; GCN-O1-OPTS-NEXT: Natural Loop Information
; GCN-O1-OPTS-NEXT: Lazy Branch Probability Analysis
; GCN-O1-OPTS-NEXT: Lazy Block Frequency Analysis
; GCN-O1-OPTS-NEXT: Expand memcmp() to load/stores
; GCN-O1-OPTS-NEXT: Remove unreachable blocks from the CFG
; GCN-O1-OPTS-NEXT: Natural Loop Information
; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction
@ -862,13 +848,6 @@
; GCN-O2-NEXT: Canonicalize Freeze Instructions in Loops
; GCN-O2-NEXT: Induction Variable Users
; GCN-O2-NEXT: Loop Strength Reduction
; GCN-O2-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O2-NEXT: Function Alias Analysis Results
; GCN-O2-NEXT: Merge contiguous icmps into a memcmp
; GCN-O2-NEXT: Natural Loop Information
; GCN-O2-NEXT: Lazy Branch Probability Analysis
; GCN-O2-NEXT: Lazy Block Frequency Analysis
; GCN-O2-NEXT: Expand memcmp() to load/stores
; GCN-O2-NEXT: Remove unreachable blocks from the CFG
; GCN-O2-NEXT: Natural Loop Information
; GCN-O2-NEXT: Post-Dominator Tree Construction
@ -1197,13 +1176,6 @@
; GCN-O3-NEXT: Canonicalize Freeze Instructions in Loops
; GCN-O3-NEXT: Induction Variable Users
; GCN-O3-NEXT: Loop Strength Reduction
; GCN-O3-NEXT: Basic Alias Analysis (stateless AA impl)
; GCN-O3-NEXT: Function Alias Analysis Results
; GCN-O3-NEXT: Merge contiguous icmps into a memcmp
; GCN-O3-NEXT: Natural Loop Information
; GCN-O3-NEXT: Lazy Branch Probability Analysis
; GCN-O3-NEXT: Lazy Block Frequency Analysis
; GCN-O3-NEXT: Expand memcmp() to load/stores
; GCN-O3-NEXT: Remove unreachable blocks from the CFG
; GCN-O3-NEXT: Natural Loop Information
; GCN-O3-NEXT: Post-Dominator Tree Construction

7
llvm/test/CodeGen/ARM/O3-pipeline.ll
View File

@ -25,13 +25,6 @@
; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
; CHECK-NEXT: Induction Variable Users
; CHECK-NEXT: Loop Strength Reduction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Merge contiguous icmps into a memcmp
; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
; CHECK-NEXT: Expand memcmp() to load/stores
; CHECK-NEXT: Lower Garbage Collection Instructions
; CHECK-NEXT: Shadow Stack GC Lowering
; CHECK-NEXT: Remove unreachable blocks from the CFG

4
llvm/test/CodeGen/BPF/memcmp.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mtriple=bpfel < %s | FileCheck %s
; RUN: llc -mtriple=bpfel -mcpu=v3 < %s | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=bpfel -S < %s | llc -mtriple=bpfel | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=bpfel -mcpu=v3 -S < %s | llc -mtriple=bpfel -mcpu=v3 | FileCheck %s
;
; Source code:
; /* set aligned 4 to minimize the number of loads */

6
llvm/test/CodeGen/Generic/llc-start-stop.ll
View File

@ -19,15 +19,15 @@
; STOP-BEFORE-NOT: Loop Strength Reduction
; RUN: llc < %s -debug-pass=Structure -start-after=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=START-AFTER
; START-AFTER: -aa -mergeicmps
; START-AFTER: -gc-lowering
; START-AFTER: FunctionPass Manager
; START-AFTER-NEXT: Dominator Tree Construction
; START-AFTER-NEXT: Lower Garbage Collection Instructions
; RUN: llc < %s -debug-pass=Structure -start-before=loop-reduce -o /dev/null 2>&1 | FileCheck %s -check-prefix=START-BEFORE
; START-BEFORE: -machine-branch-prob -regalloc-evict -regalloc-priority -domtree
; START-BEFORE: FunctionPass Manager
; START-BEFORE: Loop Strength Reduction
; START-BEFORE-NEXT: {{Loop Terminator Folding|Basic Alias Analysis \(stateless AA impl\)}}
; START-BEFORE-NEXT: {{Loop Terminator Folding|Lower Garbage Collection Instructions}}
; RUN: not llc < %s -start-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-START-BEFORE
; RUN: not llc < %s -stop-before=nonexistent -o /dev/null 2>&1 | FileCheck %s -check-prefix=NONEXISTENT-STOP-BEFORE

8
llvm/test/CodeGen/LoongArch/expandmemcmp-optsize.ll
View File

@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: sed 's/iGRLen/i32/g' %s | llc --mtriple=loongarch32 --mattr=+ual \
; RUN: sed 's/iGRLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=loongarch32 -mattr=+ual -S | llc --mtriple=loongarch32 --mattr=+ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA32,LA32-UAL
; RUN: sed 's/iGRLen/i64/g' %s | llc --mtriple=loongarch64 --mattr=+ual \
; RUN: sed 's/iGRLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=loongarch64 -mattr=+ual -S | llc --mtriple=loongarch64 --mattr=+ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA64,LA64-UAL
; RUN: sed 's/iGRLen/i32/g' %s | llc --mtriple=loongarch32 --mattr=-ual \
; RUN: sed 's/iGRLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=loongarch32 -mattr=-ual -S | llc --mtriple=loongarch32 --mattr=-ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA32,LA32-NUAL
; RUN: sed 's/iGRLen/i64/g' %s | llc --mtriple=loongarch64 --mattr=-ual \
; RUN: sed 's/iGRLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=loongarch64 -mattr=-ual -S | llc --mtriple=loongarch64 --mattr=-ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA64,LA64-NUAL
declare signext i32 @bcmp(ptr, ptr, iGRLen) nounwind readonly

8
llvm/test/CodeGen/LoongArch/expandmemcmp.ll
View File

@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: sed 's/iGRLen/i32/g' %s | llc --mtriple=loongarch32 --mattr=+ual \
; RUN: sed 's/iGRLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=loongarch32 -mattr=+ual -S | llc --mtriple=loongarch32 --mattr=+ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA32,LA32-UAL
; RUN: sed 's/iGRLen/i64/g' %s | llc --mtriple=loongarch64 --mattr=+ual \
; RUN: sed 's/iGRLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=loongarch64 -mattr=+ual -S | llc --mtriple=loongarch64 --mattr=+ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA64,LA64-UAL
; RUN: sed 's/iGRLen/i32/g' %s | llc --mtriple=loongarch32 --mattr=-ual \
; RUN: sed 's/iGRLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=loongarch32 -mattr=-ual -S | llc --mtriple=loongarch32 --mattr=-ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA32,LA32-NUAL
; RUN: sed 's/iGRLen/i64/g' %s | llc --mtriple=loongarch64 --mattr=-ual \
; RUN: sed 's/iGRLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=loongarch64 -mattr=-ual -S | llc --mtriple=loongarch64 --mattr=-ual \
; RUN: | FileCheck %s --check-prefixes=CHECK,LA64,LA64-NUAL
declare signext i32 @bcmp(ptr, ptr, iGRLen) nounwind readonly

2
llvm/test/CodeGen/LoongArch/memcmp.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 -mattr=+d < %s | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=loongarch64 -mattr=+d -S < %s | llc --mtriple=loongarch64 -mattr=+d | FileCheck %s
;; Before getSelectionDAGInfo() interface hooks were defined DAGBuilder
;; would crash.

9
llvm/test/CodeGen/LoongArch/opt-pipeline.ll
View File

@ -25,8 +25,8 @@
; LAXX-NEXT: Library Function Lowering Analysis
; LAXX-NEXT: Type-Based Alias Analysis
; LAXX-NEXT: Scoped NoAlias Alias Analysis
; LAXX-NEXT: Profile summary info
; LAXX-NEXT: Create Garbage Collector Module Metadata
; LAXX-NEXT: Profile summary info
; LAXX-NEXT: Machine Branch Probability Analysis
; LAXX-NEXT: Default Regalloc Eviction Advisor
; LAXX-NEXT: Default Regalloc Priority Advisor
@ -50,13 +50,6 @@
; LAXX-NEXT: Canonicalize Freeze Instructions in Loops
; LAXX-NEXT: Induction Variable Users
; LAXX-NEXT: Loop Strength Reduction
; LAXX-NEXT: Basic Alias Analysis (stateless AA impl)
; LAXX-NEXT: Function Alias Analysis Results
; LAXX-NEXT: Merge contiguous icmps into a memcmp
; LAXX-NEXT: Natural Loop Information
; LAXX-NEXT: Lazy Branch Probability Analysis
; LAXX-NEXT: Lazy Block Frequency Analysis
; LAXX-NEXT: Expand memcmp() to load/stores
; LAXX-NEXT: Lower Garbage Collection Instructions
; LAXX-NEXT: Shadow Stack GC Lowering
; LAXX-NEXT: Remove unreachable blocks from the CFG

7
llvm/test/CodeGen/M68k/pipeline.ll
View File

@ -19,13 +19,6 @@
; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
; CHECK-NEXT: Induction Variable Users
; CHECK-NEXT: Loop Strength Reduction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Merge contiguous icmps into a memcmp
; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
; CHECK-NEXT: Expand memcmp() to load/stores
; CHECK-NEXT: Lower Garbage Collection Instructions
; CHECK-NEXT: Shadow Stack GC Lowering
; CHECK-NEXT: Remove unreachable blocks from the CFG

9
llvm/test/CodeGen/PowerPC/O3-pipeline.ll
View File

@ -13,8 +13,8 @@
; CHECK-NEXT: Library Function Lowering Analysis
; CHECK-NEXT: Type-Based Alias Analysis
; CHECK-NEXT: Scoped NoAlias Alias Analysis
; CHECK-NEXT: Profile summary info
; CHECK-NEXT: Create Garbage Collector Module Metadata
; CHECK-NEXT: Profile summary info
; CHECK-NEXT: Machine Branch Probability Analysis
; CHECK-NEXT: Default Regalloc Eviction Advisor
; CHECK-NEXT: Default Regalloc Priority Advisor
@ -51,13 +51,6 @@
; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
; CHECK-NEXT: Induction Variable Users
; CHECK-NEXT: Loop Strength Reduction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Merge contiguous icmps into a memcmp
; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
; CHECK-NEXT: Expand memcmp() to load/stores
; CHECK-NEXT: Lower Garbage Collection Instructions
; CHECK-NEXT: Shadow Stack GC Lowering
; CHECK-NEXT: Remove unreachable blocks from the CFG

2
llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr8 < %s | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -S < %s | llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr8 | FileCheck %s
target datalayout = "e-m:e-i64:64-n32:64"
target triple = "powerpc64le-unknown-linux-gnu"

2
llvm/test/CodeGen/PowerPC/memcmp-mergeexpand.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=PPC64LE
; RUN: opt -passes=mergeicmps,expand-memcmp -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr8 -S < %s | llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux | FileCheck %s -check-prefix=PPC64LE
; This tests interaction between MergeICmp and expand-memcmp.

2
llvm/test/CodeGen/PowerPC/memcmp.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64le-unknown-gnu-linux -mcpu=pwr8 -S < %s | llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux | FileCheck %s -check-prefix=CHECK
define signext i32 @memcmp8(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
; CHECK-LABEL: memcmp8:

8
llvm/test/CodeGen/PowerPC/memcmp32_fixsize.ll
View File

@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpc-ibm-aix -mcpu=pwr8 -S < %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix | \
; RUN: FileCheck %s --check-prefix=CHECK-AIX32-P8
; RUN: llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpc-ibm-aix -mcpu=pwr10 -S < %s | llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpc-ibm-aix | \
; RUN: FileCheck %s --check-prefix=CHECK-AIX32-P10
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpcle-unknown-linux-gnu < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr8 -S < %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpcle-unknown-linux-gnu | \
; RUN: FileCheck %s --check-prefix=CHECK-LINUX32-P8
; RUN: llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpcle-unknown-linux-gnu < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr10 -S < %s | llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpcle-unknown-linux-gnu | \
; RUN: FileCheck %s --check-prefix=CHECK-LINUX32-P10
define dso_local signext range(i32 0, 2) i32 @cmpeq16(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b) {

8
llvm/test/CodeGen/PowerPC/memcmp64_fixsize.ll
View File

@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64-ibm-aix -mcpu=pwr8 -S < %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix | \
; RUN: FileCheck %s --check-prefix=CHECK-AIX64-32-P8
; RUN: llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64-ibm-aix -mcpu=pwr10 -S < %s | llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpc64-ibm-aix | \
; RUN: FileCheck %s --check-prefix=CHECK-AIX64-32-P10
; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -S < %s | llc -mcpu=pwr8 -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu | \
; RUN: FileCheck %s --check-prefix=CHECK-LINUX64-P8
; RUN: llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s | \
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr10 -S < %s | llc -mcpu=pwr10 -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu | \
; RUN: FileCheck %s --check-prefix=CHECK-LINUX64-P10
define dso_local signext range(i32 0, 2) i32 @cmpeq16(ptr noundef readonly captures(none) %a, ptr noundef readonly captures(none) %b) {

4
llvm/test/CodeGen/PowerPC/memcmpIR.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -o - -mtriple=powerpc64le-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s
; RUN: llc -o - -mtriple=powerpc64-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s --check-prefix=CHECK-BE
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64le-unknown-gnu-linux -S < %s | llc -o - -mtriple=powerpc64le-unknown-gnu-linux -stop-after codegenprepare | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=powerpc64-unknown-gnu-linux -S < %s | llc -o - -mtriple=powerpc64-unknown-gnu-linux -stop-after codegenprepare | FileCheck %s --check-prefix=CHECK-BE
define signext i32 @test1(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
entry:

7
llvm/test/CodeGen/RISCV/O3-pipeline.ll
View File

@ -53,13 +53,6 @@
; CHECK-NEXT: Induction Variable Users
; CHECK-NEXT: Loop Strength Reduction
; CHECK-NEXT: Loop Terminator Folding
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Merge contiguous icmps into a memcmp
; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
; CHECK-NEXT: Expand memcmp() to load/stores
; CHECK-NEXT: Lower Garbage Collection Instructions
; CHECK-NEXT: Shadow Stack GC Lowering
; CHECK-NEXT: Remove unreachable blocks from the CFG

32
llvm/test/CodeGen/RISCV/memcmp-optsize.ll
View File

@ -1,35 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -S | llc -mtriple=riscv32 -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -S | llc -mtriple=riscv64 -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbb -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbb -S | llc -mtriple=riscv32 -mattr=+zbb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32-ZBB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbb -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbb -S | llc -mtriple=riscv64 -mattr=+zbb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64-ZBB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbkb -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbkb -S | llc -mtriple=riscv32 -mattr=+zbkb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32-ZBKB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbkb -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbkb -S | llc -mtriple=riscv64 -mattr=+zbkb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64-ZBKB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+v -S | llc -mtriple=riscv32 -mattr=+v -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32-V
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+v -S | llc -mtriple=riscv64 -mattr=+v -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64-V
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+unaligned-scalar-mem -S | llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+unaligned-scalar-mem -S | llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbb,+unaligned-scalar-mem -S | llc -mtriple=riscv32 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32-ZBB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbb,+unaligned-scalar-mem -S | llc -mtriple=riscv64 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64-ZBB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbkb,+unaligned-scalar-mem -S | llc -mtriple=riscv32 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32-ZBKB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbkb,+unaligned-scalar-mem -S | llc -mtriple=riscv64 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64-ZBKB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -S | llc -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32-V
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -S | llc -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64-V
declare i32 @bcmp(ptr, ptr, iXLen) nounwind readonly

32
llvm/test/CodeGen/RISCV/memcmp.ll
View File

@ -1,35 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -S | llc -mtriple=riscv32 -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -S | llc -mtriple=riscv64 -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbb -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbb -S | llc -mtriple=riscv32 -mattr=+zbb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32-ZBB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbb -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbb -S | llc -mtriple=riscv64 -mattr=+zbb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64-ZBB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbkb -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbkb -S | llc -mtriple=riscv32 -mattr=+zbkb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32-ZBKB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbkb -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbkb -S | llc -mtriple=riscv64 -mattr=+zbkb -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64-ZBKB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+v -S | llc -mtriple=riscv32 -mattr=+v -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-ALIGNED,CHECK-ALIGNED-RV32-V
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+v -S | llc -mtriple=riscv64 -mattr=+v -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-ALIGNED,CHECK-ALIGNED-RV64-V
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+unaligned-scalar-mem -S | llc -mtriple=riscv32 -mattr=+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+unaligned-scalar-mem -S | llc -mtriple=riscv64 -mattr=+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbb,+unaligned-scalar-mem -S | llc -mtriple=riscv32 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32-ZBB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbb,+unaligned-scalar-mem -S | llc -mtriple=riscv64 -mattr=+zbb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64-ZBB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+zbkb,+unaligned-scalar-mem -S | llc -mtriple=riscv32 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32-ZBKB
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+zbkb,+unaligned-scalar-mem -S | llc -mtriple=riscv64 -mattr=+zbkb,+unaligned-scalar-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64-ZBKB
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: sed 's/iXLen/i32/g' %s | opt -passes=expand-memcmp -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -S | llc -mtriple=riscv32 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV32,CHECK-UNALIGNED,CHECK-UNALIGNED-RV32-V
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: sed 's/iXLen/i64/g' %s | opt -passes=expand-memcmp -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -S | llc -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem,+unaligned-vector-mem -O2 \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64,CHECK-UNALIGNED,CHECK-UNALIGNED-RV64-V
declare i32 @bcmp(ptr, ptr, iXLen) nounwind readonly

2
llvm/test/CodeGen/RISCV/pr186969.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64-unknown-elf -mattr=+unaligned-scalar-mem -O1 | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=riscv64-unknown-elf -mattr=+unaligned-scalar-mem -S < %s | llc -mtriple=riscv64-unknown-elf -mattr=+unaligned-scalar-mem -O1 | FileCheck %s
@.str.45 = constant [4 x i8] c" 16\00"
@.str.47 = constant [4 x i8] c"-0E\00"

9
llvm/test/CodeGen/SPIRV/llc-pipeline.ll
View File

@ -102,8 +102,8 @@
; SPIRV-Opt-NEXT:Library Function Lowering Analysis
; SPIRV-Opt-NEXT:Type-Based Alias Analysis
; SPIRV-Opt-NEXT:Scoped NoAlias Alias Analysis
; SPIRV-Opt-NEXT:Profile summary info
; SPIRV-Opt-NEXT:Create Garbage Collector Module Metadata
; SPIRV-Opt-NEXT:Profile summary info
; SPIRV-Opt-NEXT:Machine Branch Probability Analysis
; SPIRV-Opt-NEXT: ModulePass Manager
; SPIRV-Opt-NEXT: FunctionPass Manager
@ -124,13 +124,6 @@
; SPIRV-Opt-NEXT: Canonicalize Freeze Instructions in Loops
; SPIRV-Opt-NEXT: Induction Variable Users
; SPIRV-Opt-NEXT: Loop Strength Reduction
; SPIRV-Opt-NEXT: Basic Alias Analysis (stateless AA impl)
; SPIRV-Opt-NEXT: Function Alias Analysis Results
; SPIRV-Opt-NEXT: Merge contiguous icmps into a memcmp
; SPIRV-Opt-NEXT: Natural Loop Information
; SPIRV-Opt-NEXT: Lazy Branch Probability Analysis
; SPIRV-Opt-NEXT: Lazy Block Frequency Analysis
; SPIRV-Opt-NEXT: Expand memcmp() to load/stores
; SPIRV-Opt-NEXT: Lower Garbage Collection Instructions
; SPIRV-Opt-NEXT: Shadow Stack GC Lowering
; SPIRV-Opt-NEXT: Remove unreachable blocks from the CFG

2
llvm/test/CodeGen/WebAssembly/memcmp-expand.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=wasm32-unknown-unknown -mattr=+simd128 -S < %s | llc -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
target triple = "wasm32-unknown-unknown"

2
llvm/test/CodeGen/WebAssembly/simd-memcmp.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -verify-machineinstrs -mattr=+simd128 | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=wasm32 -mattr=+simd128 -S < %s | llc -verify-machineinstrs -mattr=+simd128 | FileCheck %s
target datalayout = "e-m:e-p:32:32-p10:8:8-p20:8:8-i64:64-i128:128-n32:64-S128-ni:1:10:20"
target triple = "wasm32"

2
llvm/test/CodeGen/WebAssembly/simd-setcc.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=wasm32-unknown-unknown -mattr=+simd128 -S < %s | llc -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 | FileCheck %s
target triple = "wasm32-unknown-unknown"

4
llvm/test/CodeGen/X86/llc-pipeline-npm.ll
View File

@ -88,8 +88,6 @@
; O2-NEXT: verify
; O2-NEXT: loop(canon-freeze
; O2-NEXT: loop-reduce)
; O2-NEXT: mergeicmps
; O2-NEXT: expand-memcmp
; O2-NEXT: gc-lowering)
; O2-NEXT: shadow-stack-gc-lowering
; O2-NEXT: function(unreachableblockelim
@ -276,8 +274,6 @@
; O3-WINDOWS-NEXT: verify
; O3-WINDOWS-NEXT: loop(canon-freeze
; O3-WINDOWS-NEXT: loop-reduce)
; O3-WINDOWS-NEXT: mergeicmps
; O3-WINDOWS-NEXT: expand-memcmp
; O3-WINDOWS-NEXT: gc-lowering)
; O3-WINDOWS-NEXT: shadow-stack-gc-lowering
; O3-WINDOWS-NEXT: function(unreachableblockelim

2
llvm/test/CodeGen/X86/memcmp-constant.ll
View File

@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -S < %s | llc -mtriple=x86_64-unknown-unknown | FileCheck %s
@.str1 = private constant [4 x i8] c"\00\00\00\00", align 1
@.str2 = private constant [4 x i8] c"\ff\ff\ff\ff", align 1

4
llvm/test/CodeGen/X86/memcmp-mergeexpand.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
; RUN: opt -passes=mergeicmps,expand-memcmp -mtriple=i686-unknown-unknown -S < %s | llc -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
; RUN: opt -passes=mergeicmps,expand-memcmp -mtriple=x86_64-unknown-unknown -S < %s | llc -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
; This tests interaction between MergeICmp and ExpandMemCmp.

8
llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
View File

@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: This is a copy of llvm/test/CodeGen/X86/memcmp.ll with more load pairs. Please keep it that way.
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=X86,X86-SSE1
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=X86,X86-SSE41
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=cmov -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=X86,X86-SSE1
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse2 -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse4.1 -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=X86,X86-SSE41
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

20
llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
View File

@ -1,15 +1,15 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: This is a copy of llvm/test/CodeGen/X86/memcmp.ll with more load pairs. Please keep it that way.
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE2
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE41
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw,+prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw,-prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512BW
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512F
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX2
; RUN: llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX512F
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=sse4.1 -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE41
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx2 -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512bw,+prefer-256-bit -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx512bw,+prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512bw,-prefer-256-bit -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx512bw,-prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512BW
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,-prefer-mask-registers -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,-prefer-mask-registers -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512F
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,+prefer-mask-registers -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,+prefer-mask-registers -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -S < %s | llc -max-loads-per-memcmp=4 -memcmp-num-loads-per-block=4 -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX512F
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

4
llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=cmov -S < %s | llc -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse2 -S < %s | llc -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

6
llvm/test/CodeGen/X86/memcmp-optsize.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -S < %s | llc -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx2 -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

4
llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=cmov -S < %s | llc -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse2 -S < %s | llc -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

6
llvm/test/CodeGen/X86/memcmp-pgso.ll
View File

@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -S < %s | llc -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx2 -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

8
llvm/test/CodeGen/X86/memcmp-x32.ll
View File

@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=X86,X86-SSE1
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=X86,X86-SSE41
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=cmov -S < %s | llc -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse -S < %s | llc -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=X86,X86-SSE1
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse2 -S < %s | llc -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=i686-unknown-unknown -mattr=+sse4.1 -S < %s | llc -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=X86,X86-SSE41
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

20
llvm/test/CodeGen/X86/memcmp.ll
View File

@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE41
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw,+prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw,-prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512BW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX512F
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -S < %s | llc -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=sse4.1 -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefixes=X64,X64-SSE,X64-SSE41
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx2 -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512bw,+prefer-256-bit -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx512bw,+prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512bw,-prefer-256-bit -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx512bw,-prefer-256-bit | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512BW
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,-prefer-mask-registers -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,-prefer-mask-registers -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,-prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX512,X64-AVX512F
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,+prefer-mask-registers -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx512f,+prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX2
; RUN: opt -passes=expand-memcmp -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,+prefer-mask-registers -S < %s | llc -mtriple=x86_64-unknown-unknown -mattr=avx512f,-prefer-256-bit,+prefer-mask-registers | FileCheck %s --check-prefixes=X64,X64-MIC-AVX,X64-MIC-AVX512F
; This tests codegen time inlining/optimization of memcmp
; rdar://6480398

9
llvm/test/CodeGen/X86/opt-pipeline.ll
View File

@ -21,8 +21,8 @@
; CHECK-NEXT: Library Function Lowering Analysis
; CHECK-NEXT: Type-Based Alias Analysis
; CHECK-NEXT: Scoped NoAlias Alias Analysis
; CHECK-NEXT: Profile summary info
; CHECK-NEXT: Create Garbage Collector Module Metadata
; CHECK-NEXT: Profile summary info
; CHECK-NEXT: Machine Branch Probability Analysis
; CHECK-NEXT: Default Regalloc Eviction Advisor
; CHECK-NEXT: Default Regalloc Priority Advisor
@ -48,13 +48,6 @@
; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
; CHECK-NEXT: Induction Variable Users
; CHECK-NEXT: Loop Strength Reduction
; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
; CHECK-NEXT: Function Alias Analysis Results
; CHECK-NEXT: Merge contiguous icmps into a memcmp
; CHECK-NEXT: Natural Loop Information
; CHECK-NEXT: Lazy Branch Probability Analysis
; CHECK-NEXT: Lazy Block Frequency Analysis
; CHECK-NEXT: Expand memcmp() to load/stores
; CHECK-NEXT: Lower Garbage Collection Instructions
; CHECK-NEXT: Shadow Stack GC Lowering
; CHECK-NEXT: Remove unreachable blocks from the CFG

2
llvm/test/Other/new-pm-defaults.ll
View File

@ -282,6 +282,8 @@
; CHECK-O-NEXT: Running pass: LoopSinkPass
; CHECK-O-NEXT: Running pass: InstSimplifyPass
; CHECK-O-NEXT: Running pass: DivRemPairsPass
; CHECK-O-NEXT: Running pass: MergeICmpsPass
; CHECK-O-NEXT: Running pass: ExpandMemCmpPass
; CHECK-O-NEXT: Running pass: TailCallElimPass
; CHECK-O-NEXT: Running pass: SimplifyCFGPass
; CHECK-DEFAULT-NEXT: Running pass: AllocToken

2
llvm/test/Other/new-pm-thinlto-postlink-defaults.ll
View File

@ -200,6 +200,8 @@
; CHECK-POSTLINK-O-NEXT: Running pass: LoopSinkPass
; CHECK-POSTLINK-O-NEXT: Running pass: InstSimplifyPass
; CHECK-POSTLINK-O-NEXT: Running pass: DivRemPairsPass
; CHECK-POSTLINK-O-NEXT: Running pass: MergeICmpsPass
; CHECK-POSTLINK-O-NEXT: Running pass: ExpandMemCmpPass
; CHECK-POSTLINK-O-NEXT: Running pass: TailCallElimPass
; CHECK-POSTLINK-O-NEXT: Running pass: SimplifyCFGPass
; CHECK-POSTLINK-O-NEXT: Running pass: AllocTokenPass

2
llvm/test/Other/new-pm-thinlto-postlink-pgo-defaults.ll
View File

@ -185,6 +185,8 @@
; CHECK-O-NEXT: Running pass: LoopSinkPass
; CHECK-O-NEXT: Running pass: InstSimplifyPass
; CHECK-O-NEXT: Running pass: DivRemPairsPass
; CHECK-O-NEXT: Running pass: MergeICmpsPass
; CHECK-O-NEXT: Running pass: ExpandMemCmpPass
; CHECK-O-NEXT: Running pass: TailCallElimPass
; CHECK-O-NEXT: Running pass: SimplifyCFGPass
; CHECK-O-NEXT: Running pass: AllocTokenPass

2
llvm/test/Other/new-pm-thinlto-postlink-samplepgo-defaults.ll
View File

@ -194,6 +194,8 @@
; CHECK-O-NEXT: Running pass: LoopSinkPass
; CHECK-O-NEXT: Running pass: InstSimplifyPass
; CHECK-O-NEXT: Running pass: DivRemPairsPass
; CHECK-O-NEXT: Running pass: MergeICmpsPass
; CHECK-O-NEXT: Running pass: ExpandMemCmpPass
; CHECK-O-NEXT: Running pass: TailCallElimPass
; CHECK-O-NEXT: Running pass: SimplifyCFGPass
; CHECK-O-NEXT: Running pass: AllocTokenPass

1
llvm/test/Transforms/ExpandMemCmp/AArch64/memcmp.ll
View File

@ -1,5 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals --version 3
; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=aarch64-unknown-unknown < %s | FileCheck %s
declare i32 @memcmp(ptr nocapture, ptr nocapture, i64)

3
llvm/test/Transforms/ExpandMemCmp/X86/bcmp.ll
View File

@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64
declare i32 @bcmp(ptr nocapture, ptr nocapture, i64)

3
llvm/test/Transforms/ExpandMemCmp/X86/memcmp-x32.ll
View File

@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
; RUN: opt -S -expand-memcmp -mtriple=i686-unknown-unknown -data-layout=e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128 < %s | FileCheck %s --check-prefix=X32
; RUN: opt -S -passes=expand-memcmp -mtriple=i686-unknown-unknown -data-layout=e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128 < %s | FileCheck %s --check-prefix=X32
; RUN: opt -S -passes=expand-memcmp -mtriple=i686-unknown-unknown -data-layout=e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128 < %s | FileCheck %s --check-prefix=X32
declare i32 @memcmp(ptr nocapture, ptr nocapture, i32)

6
llvm/test/Transforms/ExpandMemCmp/X86/memcmp.ll
View File

@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_1LD
; RUN: opt -S -expand-memcmp -memcmp-num-loads-per-block=2 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_2LD
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_1LD
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=2 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_2LD
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=1 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_1LD
; RUN: opt -S -passes=expand-memcmp -memcmp-num-loads-per-block=2 -mtriple=x86_64-unknown-unknown -data-layout=e-m:o-i64:64-f80:128-n8:16:32:64-S128 < %s | FileCheck %s --check-prefix=X64 --check-prefix=X64_2LD
declare i32 @memcmp(ptr nocapture, ptr nocapture, i64)

61
llvm/test/Transforms/ExpandMemCmp/X86/sanitizer-skip.ll Normal file
View File

@ -0,0 +1,61 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -passes=expand-memcmp -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
;
; Verify that ExpandMemCmp does not expand memcmp calls in functions with
; sanitizer attributes, so sanitizer interceptors can catch memory errors.
declare i32 @memcmp(ptr nocapture, ptr nocapture, i64)
define i32 @cmp_asan(ptr nocapture readonly %x, ptr nocapture readonly %y) sanitize_address {
; CHECK-LABEL: define i32 @cmp_asan(
; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @memcmp(ptr [[X]], ptr [[Y]], i64 4)
; CHECK-NEXT: ret i32 [[CALL]]
;
%call = tail call i32 @memcmp(ptr %x, ptr %y, i64 4)
ret i32 %call
}
define i32 @cmp_msan(ptr nocapture readonly %x, ptr nocapture readonly %y) sanitize_memory {
; CHECK-LABEL: define i32 @cmp_msan(
; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @memcmp(ptr [[X]], ptr [[Y]], i64 4)
; CHECK-NEXT: ret i32 [[CALL]]
;
%call = tail call i32 @memcmp(ptr %x, ptr %y, i64 4)
ret i32 %call
}
define i32 @cmp_tsan(ptr nocapture readonly %x, ptr nocapture readonly %y) sanitize_thread {
; CHECK-LABEL: define i32 @cmp_tsan(
; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]]) #[[ATTR2:[0-9]+]] {
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @memcmp(ptr [[X]], ptr [[Y]], i64 4)
; CHECK-NEXT: ret i32 [[CALL]]
;
%call = tail call i32 @memcmp(ptr %x, ptr %y, i64 4)
ret i32 %call
}
define i32 @cmp_hwasan(ptr nocapture readonly %x, ptr nocapture readonly %y) sanitize_hwaddress {
; CHECK-LABEL: define i32 @cmp_hwasan(
; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]]) #[[ATTR3:[0-9]+]] {
; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @memcmp(ptr [[X]], ptr [[Y]], i64 4)
; CHECK-NEXT: ret i32 [[CALL]]
;
%call = tail call i32 @memcmp(ptr %x, ptr %y, i64 4)
ret i32 %call
}
define i32 @cmp_no_sanitizer(ptr nocapture readonly %x, ptr nocapture readonly %y) {
; CHECK-LABEL: define i32 @cmp_no_sanitizer(
; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Y]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP1]])
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP2]])
; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.ucmp.i32.i32(i32 [[TMP3]], i32 [[TMP4]])
; CHECK-NEXT: ret i32 [[TMP5]]
;
%call = tail call i32 @memcmp(ptr %x, ptr %y, i64 4)
ret i32 %call
}

37
llvm/test/Transforms/PhaseOrdering/X86/expand-memcmp-middle-end.ll Normal file
View File

@ -0,0 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -S -O2 -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
;
; Verify that expanding memcmp in the middle-end enables further IR
; optimizations. When two memcmp calls share a common pointer operand and
; constant size, the expanded loads can be CSE'd / GVN'd away.
declare i32 @memcmp(ptr nocapture, ptr nocapture, i64)
; FIXME: The redundant load of %x is not eliminated yet because ExpandMemCmp
; runs late in the pipeline. Moving it earlier should allow GVN to CSE the loads.
; Two memcmp calls with a shared first argument. After expansion in the
; middle-end, further IR optimizations should be able to optimize the expanded code.
define i1 @redundant_memcmp_loads(ptr nocapture readonly %x, ptr nocapture readonly %y, ptr nocapture readonly %z) {
; CHECK-LABEL: define i1 @redundant_memcmp_loads(
; CHECK-SAME: ptr readonly captures(none) [[X:%.*]], ptr readonly captures(none) [[Y:%.*]], ptr readonly captures(none) [[Z:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[X]], align 1
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[Y]], align 1
; CHECK-NEXT: [[TMP3:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP1]])
; CHECK-NEXT: [[TMP4:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP2]])
; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.ucmp.i32.i32(i32 [[TMP3]], i32 [[TMP4]])
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[X]], align 1
; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[Z]], align 1
; CHECK-NEXT: [[TMP8:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP6]])
; CHECK-NEXT: [[TMP9:%.*]] = tail call i32 @llvm.bswap.i32(i32 [[TMP7]])
; CHECK-NEXT: [[TMP10:%.*]] = tail call i32 @llvm.ucmp.i32.i32(i32 [[TMP8]], i32 [[TMP9]])
; CHECK-NEXT: [[TMP11:%.*]] = or i32 [[TMP10]], [[TMP5]]
; CHECK-NEXT: [[RESULT:%.*]] = icmp eq i32 [[TMP11]], 0
; CHECK-NEXT: ret i1 [[RESULT]]
;
%cmp1 = call i32 @memcmp(ptr %x, ptr %y, i64 4)
%eq1 = icmp eq i32 %cmp1, 0
%cmp2 = call i32 @memcmp(ptr %x, ptr %z, i64 4)
%eq2 = icmp eq i32 %cmp2, 0
%result = and i1 %eq1, %eq2
ret i1 %result
}

2
llvm/test/tools/llc/new-pm/option-conflict.ll
View File

@ -1,3 +1,3 @@
; RUN: not llc -mtriple=x86_64-pc-linux-gnu -passes=foo -start-before=mergeicmps -stop-after=gc-lowering -filetype=null %s 2>&1 | FileCheck %s
; RUN: not llc -mtriple=x86_64-pc-linux-gnu -passes=foo -start-before=gc-lowering -stop-after=gc-lowering -filetype=null %s 2>&1 | FileCheck %s
; CHECK: error: --passes cannot be used with start-before and stop-after.

8
llvm/test/tools/llc/new-pm/start-stop.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -filetype=null %s | FileCheck --match-full-lines %s --check-prefix=NULL
; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=mergeicmps -stop-after=gc-lowering -o /dev/null %s | FileCheck --match-full-lines %s --check-prefix=OBJ
; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=gc-lowering -stop-after=gc-lowering -filetype=null %s | FileCheck --match-full-lines %s --check-prefix=NULL
; RUN: llc -mtriple=x86_64-pc-linux-gnu -enable-new-pm -print-pipeline-passes -start-before=gc-lowering -stop-after=gc-lowering -o /dev/null %s | FileCheck --match-full-lines %s --check-prefix=OBJ
; NULL: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,require<runtime-libcall-info>,require<libcall-lowering-info>,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify)
; OBJ: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,require<runtime-libcall-info>,require<libcall-lowering-info>,function(verify,mergeicmps,expand-memcmp,gc-lowering,verify),PrintMIRPreparePass,function(machine-function(print),free-machine-function)
; NULL: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,require<runtime-libcall-info>,require<libcall-lowering-info>,function(verify,gc-lowering,verify)
; OBJ: require<MachineModuleAnalysis>,require<profile-summary>,require<collector-metadata>,require<runtime-libcall-info>,require<libcall-lowering-info>,function(verify,gc-lowering,verify),PrintMIRPreparePass,function(machine-function(print),free-machine-function)

1
llvm/tools/opt/optdriver.cpp
View File

@ -422,7 +422,6 @@ optMain(int argc, char **argv,
// For codegen passes, only passes that do IR to IR transformation are
// supported.
initializeExpandIRInstsLegacyPassPass(Registry);
initializeExpandMemCmpLegacyPassPass(Registry);
initializeScalarizeMaskedMemIntrinLegacyPassPass(Registry);
initializeSelectOptimizePass(Registry);
initializeInlineAsmPreparePass(Registry);

1
llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
View File

@ -57,7 +57,6 @@ static_library("CodeGen") {
"EdgeBundles.cpp",
"ExecutionDomainFix.cpp",
"ExpandIRInsts.cpp",
"ExpandMemCmp.cpp",
"ExpandPostRAPseudos.cpp",
"ExpandReductions.cpp",
"ExpandVectorPredication.cpp",

1
llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
View File

@ -24,6 +24,7 @@ static_library("Scalar") {
"DivRemPairs.cpp",
"DropUnnecessaryAssumes.cpp",
"EarlyCSE.cpp",
"ExpandMemCmp.cpp",
"FlattenCFGPass.cpp",
"Float2Int.cpp",
"GVN.cpp",