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[TableGen][Target] Add documentation to Constraints. (#85951)

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This patch adds some basic documentation for `Constraints`, along with
some "see also" pointers for backend writers to learn more.
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Jason Eckhardt 2024-03-20 12:56:49 -05:00 committed by GitHub
parent 5ea152033e
commit 5e6bb1fb88
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1 changed files with 14 additions and 1 deletions
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15
llvm/include/llvm/Target/Target.td
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@ -697,7 +697,20 @@ class Instruction : InstructionEncoding {
// Scheduling information from TargetSchedule.td.
list<SchedReadWrite> SchedRW;
string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
/// Support for operand constraints. There are currently two kinds:
/// "$src = $dst"
/// Ensures that the operands are allocated to the same register.
///
/// "@earlyclobber $rd"
/// Ensures that LLVM will not use the same register for any inputs (other
/// than an input tied to this output).
///
/// See also:
/// - MC/MCInstrDesc.h:OperandConstraint::{TIED_TO, EARLY_CLOBBER}.
/// - CodeGen/MachineOperand.h:MachineOperand::{TiedTo, IsEarlyClobber}.
/// - The LLVM IR specification: Section `Output constraints` in the
/// discussion of inline assembly constraint strings.
string Constraints = "";
/// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
/// be encoded into the output machineinstr.