[AMDGPU] update LDS block size for gfx1250 (#167614)
LDS block size should be 2048 bytes (512 dwords) based on current spec.
This commit is contained in:
Changpeng Fang
GitHub
parent
0f0cf84dba
commit
5f38ae4a77
@ -5896,7 +5896,7 @@ The fields used by CP for code objects before V3 also match those specified in
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GFX950
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roundup(lds-size / (320 * 4))
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GFX125*
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roundup(lds-size / (256 * 4))
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roundup(lds-size / (512 * 4))
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24 1 bit ENABLE_EXCEPTION_IEEE_754_FP Wavefront starts execution
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_INVALID_OPERATION with specified exceptions
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@ -1186,21 +1186,20 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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// Make clamp modifier on NaN input returns 0.
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ProgInfo.DX10Clamp = Mode.DX10Clamp;
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unsigned LDSAlignShift;
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if (STM.getFeatureBits().test(FeatureAddressableLocalMemorySize327680)) {
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// LDS is allocated in 256 dword blocks.
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LDSAlignShift = 10;
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} else if (STM.getFeatureBits().test(
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FeatureAddressableLocalMemorySize163840)) {
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// LDS is allocated in 320 dword blocks.
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unsigned LDSAlignShift = 8;
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switch (getLdsDwGranularity(STM)) {
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case 512:
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case 320:
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LDSAlignShift = 11;
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} else if (STM.getFeatureBits().test(
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FeatureAddressableLocalMemorySize65536)) {
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// LDS is allocated in 128 dword blocks.
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break;
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case 128:
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LDSAlignShift = 9;
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} else {
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// LDS is allocated in 64 dword blocks.
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break;
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case 64:
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LDSAlignShift = 8;
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break;
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default:
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llvm_unreachable("invald LDS block size");
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}
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ProgInfo.SGPRSpill = MFI->getNumSpilledSGPRs();
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@ -3565,8 +3565,15 @@ bool isDPALU_DPP(const MCInstrDesc &OpDesc, const MCInstrInfo &MII,
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}
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unsigned getLdsDwGranularity(const MCSubtargetInfo &ST) {
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return ST.hasFeature(AMDGPU::FeatureAddressableLocalMemorySize327680) ? 256
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: 128;
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if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize32768))
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return 64;
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if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize65536))
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return 128;
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if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize163840))
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return 320;
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if (ST.getFeatureBits().test(FeatureAddressableLocalMemorySize327680))
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return 512;
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return 64; // In sync with getAddressableLocalMemorySize
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}
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bool isPackedFP32Inst(unsigned Opc) {
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@ -31,10 +31,10 @@
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; GFX1200-MESA: .long 45100
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; GFX1200-MESA-NEXT: .long 1024
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; GFX1250-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x200
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; GFX1250-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x100
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; GFX1250-MESA: .long 45100
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; GFX1250-MESA-NEXT: .long 512
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; GFX1250-MESA-NEXT: .long 256
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@lds = internal addrspace(3) global [4096 x i8] poison
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@ -41,7 +41,7 @@ define amdgpu_kernel void @test_lds_i32(i32 %val) {
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; GCN-LABEL: test_lds_array_i8:
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; GCN: .amdhsa_group_segment_fixed_size 327680
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; GCN: ; LDSByteSize: 327680 bytes/workgroup
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; MESA: granulated_lds_size = 320
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; MESA: granulated_lds_size = 160
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define amdgpu_kernel void @test_lds_array_i8() {
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%gep = getelementptr inbounds [327679 x i8], ptr addrspace(3) @lds.array.i8, i32 0, i32 5
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%val = load i8, ptr addrspace(3) %gep
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@ -52,7 +52,7 @@ define amdgpu_kernel void @test_lds_array_i8() {
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; GCN-LABEL: test_lds_array_i16:
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; GCN: .amdhsa_group_segment_fixed_size 327680
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; GCN: ; LDSByteSize: 327680 bytes/workgroup
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; MESA: granulated_lds_size = 320
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; MESA: granulated_lds_size = 160
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define amdgpu_kernel void @test_lds_array_i16() {
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%gep = getelementptr inbounds [163839 x i16], ptr addrspace(3) @lds.array.i16, i32 0, i32 10
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%val = load i16, ptr addrspace(3) %gep
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@ -63,7 +63,7 @@ define amdgpu_kernel void @test_lds_array_i16() {
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; GCN-LABEL: test_lds_array_i32:
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; GCN: .amdhsa_group_segment_fixed_size 327680
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; GCN: ; LDSByteSize: 327680 bytes/workgroup
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; MESA: granulated_lds_size = 320
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; MESA: granulated_lds_size = 160
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define amdgpu_kernel void @test_lds_array_i32() {
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%gep = getelementptr inbounds [81919 x i32], ptr addrspace(3) @lds.array.i32, i32 0, i32 20
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%val = load i32, ptr addrspace(3) %gep
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@ -114,7 +114,7 @@
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; CHECK-NEXT: .entry_point: _amdgpu_gs
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; CHECK-NEXT: .entry_point_symbol: gs_shader
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; CHECK-NEXT: .forward_progress: true
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; CHECK-NEXT: .lds_size: 0x400
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; CHECK-NEXT: .lds_size: 0x800
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; CHECK-NEXT: .mem_ordered: true
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; CHECK-NEXT: .scratch_en: false
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; CHECK-NEXT: .scratch_memory_size: 0
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215
llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
Normal file
215
llvm/test/CodeGen/AMDGPU/pal-metadata-3.0.gfx950.ll
Normal file
@ -0,0 +1,215 @@
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; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx950 <%s | FileCheck %s --check-prefixes=CHECK
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; CHECK-LABEL: {{^}}_amdgpu_cs_main:
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; CHECK: ; TotalNumSgprs: 6
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; CHECK: ; NumVgprs: 1
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; CHECK: .amdgpu_pal_metadata
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; CHECK-NEXT: ---
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; CHECK-NEXT: amdpal.pipelines:
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; CHECK-NEXT: - .api: Vulkan
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; CHECK-NEXT: .compute_registers:
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; CHECK-NEXT: .tg_size_en: true
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; CHECK-NEXT: .tgid_x_en: false
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; CHECK-NEXT: .tgid_y_en: false
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; CHECK-NEXT: .tgid_z_en: false
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; CHECK-NEXT: .tidig_comp_cnt: 0x1
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; CHECK-NEXT: .graphics_registers:
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; CHECK-NEXT: .ps_extra_lds_size: 0
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; CHECK-NEXT: .spi_ps_input_addr:
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; CHECK-NEXT: .ancillary_ena: false
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; CHECK-NEXT: .front_face_ena: true
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; CHECK-NEXT: .line_stipple_tex_ena: false
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; CHECK-NEXT: .linear_center_ena: true
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; CHECK-NEXT: .linear_centroid_ena: true
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; CHECK-NEXT: .linear_sample_ena: true
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; CHECK-NEXT: .persp_center_ena: true
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; CHECK-NEXT: .persp_centroid_ena: true
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; CHECK-NEXT: .persp_pull_model_ena: false
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; CHECK-NEXT: .persp_sample_ena: true
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; CHECK-NEXT: .pos_fixed_pt_ena: true
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; CHECK-NEXT: .pos_w_float_ena: false
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; CHECK-NEXT: .pos_x_float_ena: false
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; CHECK-NEXT: .pos_y_float_ena: false
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; CHECK-NEXT: .pos_z_float_ena: false
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; CHECK-NEXT: .sample_coverage_ena: false
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; CHECK-NEXT: .spi_ps_input_ena:
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; CHECK-NEXT: .ancillary_ena: false
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; CHECK-NEXT: .front_face_ena: false
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; CHECK-NEXT: .line_stipple_tex_ena: false
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; CHECK-NEXT: .linear_center_ena: false
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; CHECK-NEXT: .linear_centroid_ena: false
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; CHECK-NEXT: .linear_sample_ena: false
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; CHECK-NEXT: .persp_center_ena: false
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; CHECK-NEXT: .persp_centroid_ena: false
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; CHECK-NEXT: .persp_pull_model_ena: false
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; CHECK-NEXT: .persp_sample_ena: true
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; CHECK-NEXT: .pos_fixed_pt_ena: false
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; CHECK-NEXT: .pos_w_float_ena: false
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; CHECK-NEXT: .pos_x_float_ena: false
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; CHECK-NEXT: .pos_y_float_ena: false
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; CHECK-NEXT: .pos_z_float_ena: false
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; CHECK-NEXT: .sample_coverage_ena: false
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; CHECK-NEXT: .hardware_stages:
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; CHECK-NEXT: .cs:
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; CHECK-NEXT: .agpr_count: 0
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; CHECK-NEXT: .checksum_value: 0x9444d7d0
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; CHECK-NEXT: .debug_mode: false
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; CHECK-NEXT: .entry_point: _amdgpu_cs
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; CHECK-NEXT: .entry_point_symbol: _amdgpu_cs_main
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; CHECK-NEXT: .excp_en: 0
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; CHECK-NEXT: .float_mode: 0xc0
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; CHECK-NEXT: .forward_progress: false
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; CHECK-NEXT: .ieee_mode: false
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; CHECK-NEXT: .image_op: false
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; CHECK-NEXT: .lds_size: 0
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; CHECK-NEXT: .mem_ordered: false
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; CHECK-NEXT: .scratch_en: false
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; CHECK-NEXT: .scratch_memory_size: 0
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; CHECK-NEXT: .sgpr_count: 0xa
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; CHECK-NEXT: .sgpr_limit: 0x6a
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; CHECK-NEXT: .threadgroup_dimensions:
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; CHECK-NEXT: - 0x1
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; CHECK-NEXT: - 0x400
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; CHECK-NEXT: - 0x1
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; CHECK-NEXT: .trap_present: false
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; CHECK-NEXT: .user_data_reg_map:
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; CHECK-NEXT: - 0x10000000
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: - 0xffffffff
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; CHECK-NEXT: .user_sgprs: 0x3
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; CHECK-NEXT: .vgpr_count: 0x2
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; CHECK-NEXT: .vgpr_limit: 0x100
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; CHECK-NEXT: .wavefront_size: 0x20
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; CHECK-NEXT: .wgp_mode: false
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; CHECK-NEXT: .gs:
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; CHECK-NEXT: .agpr_count: 0
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; CHECK-NEXT: .debug_mode: false
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; CHECK-NEXT: .entry_point: _amdgpu_gs
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; CHECK-NEXT: .entry_point_symbol: gs_shader
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; CHECK-NEXT: .forward_progress: false
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; CHECK-NEXT: .ieee_mode: false
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; CHECK-NEXT: .lds_size: 0x500
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; CHECK-NEXT: .mem_ordered: false
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; CHECK-NEXT: .scratch_en: false
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; CHECK-NEXT: .scratch_memory_size: 0
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; CHECK-NEXT: .sgpr_count: 0x6
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; CHECK-NEXT: .vgpr_count: 0x1
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; CHECK-NEXT: .wgp_mode: false
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; CHECK-NEXT: .hs:
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; CHECK-NEXT: .agpr_count: 0
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; CHECK-NEXT: .debug_mode: false
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; CHECK-NEXT: .entry_point: _amdgpu_hs
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; CHECK-NEXT: .entry_point_symbol: hs_shader
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; CHECK-NEXT: .forward_progress: false
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; CHECK-NEXT: .ieee_mode: false
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; CHECK-NEXT: .lds_size: 0xa00
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; CHECK-NEXT: .mem_ordered: false
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; CHECK-NEXT: .scratch_en: false
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; CHECK-NEXT: .scratch_memory_size: 0
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; CHECK-NEXT: .sgpr_count: 0x6
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; CHECK-NEXT: .vgpr_count: 0x1
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; CHECK-NEXT: .wgp_mode: false
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; CHECK-NEXT: .ps:
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; CHECK-NEXT: .agpr_count: 0
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; CHECK-NEXT: .debug_mode: false
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; CHECK-NEXT: .entry_point: _amdgpu_ps
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; CHECK-NEXT: .entry_point_symbol: ps_shader
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; CHECK-NEXT: .forward_progress: false
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; CHECK-NEXT: .ieee_mode: false
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; CHECK-NEXT: .lds_size: 0
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; CHECK-NEXT: .mem_ordered: false
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; CHECK-NEXT: .scratch_en: false
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; CHECK-NEXT: .scratch_memory_size: 0
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; CHECK-NEXT: .sgpr_count: 0x6
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; CHECK-NEXT: .vgpr_count: 0x1
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; CHECK-NEXT: .wgp_mode: false
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; CHECK: .registers: {}
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; CHECK:amdpal.version:
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; CHECK-NEXT: - 0x3
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; CHECK-NEXT: - 0
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; CHECK-NEXT:...
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; CHECK-NEXT: .end_amdgpu_pal_metadata
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define amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg1, i32 %arg2) #0 !lgc.shaderstage !1 {
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.entry:
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%i = call i64 @llvm.amdgcn.s.getpc()
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%i1 = and i64 %i, -4294967296
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%i2 = zext i32 %arg1 to i64
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%i3 = or i64 %i1, %i2
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%i4 = inttoptr i64 %i3 to ptr addrspace(4)
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%i5 = and i32 %arg2, 1023
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%i6 = lshr i32 %arg2, 10
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%i7 = and i32 %i6, 1023
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%i8 = add nuw nsw i32 %i7, %i5
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%i9 = load <4 x i32>, ptr addrspace(4) %i4, align 16
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%.idx = shl nuw nsw i32 %i8, 2
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call void @llvm.amdgcn.raw.buffer.store.i32(i32 1, <4 x i32> %i9, i32 %.idx, i32 0, i32 0)
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ret void
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}
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define amdgpu_ps void @ps_shader() #1 {
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ret void
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}
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@LDS.GS = external addrspace(3) global [1 x i32], align 4
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define amdgpu_gs void @gs_shader() {
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%ptr = getelementptr i32, ptr addrspace(3) @LDS.GS, i32 0
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store i32 0, ptr addrspace(3) %ptr, align 4
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ret void
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}
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@LDS.HS = external addrspace(3) global [1024 x i32], align 4
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define amdgpu_hs void @hs_shader() {
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%ptr = getelementptr i32, ptr addrspace(3) @LDS.HS, i32 0
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store i32 0, ptr addrspace(3) %ptr, align 4
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ret void
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}
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!amdgpu.pal.metadata.msgpack = !{!0}
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; Function Attrs: nounwind willreturn memory(none)
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declare ptr addrspace(7) @lgc.buffer.desc.to.ptr(<4 x i32>) #1
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; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
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declare i64 @llvm.amdgcn.s.getpc() #2
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; Function Attrs: nocallback nofree nosync nounwind willreturn memory(write)
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declare void @llvm.amdgcn.raw.buffer.store.i32(i32, <4 x i32>, i32, i32, i32 immarg) #3
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attributes #0 = { nounwind memory(readwrite) "amdgpu-flat-work-group-size"="1024,1024" "amdgpu-memory-bound"="false" "amdgpu-unroll-threshold"="700" "amdgpu-wave-limiter"="false" "amdgpu-work-group-info-arg-no"="4" "denormal-fp-math-f32"="preserve-sign" }
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attributes #1 = { nounwind memory(readwrite) "InitialPSInputAddr"="36983" }
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!0 = !{!"\82\B0amdpal.pipelines\91\8A\A4.api\A6Vulkan\B2.compute_registers\85\AB.tg_size_en\C3\AA.tgid_x_en\C2\AA.tgid_y_en\C2\AA.tgid_z_en\C2\AF.tidig_comp_cnt\01\B0.hardware_stages\81\A3.cs\8C\AF.checksum_value\CE\94D\D7\D0\AB.debug_mode\00\AB.float_mode\CC\C0\A9.image_op\C2\AC.mem_ordered\C3\AB.sgpr_limitj\B7.threadgroup_dimensions\93\01\CD\04\00\01\AD.trap_present\00\B2.user_data_reg_map\DC\00 \CE\10\00\00\00\CE\FF\FF\FF\FF\00\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\CE\FF\FF\FF\FF\AB.user_sgprs\03\AB.vgpr_limit\CD\01\00\AF.wavefront_size \B7.internal_pipeline_hash\92\CF\E7\10k\A6:\A6%\F7\CF\B2\1F\1A\D4{\DA\E1T\AA.registers\80\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\CF\E9Zn7}\1E\B9\E7\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CE\FF\FF\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\B4X\B8\11[\A4\88P\CF\A0;\B0\AF\FF\B4\BE\C0\AD.llpc_version\A461.1\AEamdpal.version\92\03\00"}
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!1 = !{i32 7}
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@ -52,7 +52,7 @@
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// OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000
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// OBJDUMP-NEXT: 00f0 00000cc0 80000000 00040000 00000000
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// max_lds_size
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// OBJDUMP-NEXT: 0100 00000600 00000000 00000000 00000000
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// OBJDUMP-NEXT: 0100 00000500 00000000 00000000 00000000
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// OBJDUMP-NEXT: 0110 00000000 00000000 00000000 00000000
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// OBJDUMP-NEXT: 0120 00000000 00000000 00000000 00000000
|
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// OBJDUMP-NEXT: 0130 00000cc0 80000000 00040000 00000000
|
||||
@ -231,13 +231,13 @@ max_vgprs:
|
||||
|
||||
.p2align 6
|
||||
.amdhsa_kernel max_lds_size
|
||||
.amdhsa_group_segment_fixed_size 393216
|
||||
.amdhsa_group_segment_fixed_size 327680
|
||||
.amdhsa_next_free_vgpr 1
|
||||
.amdhsa_next_free_sgpr 1
|
||||
.end_amdhsa_kernel
|
||||
|
||||
// ASM: .amdhsa_kernel max_lds_size
|
||||
// ASM: .amdhsa_group_segment_fixed_size 393216
|
||||
// ASM: .amdhsa_group_segment_fixed_size 327680
|
||||
// ASM: .end_amdhsa_kernel
|
||||
|
||||
// Test maximum VGPR allocation
|
||||
|
||||
@ -52,7 +52,7 @@
|
||||
// OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000
|
||||
// OBJDUMP-NEXT: 00f0 00000cc0 80000000 00040000 00000000
|
||||
// max_lds_size
|
||||
// OBJDUMP-NEXT: 0100 00000600 00000000 00000000 00000000
|
||||
// OBJDUMP-NEXT: 0100 00000500 00000000 00000000 00000000
|
||||
// OBJDUMP-NEXT: 0110 00000000 00000000 00000000 00000000
|
||||
// OBJDUMP-NEXT: 0120 00000000 00000000 00000000 00000000
|
||||
// OBJDUMP-NEXT: 0130 00000cc0 80000000 00040000 00000000
|
||||
@ -231,13 +231,13 @@ max_vgprs:
|
||||
|
||||
.p2align 6
|
||||
.amdhsa_kernel max_lds_size
|
||||
.amdhsa_group_segment_fixed_size 393216
|
||||
.amdhsa_group_segment_fixed_size 327680
|
||||
.amdhsa_next_free_vgpr 1
|
||||
.amdhsa_next_free_sgpr 1
|
||||
.end_amdhsa_kernel
|
||||
|
||||
// ASM: .amdhsa_kernel max_lds_size
|
||||
// ASM: .amdhsa_group_segment_fixed_size 393216
|
||||
// ASM: .amdhsa_group_segment_fixed_size 327680
|
||||
// ASM: .end_amdhsa_kernel
|
||||
|
||||
// Test maximum VGPR allocation
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user