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[RISCV] Use MachineInstr::isFullCopy in a few places. NFC

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Instead of checking that there's no subregisters.
This commit is contained in:
Luke Lau 2025-07-15 21:38:32 +08:00
parent 5977766bf6
commit 612afab512
2 changed files with 3 additions and 6 deletions
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4
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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@ -1346,9 +1346,7 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
const MachineInstr &UserMI = *UserOp.getParent();
LLVM_DEBUG(dbgs() << " Checking user: " << UserMI << "\n");
if (UserMI.isCopy() && UserMI.getOperand(0).getReg().isVirtual() &&
UserMI.getOperand(0).getSubReg() == RISCV::NoSubRegister &&
UserMI.getOperand(1).getSubReg() == RISCV::NoSubRegister) {
if (UserMI.isFullCopy() && UserMI.getOperand(0).getReg().isVirtual()) {
LLVM_DEBUG(dbgs() << " Peeking through uses of COPY\n");
Worklist.insert_range(llvm::make_pointer_range(
MRI->use_operands(UserMI.getOperand(0).getReg())));

5
llvm/lib/Target/RISCV/RISCVVectorMaskDAGMutation.cpp
View File

@ -40,9 +40,8 @@
namespace llvm {
static bool isCopyToV0(const MachineInstr &MI) {
return MI.isCopy() && MI.getOperand(0).getReg() == RISCV::V0 &&
MI.getOperand(1).getReg().isVirtual() &&
MI.getOperand(1).getSubReg() == RISCV::NoSubRegister;
return MI.isFullCopy() && MI.getOperand(0).getReg() == RISCV::V0 &&
MI.getOperand(1).getReg().isVirtual();
}
static bool isSoleUseCopyToV0(SUnit &SU) {