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Renaming Variables

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This commit is contained in:
Aaditya 2025-08-01 16:45:12 +05:30
parent 79b9c33304
commit 6579973bcd
1 changed files with 25 additions and 25 deletions
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10
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -5277,19 +5277,19 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
const TargetRegisterClass *WaveMaskRegClass = TRI->getWaveMaskRegClass();
const TargetRegisterClass *DstRegClass = MRI.getRegClass(DstReg);
Register ExecMask = MRI.createVirtualRegister(WaveMaskRegClass);
Register ActiveLanes =
Register NumActiveLanes =
MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
bool IsWave32 = ST.isWave32();
unsigned MovOpc = IsWave32 ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64;
MCRegister ExecReg = IsWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
unsigned CountReg =
unsigned BitCountOpc =
IsWave32 ? AMDGPU::S_BCNT1_I32_B32 : AMDGPU::S_BCNT1_I32_B64;
BuildMI(BB, MI, DL, TII->get(MovOpc), ExecMask).addReg(ExecReg);
auto NewAccumulator =
BuildMI(BB, MI, DL, TII->get(CountReg), ActiveLanes)
BuildMI(BB, MI, DL, TII->get(BitCountOpc), NumActiveLanes)
.addReg(ExecMask);
switch (Opc) {
@ -5548,8 +5548,8 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
.addReg(Accumulator->getOperand(0).getReg());
break;
}
case ::AMDGPU::S_ADD_U64_PSEUDO:
case ::AMDGPU::S_SUB_U64_PSEUDO: {
case AMDGPU::S_ADD_U64_PSEUDO:
case AMDGPU::S_SUB_U64_PSEUDO: {
unsigned newOpc1 = Opc == AMDGPU::S_ADD_U64_PSEUDO ? AMDGPU::S_ADD_U32
: AMDGPU::S_SUB_U32;
unsigned newOpc2 = Opc == AMDGPU::S_ADD_U64_PSEUDO ? AMDGPU::S_ADDC_U32