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[InstCombine] Teach the code that pulls logical operators through constant shifts to handle vector splats too.

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llvm-svn: 310185
This commit is contained in:
Craig Topper 2017-08-05 20:00:42 +00:00
parent 1bbcab9ca5
commit 65dd32afbc
4 changed files with 17 additions and 17 deletions
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8
llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp
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@ -470,7 +470,8 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
// If the operand is a bitwise operator with a constant RHS, and the
// shift is the only use, we can pull it out of the shift.
if (ConstantInt *Op0C = dyn_cast<ConstantInt>(Op0BO->getOperand(1))) {
const APInt *Op0C;
if (match(Op0BO->getOperand(1), m_APInt(Op0C))) {
bool isValid = true; // Valid only for And, Or, Xor
bool highBitSet = false; // Transform if high bit of constant set?
@ -495,10 +496,11 @@ Instruction *InstCombiner::FoldShiftByConstant(Value *Op0, Constant *Op1,
// operation.
//
if (isValid && I.getOpcode() == Instruction::AShr)
isValid = Op0C->getValue()[TypeBits-1] == highBitSet;
isValid = Op0C->isNegative() == highBitSet;
if (isValid) {
Constant *NewRHS = ConstantExpr::get(I.getOpcode(), Op0C, Op1);
Constant *NewRHS = ConstantExpr::get(I.getOpcode(),
cast<Constant>(Op0BO->getOperand(1)), Op1);
Value *NewShift =
Builder.CreateBinOp(I.getOpcode(), Op0BO->getOperand(0), Op1);

6
llvm/test/Transforms/InstCombine/pr17827.ll
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@ -47,12 +47,10 @@ define i1 @test_shift_and_cmp_changed1(i8 %p, i8 %q) {
ret i1 %cmp
}
; FIXME: Vectors should fold the same way.
define <2 x i1> @test_shift_and_cmp_changed1_vec(<2 x i8> %p, <2 x i8> %q) {
; CHECK-LABEL: @test_shift_and_cmp_changed1_vec(
; CHECK-NEXT: [[ANDP:%.*]] = and <2 x i8> %p, <i8 6, i8 6>
; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i8> [[ANDP]], <i8 5, i8 5>
; CHECK-NEXT: [[ANDP:%.*]] = shl <2 x i8> [[P:%.*]], <i8 5, i8 5>
; CHECK-NEXT: [[SHL:%.*]] = and <2 x i8> [[ANDP]], <i8 -64, i8 -64>
; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i8> [[SHL]], <i8 32, i8 32>
; CHECK-NEXT: ret <2 x i1> [[CMP]]
;

16
llvm/test/Transforms/InstCombine/select-with-bitwise-ops.ll
View File

@ -270,9 +270,9 @@ define i32 @test65(i64 %x) {
define <2 x i32> @test65vec(<2 x i64> %x) {
; CHECK-LABEL: @test65vec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 16, i64 16>
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <2 x i64> [[TMP1]], <i64 3, i64 3>
; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 3, i64 3>
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 2, i32 2>
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP3]], <i32 40, i32 40>
; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], <i32 2, i32 2>
; CHECK-NEXT: ret <2 x i32> [[TMP5]]
@ -299,9 +299,9 @@ define i32 @test66(i64 %x) {
define <2 x i32> @test66vec(<2 x i64> %x) {
; CHECK-LABEL: @test66vec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[X:%.*]], <i64 4294967296, i64 4294967296>
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <2 x i64> [[TMP1]], <i64 31, i64 31>
; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i32>
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i64> [[X:%.*]], <i64 31, i64 31>
; CHECK-NEXT: [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i32> [[TMP2]], <i32 2, i32 2>
; CHECK-NEXT: [[TMP4:%.*]] = or <2 x i32> [[TMP3]], <i32 40, i32 40>
; CHECK-NEXT: [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], <i32 2, i32 2>
; CHECK-NEXT: ret <2 x i32> [[TMP5]]
@ -342,8 +342,8 @@ define i32 @test67(i16 %x) {
define <2 x i32> @test67vec(<2 x i16> %x) {
; CHECK-LABEL: @test67vec(
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i16> [[X:%.*]], <i16 4, i16 4>
; CHECK-NEXT: [[TMP2:%.*]] = lshr exact <2 x i16> [[TMP1]], <i16 1, i16 1>
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 1, i16 1>
; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i16> [[TMP1]], <i16 2, i16 2>
; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i16> [[TMP2]], <i16 40, i16 40>
; CHECK-NEXT: [[TMP4:%.*]] = xor <2 x i16> [[TMP3]], <i16 2, i16 2>
; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i16> [[TMP4]] to <2 x i32>

4
llvm/test/Transforms/InstCombine/vector-casts.ll
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@ -15,8 +15,8 @@ define <2 x i1> @test1(<2 x i64> %a) {
; The ashr turns into an lshr.
define <2 x i64> @test2(<2 x i64> %a) {
; CHECK-LABEL: @test2(
; CHECK-NEXT: [[B:%.*]] = and <2 x i64> %a, <i64 65534, i64 65534>
; CHECK-NEXT: [[TMP1:%.*]] = lshr exact <2 x i64> [[B]], <i64 1, i64 1>
; CHECK-NEXT: [[B:%.*]] = lshr <2 x i64> [[A:%.*]], <i64 1, i64 1>
; CHECK-NEXT: [[TMP1:%.*]] = and <2 x i64> [[B]], <i64 32767, i64 32767>
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
;
%b = and <2 x i64> %a, <i64 65535, i64 65535>