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[RISCV] Add ISel patterns for Qualcomm uC Xqcics extension (#146675)

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Add CodeGen support for conditional select instructions in this
extension
This commit is contained in:
quic_hchandel 2025-07-11 10:27:13 +05:30 committed by GitHub
parent eba35cc1c0
commit 66969c9494
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4 changed files with 717 additions and 1 deletions
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2
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -438,7 +438,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
if (!Subtarget.useCCMovInsn() && !Subtarget.hasVendorXTHeadCondMov() &&
!Subtarget.hasVendorXqcicm())
!Subtarget.hasVendorXqcicm() && !Subtarget.hasVendorXqcics())
setOperationAction(ISD::SELECT, XLenVT, Custom);
if (Subtarget.hasVendorXqcia() && !Subtarget.is64Bit()) {

55
llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
View File

@ -1312,6 +1312,30 @@ class QCIMVCCIPat<CondCode Cond, QCIMVCCI Inst, DAGOperand InTyImm>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rs1), InTyImm:$imm, Cond)), (XLenVT GPRNoX0:$rs3), (XLenVT GPRNoX0:$rd)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, InTyImm:$imm, GPRNoX0:$rs3)>;
class QCISELECTCCIPat<CondCode Cond, QCISELECTCCI Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), (XLenVT GPRNoX0:$rs2), (XLenVT GPRNoX0:$rs3)),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, GPRNoX0:$rs3)>;
class QCISELECTICCIPat<CondCode Cond, QCISELECTICCI Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCIPatInv<CondCode Cond, QCISELECTICCI Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), simm5:$imm, Cond)), simm5:$simm2, (XLenVT GPRNoX0:$rs2)),
(Inst GPRNoX0:$rd, simm5:$imm, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCPat<CondCode Cond, QCISELECTICC Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTICCPatInv<CondCode Cond, QCISELECTICC Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), simm5:$simm2, (XLenVT GPRNoX0:$rs2)),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, GPRNoX0:$rs2, simm5:$simm2)>;
class QCISELECTIICCPat<CondCode Cond, QCISELECTIICC Inst>
: Pat<(select (XLenVT (setcc (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs1), Cond)), simm5:$simm1, simm5:$simm2),
(Inst GPRNoX0:$rd, GPRNoX0:$rs1, simm5:$simm1, simm5:$simm2)>;
// Match `riscv_brcc` and lower to the appropriate XQCIBI branch instruction.
class BcciPat<CondCode Cond, QCIBranchInst_rii Inst, DAGOperand InTyImm>
: Pat<(riscv_brcc (XLenVT GPRNoX0:$rs1), InTyImm:$rs2, Cond, bb:$imm12),
@ -1461,6 +1485,37 @@ def : QCIMVCCIPat <SETLT, QC_MVLTI, simm5>;
def : QCIMVCCIPat <SETULT, QC_MVLTUI, uimm5>;
}
let Predicates = [HasVendorXqcics, IsRV32] in {
def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2),(XLenVT GPRNoX0:$rs3)),
(QC_SELECTNEI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs2, GPRNoX0:$rs3)>;
def : Pat<(select (XLenVT GPRNoX0:$rd), (XLenVT GPRNoX0:$rs2), simm5:$simm2),
(QC_SELECTINEI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs2, simm5:$simm2)>;
def : Pat<(select (XLenVT GPRNoX0:$rd), simm5:$simm2,(XLenVT GPRNoX0:$rs2)),
(QC_SELECTIEQI GPRNoX0:$rd, (XLenVT 0), GPRNoX0:$rs2, simm5:$simm2)>;
// Below AddedComplexity is added to prefer these conditional select instructions over
// conditional move instructions
let AddedComplexity = 1 in {
def : QCISELECTCCIPat <SETEQ, QC_SELECTEQI>;
def : QCISELECTCCIPat <SETNE, QC_SELECTNEI>;
}
def : QCISELECTICCIPat <SETEQ, QC_SELECTIEQI>;
def : QCISELECTICCIPat <SETNE, QC_SELECTINEI>;
def : QCISELECTICCIPatInv <SETEQ, QC_SELECTINEI>;
def : QCISELECTICCIPatInv <SETNE, QC_SELECTIEQI>;
def : QCISELECTICCPat <SETEQ, QC_SELECTIEQ>;
def : QCISELECTICCPat <SETNE, QC_SELECTINE>;
def : QCISELECTICCPatInv <SETEQ, QC_SELECTINE>;
def : QCISELECTICCPatInv <SETNE, QC_SELECTIEQ>;
def : QCISELECTIICCPat <SETEQ, QC_SELECTIIEQ>;
def : QCISELECTIICCPat <SETNE, QC_SELECTIINE>;
} // Predicates = [HasVendorXqcics, IsRV32]
//===----------------------------------------------------------------------===/i
// Compress Instruction tablegen backend.
//===----------------------------------------------------------------------===//

209
llvm/test/CodeGen/RISCV/select-cond.ll
View File

@ -5,6 +5,8 @@
; RUN: | FileCheck %s --check-prefixes=RV32-THEAD
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV64
; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \
@ -35,6 +37,12 @@ define signext i32 @select_i32_trunc(i32 signext %cond, i32 signext %x, i32 sign
; RV32-XQCICM-NEXT: mv a0, a1
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_trunc:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a0, a0, 1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@ -80,6 +88,12 @@ define signext i32 @select_i32_param(i1 signext %cond, i32 signext %x, i32 signe
; RV32-XQCICM-NEXT: mv a0, a1
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_param:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a0, a0, 1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@ -122,6 +136,13 @@ define signext i32 @select_i32_eq(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_eq:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: xor a0, a0, a1
; RV32-XQCICS-NEXT: seqz a0, a0
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB2_2
@ -164,6 +185,13 @@ define signext i32 @select_i32_ne(i32 signext %a, i32 signext %b, i32 signext %x
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ne:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: xor a0, a0, a1
; RV32-XQCICS-NEXT: snez a0, a0
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB3_2
@ -206,6 +234,12 @@ define signext i32 @select_i32_ugt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ugt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a1, a0
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB4_2
@ -248,6 +282,12 @@ define signext i32 @select_i32_uge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_uge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB5_2
@ -290,6 +330,12 @@ define signext i32 @select_i32_ult(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ult:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB6_2
@ -332,6 +378,12 @@ define signext i32 @select_i32_ule(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_ule:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu a0, a1, a0
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB7_2
@ -374,6 +426,12 @@ define signext i32 @select_i32_sgt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sgt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a1, a0
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB8_2
@ -416,6 +474,12 @@ define signext i32 @select_i32_sge(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB9_2
@ -458,6 +522,12 @@ define signext i32 @select_i32_slt(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a3
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_slt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a3
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB10_2
@ -500,6 +570,12 @@ define signext i32 @select_i32_sle(i32 signext %a, i32 signext %b, i32 signext %
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i32_sle:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt a0, a1, a0
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a3, a2
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i32_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB11_2
@ -550,6 +626,14 @@ define i64 @select_i64_trunc(i64 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a0, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_trunc:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a1, a0, 1
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a3, a5
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a2, a4
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_trunc:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@ -601,6 +685,15 @@ define i64 @select_i64_param(i1 %cond, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a2
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_param:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: andi a5, a0, 1
; RV32-XQCICS-NEXT: mv a0, a5
; RV32-XQCICS-NEXT: qc.selectnei a5, 0, a2, a4
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a1, a3
; RV32-XQCICS-NEXT: mv a1, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_param:
; RV64: # %bb.0:
; RV64-NEXT: andi a3, a0, 1
@ -657,6 +750,16 @@ define i64 @select_i64_eq(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_eq:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: xor a0, a0, a2
; RV32-XQCICS-NEXT: or a1, a0, a1
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selecteqi a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selecteqi a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_eq:
; RV64: # %bb.0:
; RV64-NEXT: beq a0, a1, .LBB14_2
@ -713,6 +816,16 @@ define i64 @select_i64_ne(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ne:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: xor a0, a0, a2
; RV32-XQCICS-NEXT: or a1, a0, a1
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ne:
; RV64: # %bb.0:
; RV64-NEXT: bne a0, a1, .LBB15_2
@ -774,6 +887,18 @@ define i64 @select_i64_ugt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ugt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ugt:
; RV64: # %bb.0:
; RV64-NEXT: bltu a1, a0, .LBB16_2
@ -835,6 +960,18 @@ define i64 @select_i64_uge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_uge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_uge:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a0, a1, .LBB17_2
@ -896,6 +1033,18 @@ define i64 @select_i64_ult(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ult:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ult:
; RV64: # %bb.0:
; RV64-NEXT: bltu a0, a1, .LBB18_2
@ -957,6 +1106,18 @@ define i64 @select_i64_ule(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_ule:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: sltu t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_ule:
; RV64: # %bb.0:
; RV64-NEXT: bgeu a1, a0, .LBB19_2
@ -1018,6 +1179,18 @@ define i64 @select_i64_sgt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sgt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sgt:
; RV64: # %bb.0:
; RV64-NEXT: blt a1, a0, .LBB20_2
@ -1079,6 +1252,18 @@ define i64 @select_i64_sge(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sge:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sge:
; RV64: # %bb.0:
; RV64-NEXT: bge a0, a1, .LBB21_2
@ -1140,6 +1325,18 @@ define i64 @select_i64_slt(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a5
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_slt:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt t0, a1, a3
; RV32-XQCICS-NEXT: sltu a0, a0, a2
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a4, a6
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a5, a7
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_slt:
; RV64: # %bb.0:
; RV64-NEXT: blt a0, a1, .LBB22_2
@ -1201,6 +1398,18 @@ define i64 @select_i64_sle(i64 %a, i64 %b, i64 %x, i64 %y) nounwind {
; RV32-XQCICM-NEXT: mv a1, a7
; RV32-XQCICM-NEXT: ret
;
; RV32-XQCICS-LABEL: select_i64_sle:
; RV32-XQCICS: # %bb.0:
; RV32-XQCICS-NEXT: slt t0, a3, a1
; RV32-XQCICS-NEXT: sltu a0, a2, a0
; RV32-XQCICS-NEXT: xor a1, a1, a3
; RV32-XQCICS-NEXT: seqz a1, a1
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a0, t0
; RV32-XQCICS-NEXT: mv a0, a1
; RV32-XQCICS-NEXT: qc.selectnei a0, 0, a6, a4
; RV32-XQCICS-NEXT: qc.selectnei a1, 0, a7, a5
; RV32-XQCICS-NEXT: ret
;
; RV64-LABEL: select_i64_sle:
; RV64: # %bb.0:
; RV64-NEXT: bge a1, a0, .LBB23_2

452
llvm/test/CodeGen/RISCV/xqcics.ll Normal file
View File

@ -0,0 +1,452 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; Test that we are able to generate the Xqcics instructions
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS
define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_s1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a1, a0, 1
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: bnez a1, .LBB0_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 12
; RV32I-NEXT: .LBB0_2: # %entry
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq_s1:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: qc.selectinei a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 %x, i32 12
ret i32 %sel
}
define i32 @select_cc_example_eq_s2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_s2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a1, a0, 1
; RV32I-NEXT: bnez a1, .LBB1_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: li a0, 12
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq_s2:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a2, 12
; RV32IXQCICS-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 12, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_eq_s3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_s3:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB2_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 25
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: li a0, 12
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq_s3:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: andi a0, a0, 1
; RV32IXQCICS-NEXT: li a1, 25
; RV32IXQCICS-NEXT: qc.selectieqi a0, 0, a1, 12
; RV32IXQCICS-NEXT: ret
entry:
%cond_trunc = trunc i32 %a to i1
%sel = select i1 %cond_trunc, i32 12, i32 25
ret i32 %sel
}
define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: beq a0, a1, .LBB3_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB3_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define i32 @select_cc_example_eq_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eq_c:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: beq a0, a1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB4_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eq_c:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selecteqi a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define i32 @select_cc_example_ne(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: bne a0, a1, .LBB5_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB5_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ne:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 11
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define i32 @select_cc_example_ne_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ne_c:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: bne a0, a1, .LBB6_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: mv a2, a3
; RV32I-NEXT: .LBB6_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ne_c:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectnei a0, 11, a2, a3
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 11, %a
%sel = select i1 %cmp, i32 %x, i32 %y
ret i32 %sel
}
define i32 @select_cc_example_eqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqi:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: beq a0, a1, .LBB7_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB7_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eqi:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}
define i32 @select_cc_example_eqi_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqi_c:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: bne a0, a1, .LBB8_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB8_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eqi_c:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 11, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_nei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_nei:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: bne a0, a1, .LBB9_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB9_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_nei:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectine a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}
define i32 @select_cc_example_nei_c(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_nei_c:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: beq a0, a1, .LBB10_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB10_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_nei_c:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieq a0, a1, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 11, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_ieqi(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: beq a0, a1, .LBB11_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB11_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ieqi:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 12
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}
define i32 @select_cc_example_ieqi_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi_c1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: beq a0, a1, .LBB12_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB12_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ieqi_c1:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 12, %a
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}
define i32 @select_cc_example_ieqi_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi_c2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: bne a0, a1, .LBB13_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB13_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ieqi_c2:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 %a, 12
%sel = select i1 %cmp, i32 11, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_ieqi_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_ieqi_c3:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: bne a0, a1, .LBB14_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB14_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_ieqi_c3:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 12, %a
%sel = select i1 %cmp, i32 11, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_inei(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: bne a0, a1, .LBB15_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB15_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_inei:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 12
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}
define i32 @select_cc_example_inei_c1(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei_c1:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: bne a0, a1, .LBB16_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB16_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_inei_c1:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectinei a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 12, %a
%sel = select i1 %cmp, i32 %x, i32 11
ret i32 %sel
}
define i32 @select_cc_example_inei_c2(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei_c2:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: beq a0, a1, .LBB17_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB17_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_inei_c2:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 %a, 12
%sel = select i1 %cmp, i32 11, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_inei_c3(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_inei_c3:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: li a1, 12
; RV32I-NEXT: beq a0, a1, .LBB18_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a2, 11
; RV32I-NEXT: .LBB18_2: # %entry
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_inei_c3:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectieqi a0, 12, a2, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 12, %a
%sel = select i1 %cmp, i32 11, i32 %x
ret i32 %sel
}
define i32 @select_cc_example_eqii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_eqii:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: beq a0, a1, .LBB19_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB19_2:
; RV32I-NEXT: li a0, 13
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_eqii:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiieq a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp eq i32 %a, %b
%sel = select i1 %cmp, i32 13, i32 11
ret i32 %sel
}
define i32 @select_cc_example_neii(i32 %a, i32 %b, i32 %x, i32 %y) {
; RV32I-LABEL: select_cc_example_neii:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: bne a0, a1, .LBB20_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 11
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB20_2:
; RV32I-NEXT: li a0, 13
; RV32I-NEXT: ret
;
; RV32IXQCICS-LABEL: select_cc_example_neii:
; RV32IXQCICS: # %bb.0: # %entry
; RV32IXQCICS-NEXT: qc.selectiine a0, a1, 13, 11
; RV32IXQCICS-NEXT: ret
entry:
%cmp = icmp ne i32 %a, %b
%sel = select i1 %cmp, i32 13, i32 11
ret i32 %sel
}