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[NFC][POWER] add Pre-Commit test case for Inefficient std::bit_floor(x) (#183363)

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add a pre-commit test case for Inefficient asm of std::bit_floor(x) for
powerpc.
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zhijian lin 2026-02-27 13:24:34 -05:00 committed by GitHub
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commit 67a51ea34d
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llvm/test/CodeGen/PowerPC/bit_floor.ll Normal file
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -ppc-asm-full-reg-names < %s | FileCheck --check-prefix=AIX32 %s
; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -ppc-asm-full-reg-names < %s | FileCheck --check-prefixes=AIX64 %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -ppc-asm-full-reg-names < %s | FileCheck --check-prefixes=LNX64 %s
define noundef range(i32 0, -2147483647) i32 @_Z10bitfloor32j(i32 noundef %x) local_unnamed_addr {
; AIX32-LABEL: _Z10bitfloor32j:
; AIX32: # %bb.0: # %entry
; AIX32-NEXT: cntlzw r4, r3
; AIX32-NEXT: lis r5, -32768
; AIX32-NEXT: cmplwi r3, 0
; AIX32-NEXT: srw r4, r5, r4
; AIX32-NEXT: iseleq r3, 0, r4
; AIX32-NEXT: blr
;
; AIX64-LABEL: _Z10bitfloor32j:
; AIX64: # %bb.0: # %entry
; AIX64-NEXT: cntlzw r4, r3
; AIX64-NEXT: lis r5, -32768
; AIX64-NEXT: cmplwi r3, 0
; AIX64-NEXT: srw r4, r5, r4
; AIX64-NEXT: iseleq r3, 0, r4
; AIX64-NEXT: blr
;
; LNX64-LABEL: _Z10bitfloor32j:
; LNX64: # %bb.0: # %entry
; LNX64-NEXT: cntlzw r4, r3
; LNX64-NEXT: cmplwi r3, 0
; LNX64-NEXT: lis r5, -32768
; LNX64-NEXT: srw r4, r5, r4
; LNX64-NEXT: iseleq r3, 0, r4
; LNX64-NEXT: blr
entry:
%cmp.i = icmp eq i32 %x, 0
%0 = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %x, i1 true)
%shl.i = lshr exact i32 -2147483648, %0
%cond.i = select i1 %cmp.i, i32 0, i32 %shl.i
ret i32 %cond.i
}
declare i32 @llvm.ctlz.i32(i32, i1 immarg)
define noundef range(i64 0, -9223372036854775807) i64 @_Z10bitfloor64y(i64 noundef %x) local_unnamed_addr {
; AIX32-LABEL: _Z10bitfloor64y:
; AIX32: # %bb.0: # %entry
; AIX32-NEXT: cntlzw r6, r4
; AIX32-NEXT: cntlzw r5, r3
; AIX32-NEXT: lis r7, -32768
; AIX32-NEXT: cmplwi r3, 0
; AIX32-NEXT: addi r6, r6, 32
; AIX32-NEXT: iseleq r5, r6, r5
; AIX32-NEXT: or. r3, r4, r3
; AIX32-NEXT: addi r6, r5, -32
; AIX32-NEXT: subfic r8, r5, 32
; AIX32-NEXT: srw r5, r7, r5
; AIX32-NEXT: srw r6, r7, r6
; AIX32-NEXT: slw r8, r7, r8
; AIX32-NEXT: or r3, r8, r6
; AIX32-NEXT: iseleq r4, 0, r3
; AIX32-NEXT: iseleq r3, 0, r5
; AIX32-NEXT: blr
;
; AIX64-LABEL: _Z10bitfloor64y:
; AIX64: # %bb.0: # %entry
; AIX64-NEXT: li r5, 1
; AIX64-NEXT: cntlzd r4, r3
; AIX64-NEXT: cmpldi r3, 0
; AIX64-NEXT: rldic r5, r5, 63, 0
; AIX64-NEXT: srd r4, r5, r4
; AIX64-NEXT: iseleq r3, 0, r4
; AIX64-NEXT: blr
;
; LNX64-LABEL: _Z10bitfloor64y:
; LNX64: # %bb.0: # %entry
; LNX64-NEXT: li r5, 1
; LNX64-NEXT: cntlzd r4, r3
; LNX64-NEXT: cmpldi r3, 0
; LNX64-NEXT: rldic r5, r5, 63, 0
; LNX64-NEXT: srd r4, r5, r4
; LNX64-NEXT: iseleq r3, 0, r4
; LNX64-NEXT: blr
entry:
%cmp.i = icmp eq i64 %x, 0
%0 = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %x, i1 true)
%shl.i = lshr exact i64 -9223372036854775808, %0
%cond.i = select i1 %cmp.i, i64 0, i64 %shl.i
ret i64 %cond.i
}
declare i64 @llvm.ctlz.i64(i64, i1 immarg)