From 681fd2c11e0819b32ca514b2b989f1a246c0b33b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 22 Mar 2022 23:41:23 -0700 Subject: [PATCH] Revert "[SelectionDAG] Don't create entries in ValueMap in ComputePHILiveOutRegInfo" This reverts commit 1a9b55b63a6e18a4692eeb795697cb61ca1b002f. Causing build bot failures --- llvm/include/llvm/CodeGen/FunctionLoweringInfo.h | 1 - llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 9 ++------- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h index 071242e14532..524730d53694 100644 --- a/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h +++ b/llvm/include/llvm/CodeGen/FunctionLoweringInfo.h @@ -258,7 +258,6 @@ public: return; Register Reg = It->second; - assert(Reg != 0); if (Reg == 0) return; diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index e39ad73cf20c..b49455111a46 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -445,14 +445,9 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); unsigned BitWidth = IntVT.getSizeInBits(); - auto It = ValueMap.find(PN); - if (It == ValueMap.end()) + Register DestReg = ValueMap[PN]; + if (!Register::isVirtualRegister(DestReg)) return; - - Register DestReg = It->second; - if (DestReg == 0) - return - assert(Register::isVirtualRegister(DestReg) && "Expected a virtual reg"); LiveOutRegInfo.grow(DestReg); LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];