From 68cbcf7ec2010a6fc4ad825ecf55e86b3c49f5fb Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Wed, 1 Apr 2026 23:14:38 -0700 Subject: [PATCH] [RISCV] Check EnsureWholeVectorRegisterMoveValidVTYPE in RISCVInsertVSETVLI::transferBefore. (#190022) Fixes #189786 --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 3 ++- .../rvv/vsetvli-insert-whole-reg-move.ll | 27 +++++++++++++++++++ 2 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 2569954d62eb..8a5ac3363b90 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -314,7 +314,8 @@ static VSETVLIInfo adjustIncoming(const VSETVLIInfo &PrevInfo, // legal for MI, but may not be the state requested by MI. void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, const MachineInstr &MI) const { - if (RISCV::isVectorCopy(ST->getRegisterInfo(), MI) && + if (EnsureWholeVectorRegisterMoveValidVTYPE && + RISCV::isVectorCopy(ST->getRegisterInfo(), MI) && (Info.isUnknown() || !Info.isValid() || Info.hasSEWLMULRatioOnly())) { // Use an arbitrary but valid AVL and VTYPE so vill will be cleared. It may // be coalesced into another vsetvli since we won't demand any fields. diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll new file mode 100644 index 000000000000..9e77ef3c8546 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-whole-reg-move.ll @@ -0,0 +1,27 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefix=ENABLE +; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-insert-vsetvli-whole-vector-register-move-valid-vtype=false | FileCheck %s --check-prefix=DISABLE + +define @foo( %0, %1, %2) nounwind { +; ENABLE-LABEL: foo: +; ENABLE: # %bb.0: # %entry +; ENABLE-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; ENABLE-NEXT: vmv1r.v v8, v9 +; ENABLE-NEXT: vmadd.vv v8, v9, v9 +; ENABLE-NEXT: ret +; +; DISABLE-LABEL: foo: +; DISABLE: # %bb.0: # %entry +; DISABLE-NEXT: vmv1r.v v8, v9 +; DISABLE-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; DISABLE-NEXT: vmadd.vv v8, v9, v9 +; DISABLE-NEXT: ret +entry: + %a = call @llvm.riscv.vmadd.nxv8i8.nxv8i8( + %1, + %1, + %1, + i64 1, i64 1) + + ret %a +}