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[RISCV][NFC] Add helpers for RVV register classes

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There are two places in tree that use these helpers and there will
be more future usages.

Reviewers: asb, BeMg, lukel97

Reviewed By: BeMg, lukel97

Pull Request: https://github.com/llvm/llvm-project/pull/84144
This commit is contained in:
Wang Pengcheng 2024-03-07 14:18:37 +08:00 committed by GitHub
parent 2e25926b50
commit 68d07bf34f
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 23 additions and 15 deletions
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22
llvm/lib/Target/RISCV/RISCVRegisterInfo.h
View File

@ -112,11 +112,33 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
bool doesRegClassHavePseudoInitUndef(
const TargetRegisterClass *RC) const override {
return isVRRegClass(RC);
}
static bool isVRRegClass(const TargetRegisterClass *RC) {
return RISCV::VRRegClass.hasSubClassEq(RC) ||
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
RISCV::VRM8RegClass.hasSubClassEq(RC);
}
static bool isVRNRegClass(const TargetRegisterClass *RC) {
return RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
RISCV::VRN3M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN3M2RegClass.hasSubClassEq(RC) ||
RISCV::VRN4M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN4M2RegClass.hasSubClassEq(RC) ||
RISCV::VRN5M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN6M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN7M1RegClass.hasSubClassEq(RC) ||
RISCV::VRN8M1RegClass.hasSubClassEq(RC);
}
static bool isRVVRegClass(const TargetRegisterClass *RC) {
return isVRRegClass(RC) || isVRNRegClass(RC);
}
};
}

16
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
View File

@ -278,21 +278,7 @@ public:
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
const TargetRegisterClass &RC) {
return RISCV::VRRegClass.hasSubClassEq(&RC) ||
RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
return RISCVRegisterInfo::isRVVRegClass(&RC);
}
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }