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[APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

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Most clients only used these methods because they wanted to be able to
extend or truncate to the same bit width (which is a no-op). Now that
the standard zext, sext and trunc allow this, there is no reason to use
the OrSelf versions.

The OrSelf versions additionally have the strange behaviour of allowing
extending to a *smaller* width, or truncating to a *larger* width, which
are also treated as no-ops. A small amount of client code relied on this
(ConstantRange::castOp and MicrosoftCXXNameMangler::mangleNumber) and
needed rewriting.

Differential Revision: https://reviews.llvm.org/D125557
This commit is contained in:
Jay Foad 2021-10-06 10:54:07 +01:00
parent 70ace420c1
commit 6bec3e9303
34 changed files with 120 additions and 119 deletions
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10
clang/lib/AST/ExprConstant.cpp
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@ -8596,7 +8596,7 @@ static bool getBytesReturnedByAllocSizeCall(const ASTContext &Ctx,
Into = ExprResult.Val.getInt(); Into = ExprResult.Val.getInt();
if (Into.isNegative() || !Into.isIntN(BitsInSizeT)) if (Into.isNegative() || !Into.isIntN(BitsInSizeT))
return false; return false;
Into = Into.zextOrSelf(BitsInSizeT); Into = Into.zext(BitsInSizeT);
return true; return true;
}; };
@ -9582,8 +9582,8 @@ bool PointerExprEvaluator::VisitCXXNewExpr(const CXXNewExpr *E) {
unsigned Bits = unsigned Bits =
std::max(CAT->getSize().getBitWidth(), ArrayBound.getBitWidth()); std::max(CAT->getSize().getBitWidth(), ArrayBound.getBitWidth());
llvm::APInt InitBound = CAT->getSize().zextOrSelf(Bits); llvm::APInt InitBound = CAT->getSize().zext(Bits);
llvm::APInt AllocBound = ArrayBound.zextOrSelf(Bits); llvm::APInt AllocBound = ArrayBound.zext(Bits);
if (InitBound.ugt(AllocBound)) { if (InitBound.ugt(AllocBound)) {
if (IsNothrow) if (IsNothrow)
return ZeroInitialization(E); return ZeroInitialization(E);
@ -10377,9 +10377,9 @@ bool VectorExprEvaluator::VisitCastExpr(const CastExpr *E) {
for (unsigned i = 0; i < NElts; i++) { for (unsigned i = 0; i < NElts; i++) {
llvm::APInt Elt; llvm::APInt Elt;
if (BigEndian) if (BigEndian)
Elt = SValInt.rotl(i*EltSize+FloatEltSize).truncOrSelf(FloatEltSize); Elt = SValInt.rotl(i * EltSize + FloatEltSize).trunc(FloatEltSize);
else else
Elt = SValInt.rotr(i*EltSize).truncOrSelf(FloatEltSize); Elt = SValInt.rotr(i * EltSize).trunc(FloatEltSize);
Elts.push_back(APValue(APFloat(Sem, Elt))); Elts.push_back(APValue(APFloat(Sem, Elt)));
} }
} else if (EltTy->isIntegerType()) { } else if (EltTy->isIntegerType()) {

4
clang/lib/AST/MicrosoftMangle.cpp
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@ -808,8 +808,8 @@ void MicrosoftCXXNameMangler::mangleNumber(llvm::APSInt Number) {
// to convert every integer to signed 64 bit before mangling (including // to convert every integer to signed 64 bit before mangling (including
// unsigned 64 bit values). Do the same, but preserve bits beyond the bottom // unsigned 64 bit values). Do the same, but preserve bits beyond the bottom
// 64. // 64.
llvm::APInt Value = unsigned Width = std::max(Number.getBitWidth(), 64U);
Number.isSigned() ? Number.sextOrSelf(64) : Number.zextOrSelf(64); llvm::APInt Value = Number.extend(Width);
// <non-negative integer> ::= A@ # when Number == 0 // <non-negative integer> ::= A@ # when Number == 0
// ::= <decimal digit> # when 1 <= Number <= 10 // ::= <decimal digit> # when 1 <= Number <= 10

2
clang/lib/CodeGen/CGBuiltin.cpp
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@ -2002,7 +2002,7 @@ EmitCheckedMixedSignMultiply(CodeGenFunction &CGF, const clang::Expr *Op1,
// Signed overflow occurs if the result is greater than INT_MAX or lesser // Signed overflow occurs if the result is greater than INT_MAX or lesser
// than INT_MIN, i.e when |Result| > (INT_MAX + IsNegative). // than INT_MIN, i.e when |Result| > (INT_MAX + IsNegative).
auto IntMax = auto IntMax =
llvm::APInt::getSignedMaxValue(ResultInfo.Width).zextOrSelf(OpWidth); llvm::APInt::getSignedMaxValue(ResultInfo.Width).zext(OpWidth);
llvm::Value *MaxResult = llvm::Value *MaxResult =
CGF.Builder.CreateAdd(llvm::ConstantInt::get(OpTy, IntMax), CGF.Builder.CreateAdd(llvm::ConstantInt::get(OpTy, IntMax),
CGF.Builder.CreateZExt(IsNegative, OpTy)); CGF.Builder.CreateZExt(IsNegative, OpTy));

2
clang/lib/Sema/SemaDecl.cpp
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@ -18720,7 +18720,7 @@ bool Sema::IsValueInFlagEnum(const EnumDecl *ED, const llvm::APInt &Val,
const auto &EVal = E->getInitVal(); const auto &EVal = E->getInitVal();
// Only single-bit enumerators introduce new flag values. // Only single-bit enumerators introduce new flag values.
if (EVal.isPowerOf2()) if (EVal.isPowerOf2())
FlagBits = FlagBits.zextOrSelf(EVal.getBitWidth()) | EVal; FlagBits = FlagBits.zext(EVal.getBitWidth()) | EVal;
} }
} }

4
clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
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@ -264,8 +264,8 @@ bool shouldCompletelyUnroll(const Stmt *LoopStmt, ASTContext &ASTCtx,
Matches[0].getNodeAs<IntegerLiteral>("initNum")->getValue(); Matches[0].getNodeAs<IntegerLiteral>("initNum")->getValue();
auto CondOp = Matches[0].getNodeAs<BinaryOperator>("conditionOperator"); auto CondOp = Matches[0].getNodeAs<BinaryOperator>("conditionOperator");
if (InitNum.getBitWidth() != BoundNum.getBitWidth()) { if (InitNum.getBitWidth() != BoundNum.getBitWidth()) {
InitNum = InitNum.zextOrSelf(BoundNum.getBitWidth()); InitNum = InitNum.zext(BoundNum.getBitWidth());
BoundNum = BoundNum.zextOrSelf(InitNum.getBitWidth()); BoundNum = BoundNum.zext(InitNum.getBitWidth());
} }
if (CondOp->getOpcode() == BO_GE || CondOp->getOpcode() == BO_LE) if (CondOp->getOpcode() == BO_GE || CondOp->getOpcode() == BO_LE)

4
llvm/lib/Analysis/BasicAliasAnalysis.cpp
View File

@ -659,8 +659,8 @@ BasicAAResult::DecomposeGEPExpression(const Value *V, const DataLayout &DL,
unsigned TypeSize = unsigned TypeSize =
DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize(); DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
LE = LE.mul(APInt(IndexSize, TypeSize), GEPOp->isInBounds()); LE = LE.mul(APInt(IndexSize, TypeSize), GEPOp->isInBounds());
Decomposed.Offset += LE.Offset.sextOrSelf(MaxIndexSize); Decomposed.Offset += LE.Offset.sext(MaxIndexSize);
APInt Scale = LE.Scale.sextOrSelf(MaxIndexSize); APInt Scale = LE.Scale.sext(MaxIndexSize);
// If we already had an occurrence of this index variable, merge this // If we already had an occurrence of this index variable, merge this
// scale into it. For example, we want to handle: // scale into it. For example, we want to handle:

10
llvm/lib/Analysis/ConstantFolding.cpp
View File

@ -91,7 +91,7 @@ static Constant *foldConstVectorToAPInt(APInt &Result, Type *DestTy,
return ConstantExpr::getBitCast(C, DestTy); return ConstantExpr::getBitCast(C, DestTy);
Result <<= BitShift; Result <<= BitShift;
Result |= ElementCI->getValue().zextOrSelf(Result.getBitWidth()); Result |= ElementCI->getValue().zext(Result.getBitWidth());
} }
return nullptr; return nullptr;
@ -2878,11 +2878,11 @@ static Constant *ConstantFoldScalarCall3(StringRef Name,
unsigned Width = C0->getBitWidth(); unsigned Width = C0->getBitWidth();
assert(Scale < Width && "Illegal scale."); assert(Scale < Width && "Illegal scale.");
unsigned ExtendedWidth = Width * 2; unsigned ExtendedWidth = Width * 2;
APInt Product = (C0->sextOrSelf(ExtendedWidth) * APInt Product =
C1->sextOrSelf(ExtendedWidth)).ashr(Scale); (C0->sext(ExtendedWidth) * C1->sext(ExtendedWidth)).ashr(Scale);
if (IntrinsicID == Intrinsic::smul_fix_sat) { if (IntrinsicID == Intrinsic::smul_fix_sat) {
APInt Max = APInt::getSignedMaxValue(Width).sextOrSelf(ExtendedWidth); APInt Max = APInt::getSignedMaxValue(Width).sext(ExtendedWidth);
APInt Min = APInt::getSignedMinValue(Width).sextOrSelf(ExtendedWidth); APInt Min = APInt::getSignedMinValue(Width).sext(ExtendedWidth);
Product = APIntOps::smin(Product, Max); Product = APIntOps::smin(Product, Max);
Product = APIntOps::smax(Product, Min); Product = APIntOps::smax(Product, Min);
} }

2
llvm/lib/Analysis/LazyValueInfo.cpp
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@ -1133,7 +1133,7 @@ static ValueLatticeElement getValueFromICmpCondition(Value *Val, ICmpInst *ICI,
ConstantRange CR = ConstantRange::makeExactICmpRegion(EdgePred, *C); ConstantRange CR = ConstantRange::makeExactICmpRegion(EdgePred, *C);
if (!CR.isEmptySet()) if (!CR.isEmptySet())
return ValueLatticeElement::getRange(ConstantRange::getNonEmpty( return ValueLatticeElement::getRange(ConstantRange::getNonEmpty(
CR.getUnsignedMin().zextOrSelf(BitWidth), APInt(BitWidth, 0))); CR.getUnsignedMin().zext(BitWidth), APInt(BitWidth, 0)));
} }
return ValueLatticeElement::getOverdefined(); return ValueLatticeElement::getOverdefined();

2
llvm/lib/Analysis/MemoryBuiltins.cpp
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@ -385,7 +385,7 @@ llvm::getAllocSize(const CallBase *CB,
if (!Arg) if (!Arg)
return None; return None;
APInt MaxSize = Arg->getValue().zextOrSelf(IntTyBits); APInt MaxSize = Arg->getValue().zext(IntTyBits);
if (Size.ugt(MaxSize)) if (Size.ugt(MaxSize))
Size = MaxSize + 1; Size = MaxSize + 1;
} }

8
llvm/lib/Analysis/ScalarEvolution.cpp
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@ -9717,8 +9717,8 @@ GetQuadraticEquation(const SCEVAddRecExpr *AddRec) {
static Optional<APInt> MinOptional(Optional<APInt> X, Optional<APInt> Y) { static Optional<APInt> MinOptional(Optional<APInt> X, Optional<APInt> Y) {
if (X.hasValue() && Y.hasValue()) { if (X.hasValue() && Y.hasValue()) {
unsigned W = std::max(X->getBitWidth(), Y->getBitWidth()); unsigned W = std::max(X->getBitWidth(), Y->getBitWidth());
APInt XW = X->sextOrSelf(W); APInt XW = X->sext(W);
APInt YW = Y->sextOrSelf(W); APInt YW = Y->sext(W);
return XW.slt(YW) ? *X : *Y; return XW.slt(YW) ? *X : *Y;
} }
if (!X.hasValue() && !Y.hasValue()) if (!X.hasValue() && !Y.hasValue())
@ -9870,8 +9870,8 @@ SolveQuadraticAddRecRange(const SCEVAddRecExpr *AddRec,
std::tie(A, B, C, M, BitWidth) = *T; std::tie(A, B, C, M, BitWidth) = *T;
// Lower bound is inclusive, subtract 1 to represent the exiting value. // Lower bound is inclusive, subtract 1 to represent the exiting value.
APInt Lower = Range.getLower().sextOrSelf(A.getBitWidth()) - 1; APInt Lower = Range.getLower().sext(A.getBitWidth()) - 1;
APInt Upper = Range.getUpper().sextOrSelf(A.getBitWidth()); APInt Upper = Range.getUpper().sext(A.getBitWidth());
auto SL = SolveForBoundary(Lower); auto SL = SolveForBoundary(Lower);
auto SU = SolveForBoundary(Upper); auto SU = SolveForBoundary(Upper);
// If any of the solutions was unknown, no meaninigful conclusions can // If any of the solutions was unknown, no meaninigful conclusions can

2
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
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@ -2874,7 +2874,7 @@ static int isRepeatedByteSequence(const Value *V, const DataLayout &DL) {
assert(Size % 8 == 0); assert(Size % 8 == 0);
// Extend the element to take zero padding into account. // Extend the element to take zero padding into account.
APInt Value = CI->getValue().zextOrSelf(Size); APInt Value = CI->getValue().zext(Size);
if (!Value.isSplat(8)) if (!Value.isSplat(8))
return -1; return -1;

2
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -7466,7 +7466,7 @@ static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB) {
unsigned NumBits = Ty.getScalarSizeInBits(); unsigned NumBits = Ty.getScalarSizeInBits();
auto ValVRegAndVal = getIConstantVRegValWithLookThrough(Val, MRI); auto ValVRegAndVal = getIConstantVRegValWithLookThrough(Val, MRI);
if (!Ty.isVector() && ValVRegAndVal) { if (!Ty.isVector() && ValVRegAndVal) {
APInt Scalar = ValVRegAndVal->Value.truncOrSelf(8); APInt Scalar = ValVRegAndVal->Value.trunc(8);
APInt SplatVal = APInt::getSplat(NumBits, Scalar); APInt SplatVal = APInt::getSplat(NumBits, Scalar);
return MIB.buildConstant(Ty, SplatVal).getReg(0); return MIB.buildConstant(Ty, SplatVal).getReg(0);
} }

9
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -882,8 +882,8 @@ void DAGCombiner::deleteAndRecombine(SDNode *N) {
// We provide an Offset so that we can create bitwidths that won't overflow. // We provide an Offset so that we can create bitwidths that won't overflow.
static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) { static void zeroExtendToMatch(APInt &LHS, APInt &RHS, unsigned Offset = 0) {
unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth()); unsigned Bits = Offset + std::max(LHS.getBitWidth(), RHS.getBitWidth());
LHS = LHS.zextOrSelf(Bits); LHS = LHS.zext(Bits);
RHS = RHS.zextOrSelf(Bits); RHS = RHS.zext(Bits);
} }
// Return true if this node is a setcc, or is a select_cc // Return true if this node is a setcc, or is a select_cc
@ -4970,8 +4970,7 @@ static SDValue isSaturatingMinMax(SDValue N0, SDValue N1, SDValue N2,
return 0; return 0;
const APInt &C1 = N1C->getAPIntValue(); const APInt &C1 = N1C->getAPIntValue();
const APInt &C2 = N3C->getAPIntValue(); const APInt &C2 = N3C->getAPIntValue();
if (C1.getBitWidth() < C2.getBitWidth() || if (C1.getBitWidth() < C2.getBitWidth() || C1 != C2.sext(C1.getBitWidth()))
C1 != C2.sextOrSelf(C1.getBitWidth()))
return 0; return 0;
return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0); return CC == ISD::SETLT ? ISD::SMIN : (CC == ISD::SETGT ? ISD::SMAX : 0);
}; };
@ -5078,7 +5077,7 @@ static SDValue PerformUMinFpToSatCombine(SDValue N0, SDValue N1, SDValue N2,
const APInt &C1 = N1C->getAPIntValue(); const APInt &C1 = N1C->getAPIntValue();
const APInt &C3 = N3C->getAPIntValue(); const APInt &C3 = N3C->getAPIntValue();
if (!(C1 + 1).isPowerOf2() || C1.getBitWidth() < C3.getBitWidth() || if (!(C1 + 1).isPowerOf2() || C1.getBitWidth() < C3.getBitWidth() ||
C1 != C3.zextOrSelf(C1.getBitWidth())) C1 != C3.zext(C1.getBitWidth()))
return SDValue(); return SDValue();
unsigned BW = (C1 + 1).exactLogBase2(); unsigned BW = (C1 + 1).exactLogBase2();

8
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -466,9 +466,9 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
APInt Val; APInt Val;
if (TLI->signExtendConstant(CI)) if (TLI->signExtendConstant(CI))
Val = CI->getValue().sextOrSelf(BitWidth); Val = CI->getValue().sext(BitWidth);
else else
Val = CI->getValue().zextOrSelf(BitWidth); Val = CI->getValue().zext(BitWidth);
DestLOI.NumSignBits = Val.getNumSignBits(); DestLOI.NumSignBits = Val.getNumSignBits();
DestLOI.Known = KnownBits::makeConstant(Val); DestLOI.Known = KnownBits::makeConstant(Val);
} else { } else {
@ -502,9 +502,9 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) { if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
APInt Val; APInt Val;
if (TLI->signExtendConstant(CI)) if (TLI->signExtendConstant(CI))
Val = CI->getValue().sextOrSelf(BitWidth); Val = CI->getValue().sext(BitWidth);
else else
Val = CI->getValue().zextOrSelf(BitWidth); Val = CI->getValue().zext(BitWidth);
DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits()); DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
DestLOI.Known.Zero &= ~Val; DestLOI.Known.Zero &= ~Val;
DestLOI.Known.One &= Val; DestLOI.Known.One &= Val;

2
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1540,7 +1540,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VSCALE(SDNode *N) {
EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT VT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue(); APInt MulImm = cast<ConstantSDNode>(N->getOperand(0))->getAPIntValue();
return DAG.getVScale(SDLoc(N), VT, MulImm.sextOrSelf(VT.getSizeInBits())); return DAG.getVScale(SDLoc(N), VT, MulImm.sext(VT.getSizeInBits()));
} }
SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {

29
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -141,11 +141,11 @@ bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) {
unsigned EltSize = unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits(); N->getValueType(0).getVectorElementType().getSizeInBits();
if (auto *Op0 = dyn_cast<ConstantSDNode>(N->getOperand(0))) { if (auto *Op0 = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
SplatVal = Op0->getAPIntValue().truncOrSelf(EltSize); SplatVal = Op0->getAPIntValue().trunc(EltSize);
return true; return true;
} }
if (auto *Op0 = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) { if (auto *Op0 = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) {
SplatVal = Op0->getValueAPF().bitcastToAPInt().truncOrSelf(EltSize); SplatVal = Op0->getValueAPF().bitcastToAPInt().trunc(EltSize);
return true; return true;
} }
} }
@ -2669,7 +2669,7 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
uint64_t Idx = V.getConstantOperandVal(1); uint64_t Idx = V.getConstantOperandVal(1);
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt UndefSrcElts; APInt UndefSrcElts;
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
if (isSplatValue(Src, DemandedSrcElts, UndefSrcElts, Depth + 1)) { if (isSplatValue(Src, DemandedSrcElts, UndefSrcElts, Depth + 1)) {
UndefElts = UndefSrcElts.extractBits(NumElts, Idx); UndefElts = UndefSrcElts.extractBits(NumElts, Idx);
return true; return true;
@ -2686,9 +2686,9 @@ bool SelectionDAG::isSplatValue(SDValue V, const APInt &DemandedElts,
return false; return false;
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt UndefSrcElts; APInt UndefSrcElts;
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts);
if (isSplatValue(Src, DemandedSrcElts, UndefSrcElts, Depth + 1)) { if (isSplatValue(Src, DemandedSrcElts, UndefSrcElts, Depth + 1)) {
UndefElts = UndefSrcElts.truncOrSelf(NumElts); UndefElts = UndefSrcElts.trunc(NumElts);
return true; return true;
} }
break; break;
@ -3066,7 +3066,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break; break;
uint64_t Idx = Op.getConstantOperandVal(1); uint64_t Idx = Op.getConstantOperandVal(1);
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
Known = computeKnownBits(Src, DemandedSrcElts, Depth + 1); Known = computeKnownBits(Src, DemandedSrcElts, Depth + 1);
break; break;
} }
@ -3429,7 +3429,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
} }
case ISD::ZERO_EXTEND_VECTOR_INREG: { case ISD::ZERO_EXTEND_VECTOR_INREG: {
EVT InVT = Op.getOperand(0).getValueType(); EVT InVT = Op.getOperand(0).getValueType();
APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1); Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);
Known = Known.zext(BitWidth); Known = Known.zext(BitWidth);
break; break;
@ -3441,7 +3441,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
} }
case ISD::SIGN_EXTEND_VECTOR_INREG: { case ISD::SIGN_EXTEND_VECTOR_INREG: {
EVT InVT = Op.getOperand(0).getValueType(); EVT InVT = Op.getOperand(0).getValueType();
APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1); Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);
// If the sign bit is known to be zero or one, then sext will extend // If the sign bit is known to be zero or one, then sext will extend
// it to the top bits, else it will just zext. // it to the top bits, else it will just zext.
@ -3457,7 +3457,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
} }
case ISD::ANY_EXTEND_VECTOR_INREG: { case ISD::ANY_EXTEND_VECTOR_INREG: {
EVT InVT = Op.getOperand(0).getValueType(); EVT InVT = Op.getOperand(0).getValueType();
APInt InDemandedElts = DemandedElts.zextOrSelf(InVT.getVectorNumElements()); APInt InDemandedElts = DemandedElts.zext(InVT.getVectorNumElements());
Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1); Known = computeKnownBits(Op.getOperand(0), InDemandedElts, Depth + 1);
Known = Known.anyext(BitWidth); Known = Known.anyext(BitWidth);
break; break;
@ -4004,7 +4004,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
case ISD::SIGN_EXTEND_VECTOR_INREG: { case ISD::SIGN_EXTEND_VECTOR_INREG: {
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
EVT SrcVT = Src.getValueType(); EVT SrcVT = Src.getValueType();
APInt DemandedSrcElts = DemandedElts.zextOrSelf(SrcVT.getVectorNumElements()); APInt DemandedSrcElts = DemandedElts.zext(SrcVT.getVectorNumElements());
Tmp = VTBits - SrcVT.getScalarSizeInBits(); Tmp = VTBits - SrcVT.getScalarSizeInBits();
return ComputeNumSignBits(Src, DemandedSrcElts, Depth+1) + Tmp; return ComputeNumSignBits(Src, DemandedSrcElts, Depth+1) + Tmp;
} }
@ -4291,7 +4291,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, const APInt &DemandedElts,
break; break;
uint64_t Idx = Op.getConstantOperandVal(1); uint64_t Idx = Op.getConstantOperandVal(1);
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
return ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1); return ComputeNumSignBits(Src, DemandedSrcElts, Depth + 1);
} }
case ISD::CONCAT_VECTORS: { case ISD::CONCAT_VECTORS: {
@ -5573,7 +5573,7 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
for (unsigned I = 0, E = DstBits.size(); I != E; ++I) { for (unsigned I = 0, E = DstBits.size(); I != E; ++I) {
if (DstUndefs[I]) if (DstUndefs[I])
continue; continue;
Ops[I] = getConstant(DstBits[I].sextOrSelf(BVEltBits), DL, BVEltVT); Ops[I] = getConstant(DstBits[I].sext(BVEltBits), DL, BVEltVT);
} }
return getBitcast(VT, getBuildVector(BVVT, DL, Ops)); return getBitcast(VT, getBuildVector(BVVT, DL, Ops));
} }
@ -11459,9 +11459,8 @@ bool BuildVectorSDNode::getConstantRawBits(
auto *CInt = dyn_cast<ConstantSDNode>(Op); auto *CInt = dyn_cast<ConstantSDNode>(Op);
auto *CFP = dyn_cast<ConstantFPSDNode>(Op); auto *CFP = dyn_cast<ConstantFPSDNode>(Op);
assert((CInt || CFP) && "Unknown constant"); assert((CInt || CFP) && "Unknown constant");
SrcBitElements[I] = SrcBitElements[I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
CInt ? CInt->getAPIntValue().truncOrSelf(SrcEltSizeInBits) : CFP->getValueAPF().bitcastToAPInt();
: CFP->getValueAPF().bitcastToAPInt();
} }
// Recast to dst width. // Recast to dst width.

22
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1118,7 +1118,7 @@ bool TargetLowering::SimplifyDemandedBits(
KnownBits SrcKnown; KnownBits SrcKnown;
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
unsigned SrcBitWidth = Src.getScalarValueSizeInBits(); unsigned SrcBitWidth = Src.getScalarValueSizeInBits();
APInt SrcDemandedBits = DemandedBits.zextOrSelf(SrcBitWidth); APInt SrcDemandedBits = DemandedBits.zext(SrcBitWidth);
if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1)) if (SimplifyDemandedBits(Src, SrcDemandedBits, SrcKnown, TLO, Depth + 1))
return true; return true;
@ -1234,7 +1234,7 @@ bool TargetLowering::SimplifyDemandedBits(
break; break;
uint64_t Idx = Op.getConstantOperandVal(1); uint64_t Idx = Op.getConstantOperandVal(1);
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, Known, TLO, if (SimplifyDemandedBits(Src, DemandedBits, DemandedSrcElts, Known, TLO,
Depth + 1)) Depth + 1))
@ -2114,7 +2114,7 @@ bool TargetLowering::SimplifyDemandedBits(
} }
APInt InDemandedBits = DemandedBits.trunc(InBits); APInt InDemandedBits = DemandedBits.trunc(InBits);
APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); APInt InDemandedElts = DemandedElts.zext(InElts);
if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
Depth + 1)) Depth + 1))
return true; return true;
@ -2151,7 +2151,7 @@ bool TargetLowering::SimplifyDemandedBits(
} }
APInt InDemandedBits = DemandedBits.trunc(InBits); APInt InDemandedBits = DemandedBits.trunc(InBits);
APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); APInt InDemandedElts = DemandedElts.zext(InElts);
// Since some of the sign extended bits are demanded, we know that the sign // Since some of the sign extended bits are demanded, we know that the sign
// bit is demanded. // bit is demanded.
@ -2195,7 +2195,7 @@ bool TargetLowering::SimplifyDemandedBits(
return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src)); return TLO.CombineTo(Op, TLO.DAG.getBitcast(VT, Src));
APInt InDemandedBits = DemandedBits.trunc(InBits); APInt InDemandedBits = DemandedBits.trunc(InBits);
APInt InDemandedElts = DemandedElts.zextOrSelf(InElts); APInt InDemandedElts = DemandedElts.zext(InElts);
if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO, if (SimplifyDemandedBits(Src, InDemandedBits, InDemandedElts, Known, TLO,
Depth + 1)) Depth + 1))
return true; return true;
@ -2924,7 +2924,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
break; break;
uint64_t Idx = Op.getConstantOperandVal(1); uint64_t Idx = Op.getConstantOperandVal(1);
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts).shl(Idx); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts).shl(Idx);
APInt SrcUndef, SrcZero; APInt SrcUndef, SrcZero;
if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
@ -3083,7 +3083,7 @@ bool TargetLowering::SimplifyDemandedVectorElts(
APInt SrcUndef, SrcZero; APInt SrcUndef, SrcZero;
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
unsigned NumSrcElts = Src.getValueType().getVectorNumElements(); unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
APInt DemandedSrcElts = DemandedElts.zextOrSelf(NumSrcElts); APInt DemandedSrcElts = DemandedElts.zext(NumSrcElts);
if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO, if (SimplifyDemandedVectorElts(Src, DemandedSrcElts, SrcUndef, SrcZero, TLO,
Depth + 1)) Depth + 1))
return true; return true;
@ -9358,11 +9358,11 @@ SDValue TargetLowering::expandFP_TO_INT_SAT(SDNode *Node,
// floating-point values. // floating-point values.
APInt MinInt, MaxInt; APInt MinInt, MaxInt;
if (IsSigned) { if (IsSigned) {
MinInt = APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth); MinInt = APInt::getSignedMinValue(SatWidth).sext(DstWidth);
MaxInt = APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth); MaxInt = APInt::getSignedMaxValue(SatWidth).sext(DstWidth);
} else { } else {
MinInt = APInt::getMinValue(SatWidth).zextOrSelf(DstWidth); MinInt = APInt::getMinValue(SatWidth).zext(DstWidth);
MaxInt = APInt::getMaxValue(SatWidth).zextOrSelf(DstWidth); MaxInt = APInt::getMaxValue(SatWidth).zext(DstWidth);
} }
// We cannot risk emitting FP_TO_XINT nodes with a source VT of f16, as // We cannot risk emitting FP_TO_XINT nodes with a source VT of f16, as

16
llvm/lib/IR/ConstantRange.cpp
View File

@ -739,15 +739,23 @@ ConstantRange ConstantRange::castOp(Instruction::CastOps CastOp,
case Instruction::UIToFP: { case Instruction::UIToFP: {
// TODO: use input range if available // TODO: use input range if available
auto BW = getBitWidth(); auto BW = getBitWidth();
APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth); APInt Min = APInt::getMinValue(BW);
APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth); APInt Max = APInt::getMaxValue(BW);
if (ResultBitWidth > BW) {
Min = Min.zext(ResultBitWidth);
Max = Max.zext(ResultBitWidth);
}
return ConstantRange(std::move(Min), std::move(Max)); return ConstantRange(std::move(Min), std::move(Max));
} }
case Instruction::SIToFP: { case Instruction::SIToFP: {
// TODO: use input range if available // TODO: use input range if available
auto BW = getBitWidth(); auto BW = getBitWidth();
APInt SMin = APInt::getSignedMinValue(BW).sextOrSelf(ResultBitWidth); APInt SMin = APInt::getSignedMinValue(BW);
APInt SMax = APInt::getSignedMaxValue(BW).sextOrSelf(ResultBitWidth); APInt SMax = APInt::getSignedMaxValue(BW);
if (ResultBitWidth > BW) {
SMin = SMin.sext(ResultBitWidth);
SMax = SMax.sext(ResultBitWidth);
}
return ConstantRange(std::move(SMin), std::move(SMax)); return ConstantRange(std::move(SMin), std::move(SMax));
} }
case Instruction::FPTrunc: case Instruction::FPTrunc:

20
llvm/lib/Support/APFixedPoint.cpp
View File

@ -233,11 +233,11 @@ APFixedPoint APFixedPoint::mul(const APFixedPoint &Other,
// Widen the LHS and RHS so we can perform a full multiplication. // Widen the LHS and RHS so we can perform a full multiplication.
unsigned Wide = CommonFXSema.getWidth() * 2; unsigned Wide = CommonFXSema.getWidth() * 2;
if (CommonFXSema.isSigned()) { if (CommonFXSema.isSigned()) {
ThisVal = ThisVal.sextOrSelf(Wide); ThisVal = ThisVal.sext(Wide);
OtherVal = OtherVal.sextOrSelf(Wide); OtherVal = OtherVal.sext(Wide);
} else { } else {
ThisVal = ThisVal.zextOrSelf(Wide); ThisVal = ThisVal.zext(Wide);
OtherVal = OtherVal.zextOrSelf(Wide); OtherVal = OtherVal.zext(Wide);
} }
// Perform the full multiplication and downscale to get the same scale. // Perform the full multiplication and downscale to get the same scale.
@ -290,11 +290,11 @@ APFixedPoint APFixedPoint::div(const APFixedPoint &Other,
// Widen the LHS and RHS so we can perform a full division. // Widen the LHS and RHS so we can perform a full division.
unsigned Wide = CommonFXSema.getWidth() * 2; unsigned Wide = CommonFXSema.getWidth() * 2;
if (CommonFXSema.isSigned()) { if (CommonFXSema.isSigned()) {
ThisVal = ThisVal.sextOrSelf(Wide); ThisVal = ThisVal.sext(Wide);
OtherVal = OtherVal.sextOrSelf(Wide); OtherVal = OtherVal.sext(Wide);
} else { } else {
ThisVal = ThisVal.zextOrSelf(Wide); ThisVal = ThisVal.zext(Wide);
OtherVal = OtherVal.zextOrSelf(Wide); OtherVal = OtherVal.zext(Wide);
} }
// Upscale to compensate for the loss of precision from division, and // Upscale to compensate for the loss of precision from division, and
@ -340,9 +340,9 @@ APFixedPoint APFixedPoint::shl(unsigned Amt, bool *Overflow) const {
// Widen the LHS. // Widen the LHS.
unsigned Wide = Sema.getWidth() * 2; unsigned Wide = Sema.getWidth() * 2;
if (Sema.isSigned()) if (Sema.isSigned())
ThisVal = ThisVal.sextOrSelf(Wide); ThisVal = ThisVal.sext(Wide);
else else
ThisVal = ThisVal.zextOrSelf(Wide); ThisVal = ThisVal.zext(Wide);
// Clamp the shift amount at the original width, and perform the shift. // Clamp the shift amount at the original width, and perform the shift.
Amt = std::min(Amt, ThisVal.getBitWidth()); Amt = std::min(Amt, ThisVal.getBitWidth());

4
llvm/lib/Support/APInt.cpp
View File

@ -343,7 +343,7 @@ void APInt::flipAllBitsSlowCase() {
/// In the slow case, we know the result is large. /// In the slow case, we know the result is large.
APInt APInt::concatSlowCase(const APInt &NewLSB) const { APInt APInt::concatSlowCase(const APInt &NewLSB) const {
unsigned NewWidth = getBitWidth() + NewLSB.getBitWidth(); unsigned NewWidth = getBitWidth() + NewLSB.getBitWidth();
APInt Result = NewLSB.zextOrSelf(NewWidth); APInt Result = NewLSB.zext(NewWidth);
Result.insertBits(*this, NewLSB.getBitWidth()); Result.insertBits(*this, NewLSB.getBitWidth());
return Result; return Result;
} }
@ -612,7 +612,7 @@ APInt APInt::getLoBits(unsigned numBits) const {
APInt APInt::getSplat(unsigned NewLen, const APInt &V) { APInt APInt::getSplat(unsigned NewLen, const APInt &V) {
assert(NewLen >= V.getBitWidth() && "Can't splat to smaller bit width!"); assert(NewLen >= V.getBitWidth() && "Can't splat to smaller bit width!");
APInt Val = V.zextOrSelf(NewLen); APInt Val = V.zext(NewLen);
for (unsigned I = V.getBitWidth(); I < NewLen; I <<= 1) for (unsigned I = V.getBitWidth(); I < NewLen; I <<= 1)
Val |= Val << I; Val |= Val << I;

4
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -3148,7 +3148,7 @@ bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm,
SDLoc DL(N); SDLoc DL(N);
uint64_t Val = cast<ConstantSDNode>(N) uint64_t Val = cast<ConstantSDNode>(N)
->getAPIntValue() ->getAPIntValue()
.truncOrSelf(VT.getFixedSizeInBits()) .trunc(VT.getFixedSizeInBits())
.getZExtValue(); .getZExtValue();
switch (VT.SimpleTy) { switch (VT.SimpleTy) {
@ -3188,7 +3188,7 @@ bool AArch64DAGToDAGISel::SelectSVECpyDupImm(SDValue N, MVT VT, SDValue &Imm,
SDLoc DL(N); SDLoc DL(N);
int64_t Val = cast<ConstantSDNode>(N) int64_t Val = cast<ConstantSDNode>(N)
->getAPIntValue() ->getAPIntValue()
.truncOrSelf(VT.getFixedSizeInBits()) .trunc(VT.getFixedSizeInBits())
.getSExtValue(); .getSExtValue();
switch (VT.SimpleTy) { switch (VT.SimpleTy) {

19
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -3593,17 +3593,14 @@ AArch64TargetLowering::LowerVectorFP_TO_INT_SAT(SDValue Op,
SDValue Sat; SDValue Sat;
if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) {
SDValue MinC = DAG.getConstant( SDValue MinC = DAG.getConstant(
APInt::getSignedMaxValue(SatWidth).sextOrSelf(SrcElementWidth), DL, APInt::getSignedMaxValue(SatWidth).sext(SrcElementWidth), DL, IntVT);
IntVT);
SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC); SDValue Min = DAG.getNode(ISD::SMIN, DL, IntVT, NativeCvt, MinC);
SDValue MaxC = DAG.getConstant( SDValue MaxC = DAG.getConstant(
APInt::getSignedMinValue(SatWidth).sextOrSelf(SrcElementWidth), DL, APInt::getSignedMinValue(SatWidth).sext(SrcElementWidth), DL, IntVT);
IntVT);
Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC); Sat = DAG.getNode(ISD::SMAX, DL, IntVT, Min, MaxC);
} else { } else {
SDValue MinC = DAG.getConstant( SDValue MinC = DAG.getConstant(
APInt::getAllOnesValue(SatWidth).zextOrSelf(SrcElementWidth), DL, APInt::getAllOnesValue(SatWidth).zext(SrcElementWidth), DL, IntVT);
IntVT);
Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC); Sat = DAG.getNode(ISD::UMIN, DL, IntVT, NativeCvt, MinC);
} }
@ -3652,14 +3649,14 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
SDValue Sat; SDValue Sat;
if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) { if (Op.getOpcode() == ISD::FP_TO_SINT_SAT) {
SDValue MinC = DAG.getConstant( SDValue MinC = DAG.getConstant(
APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth), DL, DstVT); APInt::getSignedMaxValue(SatWidth).sext(DstWidth), DL, DstVT);
SDValue Min = DAG.getNode(ISD::SMIN, DL, DstVT, NativeCvt, MinC); SDValue Min = DAG.getNode(ISD::SMIN, DL, DstVT, NativeCvt, MinC);
SDValue MaxC = DAG.getConstant( SDValue MaxC = DAG.getConstant(
APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth), DL, DstVT); APInt::getSignedMinValue(SatWidth).sext(DstWidth), DL, DstVT);
Sat = DAG.getNode(ISD::SMAX, DL, DstVT, Min, MaxC); Sat = DAG.getNode(ISD::SMAX, DL, DstVT, Min, MaxC);
} else { } else {
SDValue MinC = DAG.getConstant( SDValue MinC = DAG.getConstant(
APInt::getAllOnesValue(SatWidth).zextOrSelf(DstWidth), DL, DstVT); APInt::getAllOnesValue(SatWidth).zext(DstWidth), DL, DstVT);
Sat = DAG.getNode(ISD::UMIN, DL, DstVT, NativeCvt, MinC); Sat = DAG.getNode(ISD::UMIN, DL, DstVT, NativeCvt, MinC);
} }
@ -12061,8 +12058,8 @@ SDValue AArch64TargetLowering::LowerVSCALE(SDValue Op,
SDLoc DL(Op); SDLoc DL(Op);
APInt MulImm = cast<ConstantSDNode>(Op.getOperand(0))->getAPIntValue(); APInt MulImm = cast<ConstantSDNode>(Op.getOperand(0))->getAPIntValue();
return DAG.getZExtOrTrunc(DAG.getVScale(DL, MVT::i64, MulImm.sextOrSelf(64)), return DAG.getZExtOrTrunc(DAG.getVScale(DL, MVT::i64, MulImm.sext(64)), DL,
DL, VT); VT);
} }
/// Set the IntrinsicInfo for the `aarch64_sve_st<N>` intrinsics. /// Set the IntrinsicInfo for the `aarch64_sve_st<N>` intrinsics.

2
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
View File

@ -135,7 +135,7 @@ bool matchAArch64MulConstCombine(
if (!Const) if (!Const)
return false; return false;
const APInt ConstValue = Const->Value.sextOrSelf(Ty.getSizeInBits()); APInt ConstValue = Const->Value.sext(Ty.getSizeInBits());
// The following code is ported from AArch64ISelLowering. // The following code is ported from AArch64ISelLowering.
// Multiplication of a power of two plus/minus one can be done more // Multiplication of a power of two plus/minus one can be done more
// cheaply as as shift+add/sub. For now, this is true unilaterally. If // cheaply as as shift+add/sub. For now, this is true unilaterally. If

2
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -2507,7 +2507,7 @@ bool AMDGPUInstructionSelector::selectG_PTRMASK(MachineInstr &I) const {
// Try to avoid emitting a bit operation when we only need to touch half of // Try to avoid emitting a bit operation when we only need to touch half of
// the 64-bit pointer. // the 64-bit pointer.
APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zextOrSelf(64); APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zext(64);
const APInt MaskHi32 = APInt::getHighBitsSet(64, 32); const APInt MaskHi32 = APInt::getHighBitsSet(64, 32);
const APInt MaskLo32 = APInt::getLowBitsSet(64, 32); const APInt MaskLo32 = APInt::getLowBitsSet(64, 32);

14
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
View File

@ -1217,8 +1217,8 @@ bool MachineConstEvaluator::evaluateCMPii(uint32_t Cmp, const APInt &A1,
unsigned W2 = A2.getBitWidth(); unsigned W2 = A2.getBitWidth();
unsigned MaxW = (W1 >= W2) ? W1 : W2; unsigned MaxW = (W1 >= W2) ? W1 : W2;
if (Cmp & Comparison::U) { if (Cmp & Comparison::U) {
const APInt Zx1 = A1.zextOrSelf(MaxW); APInt Zx1 = A1.zext(MaxW);
const APInt Zx2 = A2.zextOrSelf(MaxW); APInt Zx2 = A2.zext(MaxW);
if (Cmp & Comparison::L) if (Cmp & Comparison::L)
Result = Zx1.ult(Zx2); Result = Zx1.ult(Zx2);
else if (Cmp & Comparison::G) else if (Cmp & Comparison::G)
@ -1227,8 +1227,8 @@ bool MachineConstEvaluator::evaluateCMPii(uint32_t Cmp, const APInt &A1,
} }
// Signed comparison. // Signed comparison.
const APInt Sx1 = A1.sextOrSelf(MaxW); APInt Sx1 = A1.sext(MaxW);
const APInt Sx2 = A2.sextOrSelf(MaxW); APInt Sx2 = A2.sext(MaxW);
if (Cmp & Comparison::L) if (Cmp & Comparison::L)
Result = Sx1.slt(Sx2); Result = Sx1.slt(Sx2);
else if (Cmp & Comparison::G) else if (Cmp & Comparison::G)
@ -1813,7 +1813,7 @@ bool MachineConstEvaluator::evaluateSplati(const APInt &A1, unsigned Bits,
unsigned Count, APInt &Result) { unsigned Count, APInt &Result) {
assert(Count > 0); assert(Count > 0);
unsigned BW = A1.getBitWidth(), SW = Count*Bits; unsigned BW = A1.getBitWidth(), SW = Count*Bits;
APInt LoBits = (Bits < BW) ? A1.trunc(Bits) : A1.zextOrSelf(Bits); APInt LoBits = (Bits < BW) ? A1.trunc(Bits) : A1.zext(Bits);
if (Count > 1) if (Count > 1)
LoBits = LoBits.zext(SW); LoBits = LoBits.zext(SW);
@ -2538,9 +2538,9 @@ bool HexagonConstEvaluator::evaluateHexRSEQ32(RegisterSubReg RL, RegisterSubReg
} }
for (unsigned i = 0; i < HiVs.size(); ++i) { for (unsigned i = 0; i < HiVs.size(); ++i) {
APInt HV = HiVs[i].zextOrSelf(64) << 32; APInt HV = HiVs[i].zext(64) << 32;
for (unsigned j = 0; j < LoVs.size(); ++j) { for (unsigned j = 0; j < LoVs.size(); ++j) {
APInt LV = LoVs[j].zextOrSelf(64); APInt LV = LoVs[j].zext(64);
const Constant *C = intToConst(HV | LV); const Constant *C = intToConst(HV | LV);
Result.add(C); Result.add(C);
if (Result.isBottom()) if (Result.isBottom())

2
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -8616,7 +8616,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
break; break;
SDValue NewFMV = DAG.getNode(N->getOpcode(), DL, VT, Op0.getOperand(0)); SDValue NewFMV = DAG.getNode(N->getOpcode(), DL, VT, Op0.getOperand(0));
unsigned FPBits = N->getOpcode() == RISCVISD::FMV_X_ANYEXTW_RV64 ? 32 : 16; unsigned FPBits = N->getOpcode() == RISCVISD::FMV_X_ANYEXTW_RV64 ? 32 : 16;
APInt SignBit = APInt::getSignMask(FPBits).sextOrSelf(VT.getSizeInBits()); APInt SignBit = APInt::getSignMask(FPBits).sext(VT.getSizeInBits());
if (Op0.getOpcode() == ISD::FNEG) if (Op0.getOpcode() == ISD::FNEG)
return DAG.getNode(ISD::XOR, DL, VT, NewFMV, return DAG.getNode(ISD::XOR, DL, VT, NewFMV,
DAG.getConstant(SignBit, DL, VT)); DAG.getConstant(SignBit, DL, VT));

14
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -22496,11 +22496,11 @@ X86TargetLowering::LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const {
// floating-point values. // floating-point values.
APInt MinInt, MaxInt; APInt MinInt, MaxInt;
if (IsSigned) { if (IsSigned) {
MinInt = APInt::getSignedMinValue(SatWidth).sextOrSelf(DstWidth); MinInt = APInt::getSignedMinValue(SatWidth).sext(DstWidth);
MaxInt = APInt::getSignedMaxValue(SatWidth).sextOrSelf(DstWidth); MaxInt = APInt::getSignedMaxValue(SatWidth).sext(DstWidth);
} else { } else {
MinInt = APInt::getMinValue(SatWidth).zextOrSelf(DstWidth); MinInt = APInt::getMinValue(SatWidth).zext(DstWidth);
MaxInt = APInt::getMaxValue(SatWidth).zextOrSelf(DstWidth); MaxInt = APInt::getMaxValue(SatWidth).zext(DstWidth);
} }
APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT)); APFloat MinFloat(DAG.EVTToAPFloatSemantics(SrcVT));
@ -41443,7 +41443,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
TLO, Depth + 1)) TLO, Depth + 1))
return true; return true;
Known.Zero = KnownZero.zextOrSelf(BitWidth); Known.Zero = KnownZero.zext(BitWidth);
Known.Zero.setHighBits(BitWidth - NumElts); Known.Zero.setHighBits(BitWidth - NumElts);
// MOVMSK only uses the MSB from each vector element. // MOVMSK only uses the MSB from each vector element.
@ -43388,8 +43388,8 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG,
uint64_t Idx = CIdx->getZExtValue(); uint64_t Idx = CIdx->getZExtValue();
if (UndefVecElts[Idx]) if (UndefVecElts[Idx])
return IsPextr ? DAG.getConstant(0, dl, VT) : DAG.getUNDEF(VT); return IsPextr ? DAG.getConstant(0, dl, VT) : DAG.getUNDEF(VT);
return DAG.getConstant(EltBits[Idx].zextOrSelf(VT.getScalarSizeInBits()), return DAG.getConstant(EltBits[Idx].zext(VT.getScalarSizeInBits()), dl,
dl, VT); VT);
} }
} }

5
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
View File

@ -3813,7 +3813,7 @@ InstructionCost X86TTIImpl::getScalarizationOverhead(VectorType *Ty,
assert(CostValue >= 0 && "Negative cost!"); assert(CostValue >= 0 && "Negative cost!");
unsigned Num128Lanes = SizeInBits / 128 * CostValue; unsigned Num128Lanes = SizeInBits / 128 * CostValue;
unsigned NumElts = LT.second.getVectorNumElements() * CostValue; unsigned NumElts = LT.second.getVectorNumElements() * CostValue;
APInt WidenedDemandedElts = DemandedElts.zextOrSelf(NumElts); APInt WidenedDemandedElts = DemandedElts.zext(NumElts);
unsigned Scale = NumElts / Num128Lanes; unsigned Scale = NumElts / Num128Lanes;
// We iterate each 128-lane, and check if we need a // We iterate each 128-lane, and check if we need a
// extracti128/inserti128 for this 128-lane. // extracti128/inserti128 for this 128-lane.
@ -3973,8 +3973,7 @@ X86TTIImpl::getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
// if all elements that will form a single Dst vector aren't demanded, // if all elements that will form a single Dst vector aren't demanded,
// then we won't need to do that shuffle, so adjust the cost accordingly. // then we won't need to do that shuffle, so adjust the cost accordingly.
APInt DemandedDstVectors = APIntOps::ScaleBitMask( APInt DemandedDstVectors = APIntOps::ScaleBitMask(
DemandedDstElts.zextOrSelf(NumDstVectors * NumEltsPerDstVec), DemandedDstElts.zext(NumDstVectors * NumEltsPerDstVec), NumDstVectors);
NumDstVectors);
unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation(); unsigned NumDstVectorsDemanded = DemandedDstVectors.countPopulation();
InstructionCost SingleShuffleCost = InstructionCost SingleShuffleCost =

2
llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
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@ -772,7 +772,7 @@ static bool isObjectSizeLessThanOrEq(Value *V, uint64_t MaxSize,
uint64_t TypeSize = DL.getTypeAllocSize(AI->getAllocatedType()); uint64_t TypeSize = DL.getTypeAllocSize(AI->getAllocatedType());
// Make sure that, even if the multiplication below would wrap as an // Make sure that, even if the multiplication below would wrap as an
// uint64_t, we still do the right thing. // uint64_t, we still do the right thing.
if ((CS->getValue().zextOrSelf(128)*APInt(128, TypeSize)).ugt(MaxSize)) if ((CS->getValue().zext(128) * APInt(128, TypeSize)).ugt(MaxSize))
return false; return false;
continue; continue;
} }

3
llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
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@ -741,8 +741,7 @@ static bool narrowSDivOrSRem(BinaryOperator *Instr, LazyValueInfo *LVI) {
// sdiv/srem is UB if divisor is -1 and divident is INT_MIN, so unless we can // sdiv/srem is UB if divisor is -1 and divident is INT_MIN, so unless we can
// prove that such a combination is impossible, we need to bump the bitwidth. // prove that such a combination is impossible, we need to bump the bitwidth.
if (CRs[1]->contains(APInt::getAllOnes(OrigWidth)) && if (CRs[1]->contains(APInt::getAllOnes(OrigWidth)) &&
CRs[0]->contains( CRs[0]->contains(APInt::getSignedMinValue(MinSignedBits).sext(OrigWidth)))
APInt::getSignedMinValue(MinSignedBits).sextOrSelf(OrigWidth)))
++MinSignedBits; ++MinSignedBits;
// Don't shrink below 8 bits wide. // Don't shrink below 8 bits wide.

2
llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
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@ -496,7 +496,7 @@ bool Vectorizer::lookThroughComplexAddresses(Value *PtrA, Value *PtrB,
if (PtrDelta.urem(Stride) != 0) if (PtrDelta.urem(Stride) != 0)
return false; return false;
unsigned IdxBitWidth = OpA->getType()->getScalarSizeInBits(); unsigned IdxBitWidth = OpA->getType()->getScalarSizeInBits();
APInt IdxDiff = PtrDelta.udiv(Stride).zextOrSelf(IdxBitWidth); APInt IdxDiff = PtrDelta.udiv(Stride).zext(IdxBitWidth);
// Only look through a ZExt/SExt. // Only look through a ZExt/SExt.
if (!isa<SExtInst>(OpA) && !isa<ZExtInst>(OpA)) if (!isa<SExtInst>(OpA) && !isa<ZExtInst>(OpA))

4
llvm/test/TableGen/VarLenEncoder.td
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@ -65,7 +65,7 @@ def FOO32 : MyVarInst<MemOp32<"src">>;
// CHECK: UINT64_C(46848), // FOO32 // CHECK: UINT64_C(46848), // FOO32
// CHECK-LABEL: case ::FOO16: { // CHECK-LABEL: case ::FOO16: {
// CHECK: Scratch = Scratch.zextOrSelf(41); // CHECK: Scratch = Scratch.zext(41);
// src.reg // src.reg
// CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI); // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
// CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0); // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
@ -83,7 +83,7 @@ def FOO32 : MyVarInst<MemOp32<"src">>;
// CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39); // CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39);
// CHECK-LABEL: case ::FOO32: { // CHECK-LABEL: case ::FOO32: {
// CHECK: Scratch = Scratch.zextOrSelf(57); // CHECK: Scratch = Scratch.zext(57);
// src.reg // src.reg
// CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI); // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
// CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0); // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);

2
llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
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@ -424,7 +424,7 @@ std::string VarLenCodeEmitterGen::getInstructionCaseForEncoding(
raw_string_ostream SS(Case); raw_string_ostream SS(Case);
// Resize the scratch buffer. // Resize the scratch buffer.
if (BitWidth && !VLI.isFixedValueOnly()) if (BitWidth && !VLI.isFixedValueOnly())
SS.indent(6) << "Scratch = Scratch.zextOrSelf(" << BitWidth << ");\n"; SS.indent(6) << "Scratch = Scratch.zext(" << BitWidth << ");\n";
// Populate based value. // Populate based value.
SS.indent(6) << "Inst = getInstBits(opcode);\n"; SS.indent(6) << "Inst = getInstBits(opcode);\n";

2
polly/lib/CodeGen/IslExprBuilder.cpp
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@ -765,7 +765,7 @@ Value *IslExprBuilder::createInt(__isl_take isl_ast_expr *Expr) {
else else
T = Builder.getIntNTy(BitWidth); T = Builder.getIntNTy(BitWidth);
APValue = APValue.sextOrSelf(T->getBitWidth()); APValue = APValue.sext(T->getBitWidth());
V = ConstantInt::get(T, APValue); V = ConstantInt::get(T, APValue);
isl_ast_expr_free(Expr); isl_ast_expr_free(Expr);