[GISel] handle CTTZ in computeKnownBits (#181474)
Addresses part of #150515. Adapted from the CTLZ code below this
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Aayush Sabharwal
GitHub
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6d033abb71
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6ce9e363e0
@ -690,6 +690,17 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
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}
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break;
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}
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case TargetOpcode::G_CTTZ:
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case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
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KnownBits SrcOpKnown;
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computeKnownBitsImpl(MI.getOperand(1).getReg(), SrcOpKnown, DemandedElts,
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Depth + 1);
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// If we have a known 1, its position is our upper bound
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unsigned PossibleTZ = SrcOpKnown.countMaxTrailingZeros();
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unsigned LowBits = llvm::bit_width(PossibleTZ);
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Known.Zero.setBitsFrom(LowBits);
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break;
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}
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case TargetOpcode::G_CTLZ:
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case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
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KnownBits SrcOpKnown;
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111
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-cttz.mir
Normal file
111
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-cttz.mir
Normal file
@ -0,0 +1,111 @@
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# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
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---
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name: CTTZNoKnown8
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZNoKnown8
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; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:000000000000???? SignBits:12
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%0:_(s8) = COPY $b0
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%1:_(s16) = G_CTTZ %0
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...
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---
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name: CTTZNoKnown16
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZNoKnown16
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; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:00000000000????? SignBits:11
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%0:_(s16) = COPY $h0
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%1:_(s16) = G_CTTZ %0
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...
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---
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name: CTTZNoKnown32
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZNoKnown32
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; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:0000000000?????? SignBits:10
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%0:_(s32) = COPY $s0
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%1:_(s16) = G_CTTZ %0
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...
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---
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name: CTTZHalfKnown8
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZHalfKnown8
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; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:00000100 SignBits:5
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; CHECK-NEXT: %2:_ KnownBits:?????1?? SignBits:1
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; CHECK-NEXT: %3:_ KnownBits:000000?? SignBits:6
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%0:_(s8) = COPY $b0
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%1:_(s8) = G_CONSTANT i8 4
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%2:_(s8) = G_OR %0, %1
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%3:_(s8) = G_CTTZ %2
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...
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---
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name: CTTZHalfKnown16
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZHalfKnown16
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; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
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; CHECK-NEXT: %1:_ KnownBits:0000000001000000 SignBits:9
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; CHECK-NEXT: %2:_ KnownBits:?????????1?????? SignBits:1
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; CHECK-NEXT: %3:_ KnownBits:0000000000000??? SignBits:13
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%0:_(s16) = COPY $h0
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%1:_(s16) = G_CONSTANT i16 64
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%2:_(s16) = G_OR %0, %1
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%3:_(s16) = G_CTTZ %2
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...
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---
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name: CTTZHalfConst8Zero
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZHalfConst8Zero
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; CHECK-NEXT: %0:_ KnownBits:00000000 SignBits:8
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; CHECK-NEXT: %1:_ KnownBits:0000???? SignBits:4
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%0:_(s8) = G_CONSTANT i8 0
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%1:_(s8) = G_CTTZ %0
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...
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---
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name: CTTZHalfConst16Zero
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZHalfConst16Zero
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; CHECK-NEXT: %0:_ KnownBits:0000000000000000 SignBits:16
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; CHECK-NEXT: %1:_ KnownBits:00000000000????? SignBits:11
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%0:_(s16) = G_CONSTANT i16 0
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%1:_(s16) = G_CTTZ %0
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...
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---
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name: CTTZHalfConst8
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZHalfConst8
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; CHECK-NEXT: %0:_ KnownBits:00000100 SignBits:5
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; CHECK-NEXT: %1:_ KnownBits:000000?? SignBits:6
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%0:_(s8) = G_CONSTANT i8 4
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%1:_(s8) = G_CTTZ %0
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...
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---
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name: CTTZHalfConst16
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body: |
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bb.1:
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; CHECK-LABEL: name: @CTTZHalfConst16
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; CHECK-NEXT: %0:_ KnownBits:0000000000000100 SignBits:13
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; CHECK-NEXT: %1:_ KnownBits:00000000000000?? SignBits:14
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%0:_(s16) = G_CONSTANT i16 4
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%1:_(s16) = G_CTTZ %0
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...
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@ -64,9 +64,7 @@ body: |
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[CTTZ_ZERO_UNDEF]], [[C]]
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[CTTZ_ZERO_UNDEF]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_CTTZ_ZERO_UNDEF %0
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%2:_(s32) = G_ZEXT %1
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@ -85,9 +83,7 @@ body: |
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s16) = G_CTTZ_ZERO_UNDEF %1
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@ -152,11 +148,8 @@ body: |
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[LSHR]](s32)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]
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; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $vgpr0
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@ -177,9 +170,7 @@ body: |
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s7) = G_TRUNC %0
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%2:_(s7) = G_CTTZ_ZERO_UNDEF %1
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@ -93,9 +93,7 @@ body: |
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s16) = G_CTTZ %1
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@ -169,11 +167,8 @@ body: |
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; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[C1]]
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF1]](s32)
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; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
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; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
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; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
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; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY2]], [[C]](s32)
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; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[SHL]]
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; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
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%0:_(<2 x s16>) = COPY $vgpr0
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@ -196,9 +191,7 @@ body: |
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; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[C]]
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; CHECK-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ_ZERO_UNDEF]](s32)
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; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
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; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
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; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s7) = G_TRUNC %0
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%2:_(s7) = G_CTTZ %1
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@ -1561,7 +1561,6 @@ define amdgpu_kernel void @v_cttz_i7_sel_eq_neg1(ptr addrspace(1) noalias %out,
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; GFX10-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
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; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, v1, 0x7f, vcc_lo
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; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-GISEL-NEXT: v_and_b32_e32 v0, 0x7f, v0
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; GFX10-GISEL-NEXT: global_store_byte v1, v0, s[0:1]
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; GFX10-GISEL-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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@ -18,9 +18,7 @@ body: |
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; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
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; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
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; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
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; X64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738367
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; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[CTTZ_ZERO_UNDEF]], [[C1]]
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; X64-NEXT: RET 0, implicit [[AND]](s64)
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; X64-NEXT: RET 0, implicit [[CTTZ_ZERO_UNDEF]](s64)
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;
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; X86-LABEL: name: test_cttz35
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; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
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@ -18,9 +18,7 @@ body: |
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; X64-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738368
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; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[C]]
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; X64-NEXT: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s64) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
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; X64-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 34359738367
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; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[CTTZ_ZERO_UNDEF]], [[C1]]
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; X64-NEXT: RET 0, implicit [[AND]](s64)
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; X64-NEXT: RET 0, implicit [[CTTZ_ZERO_UNDEF]](s64)
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;
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; X86-LABEL: name: test_cttz35
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; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
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