[AMDGPU] Select v_bfe_u32 for i8/i16 (and (srl x, c), mask) (#182446)
Combine i8 and i16 (and (srl x, c), mask) instructions to v_bfe_32. This optimization is skipped true_i16 targets. resolves issue #179494
This commit is contained in:
Vigneshwar Jayakumar
GitHub
parent
d62fbb6a96
commit
6e1aee4276
@ -441,8 +441,8 @@ def gi_bitcast_fpimm_to_i32 : GICustomOperandRenderer<"renderBitcastFPImm32">,
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def gi_bitcast_fpimm_to_i64 : GICustomOperandRenderer<"renderBitcastFPImm64">,
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GISDNodeXFormEquiv<bitcast_fpimm_to_i64>;
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def gi_IMMPopCount : GICustomOperandRenderer<"renderPopcntImm">,
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GISDNodeXFormEquiv<IMMPopCount>;
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def gi_IMMCountTrailingOnes : GICustomOperandRenderer<"renderCountTrailingOnesImm">,
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GISDNodeXFormEquiv<IMMCountTrailingOnes>;
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def gi_extract_cpol : GICustomOperandRenderer<"renderExtractCPol">,
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GISDNodeXFormEquiv<extract_cpol>;
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@ -7224,12 +7224,11 @@ void AMDGPUInstructionSelector::renderBitcastFPImm(MachineInstrBuilder &MIB,
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MIB.addImm(Op.getFPImm()->getValueAPF().bitcastToAPInt().getZExtValue());
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}
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void AMDGPUInstructionSelector::renderPopcntImm(MachineInstrBuilder &MIB,
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const MachineInstr &MI,
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int OpIdx) const {
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void AMDGPUInstructionSelector::renderCountTrailingOnesImm(
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MachineInstrBuilder &MIB, const MachineInstr &MI, int OpIdx) const {
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assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 &&
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"Expected G_CONSTANT");
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MIB.addImm(MI.getOperand(1).getCImm()->getValue().popcount());
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MIB.addImm(MI.getOperand(1).getCImm()->getValue().countTrailingOnes());
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}
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/// This only really exists to satisfy DAG type checking machinery, so is a
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@ -400,8 +400,8 @@ private:
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renderBitcastFPImm(MIB, MI, OpIdx);
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}
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void renderPopcntImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderCountTrailingOnesImm(MachineInstrBuilder &MIB,
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const MachineInstr &MI, int OpIdx) const;
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void renderExtractCPol(MachineInstrBuilder &MIB, const MachineInstr &MI,
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int OpIdx) const;
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void renderExtractSWZ(MachineInstrBuilder &MIB, const MachineInstr &MI,
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@ -4157,15 +4157,26 @@ def IMMZeroBasedBitfieldMask : ImmLeaf <i32, [{
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return isMask_32(Imm);
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}]>;
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def IMMPopCount : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(llvm::popcount(N->getZExtValue()), SDLoc(N),
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MVT::i32);
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def IMMZeroBasedBitfieldMask16 : ImmLeaf <i16, [{
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return isUInt<16>(Imm) && isMask_32(Imm);
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}]>;
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def IMMCountTrailingOnes : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(llvm::countr_one(N->getZExtValue()),
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SDLoc(N), MVT::i32);
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}]>;
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def : AMDGPUPat <
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(DivergentBinFrag<and> (i32 (srl i32:$src, i32:$rshift)),
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IMMZeroBasedBitfieldMask:$mask),
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(V_BFE_U32_e64 $src, $rshift, (i32 (IMMPopCount $mask)))
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(V_BFE_U32_e64 $src, $rshift, (i32 (IMMCountTrailingOnes $mask)))
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>;
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let True16Predicate = NotUseRealTrue16Insts in
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def : AMDGPUPat <
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(i16 (DivergentBinFrag<and> (srl_oneuse i16:$src, (i16 imm:$rshift)),
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IMMZeroBasedBitfieldMask16:$mask)),
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(V_BFE_U32_e64 $src, (i32 (as_i32timm $rshift)), (i32 (IMMCountTrailingOnes $mask)))
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>;
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// x & ((1 << y) - 1)
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141
llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
Normal file
141
llvm/test/CodeGen/AMDGPU/bfe-i8-i16.ll
Normal file
@ -0,0 +1,141 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefix=GFX9
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck %s --check-prefix=GFX12-TRUE16
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; Test that isel patterns recognize (and (lshr x, C), mask) for i8/i16
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; and lower it to v_bfe_u32 when real true16 instructions are not used.
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define i16 @bfe_i16(i16 %a) {
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; GFX9-LABEL: bfe_i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_bfe_u32 v0, v0, 4, 4
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: bfe_i16:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.l, 4, v0.l
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 15
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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%shr = lshr i16 %a, 4
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%and = and i16 %shr, 15
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ret i16 %and
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}
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; i8: 4 bits at offset 4.
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define i8 @bfe_i8(i8 %a) {
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; GFX9-LABEL: bfe_i8:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_bfe_u32 v0, v0, 4, 4
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: bfe_i8:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.l, 4, v0.l
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 15
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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%shr = lshr i8 %a, 4
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%and = and i8 %shr, 15
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ret i8 %and
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}
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; Negative: multiple uses of the shifted value should not match the one-use
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; narrow BFE pattern.
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define i16 @no_bfe_i16_multi_use(i16 %a) {
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; GFX9-LABEL: no_bfe_i16_multi_use:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_lshrrev_b16_e32 v0, 4, v0
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; GFX9-NEXT: v_and_b32_e32 v1, 15, v0
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; GFX9-NEXT: v_and_b32_e32 v0, 3, v0
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; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: no_bfe_i16_multi_use:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_lshrrev_b16 v0.l, 4, v0.l
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
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; GFX12-TRUE16-NEXT: v_and_b16 v0.h, v0.l, 15
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; GFX12-TRUE16-NEXT: v_and_b16 v0.l, v0.l, 3
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; GFX12-TRUE16-NEXT: v_xor_b16 v0.l, v0.h, v0.l
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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%shr = lshr i16 %a, 4
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%and0 = and i16 %shr, 15
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%and1 = and i16 %shr, 3
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%xor = xor i16 %and0, %and1
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ret i16 %xor
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}
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; Pure uniform (SGPR) case.
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define amdgpu_ps i16 @bfe_i16_uniform(i16 inreg %a) {
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; GFX9-LABEL: bfe_i16_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_bfe_u32 s0, s0, 0x40004
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX12-TRUE16-LABEL: bfe_i16_uniform:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_bfe_u32 s0, s0, 0x40004
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; GFX12-TRUE16-NEXT: ; return to shader part epilog
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%shr = lshr i16 %a, 4
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%and = and i16 %shr, 15
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ret i16 %and
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}
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define amdgpu_ps i8 @bfe_i8_uniform(i8 inreg %a) {
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; GFX9-LABEL: bfe_i8_uniform:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_bfe_u32 s0, s0, 0x40004
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; GFX9-NEXT: ; return to shader part epilog
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;
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; GFX12-TRUE16-LABEL: bfe_i8_uniform:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_bfe_u32 s0, s0, 0x40004
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; GFX12-TRUE16-NEXT: ; return to shader part epilog
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%shr = lshr i8 %a, 4
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%and = and i8 %shr, 15
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ret i8 %and
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}
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; Vector case: keep the packed shift/and lowering.
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define <2 x i16> @bfe_v2i16(<2 x i16> %a) {
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; GFX9-LABEL: bfe_v2i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_pk_lshrrev_b16 v0, 4, v0 op_sel_hi:[0,1]
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; GFX9-NEXT: v_and_b32_e32 v0, 0xf000f, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-TRUE16-LABEL: bfe_v2i16:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_expcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-TRUE16-NEXT: v_pk_lshrrev_b16 v0, 4, v0 op_sel_hi:[0,1]
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; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xf000f, v0
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; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
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%shr = lshr <2 x i16> %a, <i16 4, i16 4>
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%and = and <2 x i16> %shr, <i16 15, i16 15>
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ret <2 x i16> %and
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}
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@ -281,8 +281,7 @@ define <2 x i6> @bitcast_i12_to_v2i6(i12 %int) {
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_and_b32_e32 v2, 63, v0
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; GFX9-NEXT: v_lshrrev_b16_e32 v0, 6, v0
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; GFX9-NEXT: v_and_b32_e32 v1, 63, v0
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; GFX9-NEXT: v_bfe_u32 v1, v0, 6, 6
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; GFX9-NEXT: v_mov_b32_e32 v0, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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@ -306,10 +305,10 @@ define <2 x i6> @bitcast_i12_to_v2i6(i12 %int) {
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; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
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; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
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; GFX12-FAKE16-NEXT: v_lshrrev_b16 v1, 6, v0
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; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 63, v0
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; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 63, v0
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; GFX12-FAKE16-NEXT: v_bfe_u32 v1, v0, 6, 6
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; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 63, v1
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; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v2
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; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
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%bitcast = bitcast i12 %int to <2 x i6>
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ret <2 x i6> %bitcast
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@ -3479,16 +3479,14 @@ define <4 x i4> @load_v4i4(ptr addrspace(8) inreg %buf) {
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: buffer_load_ushort v0, off, s[16:19], 0
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; SDAG-NEXT: v_mov_b32_e32 v2, 15
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: buffer_store_short v0, off, s[0:3], s32
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; SDAG-NEXT: buffer_load_ushort v1, off, s[0:3], s32
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; SDAG-NEXT: buffer_load_ushort v2, off, s[0:3], s32
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; SDAG-NEXT: s_waitcnt vmcnt(0)
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; SDAG-NEXT: v_lshrrev_b16_e32 v4, 4, v1
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; SDAG-NEXT: v_and_b32_e32 v0, 15, v1
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; SDAG-NEXT: v_lshrrev_b16_e32 v3, 12, v1
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; SDAG-NEXT: v_and_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
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; SDAG-NEXT: v_and_b32_e32 v1, 15, v4
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; SDAG-NEXT: v_and_b32_e32 v0, 15, v2
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; SDAG-NEXT: v_lshrrev_b16_e32 v3, 12, v2
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; SDAG-NEXT: v_bfe_u32 v1, v2, 4, 4
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; SDAG-NEXT: v_bfe_u32 v2, v2, 8, 4
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; SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GISEL-LABEL: load_v4i4:
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@ -722,14 +722,14 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
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; SDAG: ; %bb.0: ; %fp-to-i-entry
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; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; SDAG-NEXT: v_mov_b32_e32 v4, v0
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; SDAG-NEXT: v_lshrrev_b16_e32 v8, 7, v4
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; SDAG-NEXT: v_bfe_u32 v8, v4, 7, 8
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; SDAG-NEXT: s_movk_i32 s4, 0x7e
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; SDAG-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-NEXT: v_mov_b32_e32 v2, 0
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; SDAG-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-NEXT: v_mov_b32_e32 v3, 0
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; SDAG-NEXT: v_cmp_gt_u16_sdwa s[4:5], v8, s4 src0_sel:BYTE_0 src1_sel:DWORD
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; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
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; SDAG-NEXT: v_cmp_lt_u16_e32 vcc, s4, v8
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; SDAG-NEXT: s_and_saveexec_b64 s[6:7], vcc
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; SDAG-NEXT: s_cbranch_execz .LBB6_6
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; SDAG-NEXT: ; %bb.1: ; %fp-to-i-if-check.exp.size
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; SDAG-NEXT: v_ashrrev_i16_e32 v0, 15, v4
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@ -740,15 +740,14 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
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; SDAG-NEXT: v_ashrrev_i32_e32 v6, 31, v7
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; SDAG-NEXT: v_or_b32_e32 v5, 1, v7
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; SDAG-NEXT: v_or_b32_e32 v4, 0x80, v0
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; SDAG-NEXT: v_cmp_gt_u16_sdwa s[8:9], v8, s5 src0_sel:BYTE_0 src1_sel:DWORD
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; SDAG-NEXT: v_cmp_lt_u16_e32 vcc, s5, v8
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; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1
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; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3
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; SDAG-NEXT: s_and_saveexec_b64 s[10:11], s[8:9]
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; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[10:11]
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; SDAG-NEXT: s_and_saveexec_b64 s[8:9], vcc
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; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
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; SDAG-NEXT: s_cbranch_execz .LBB6_3
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; SDAG-NEXT: ; %bb.2: ; %fp-to-i-if-exp.large
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; SDAG-NEXT: s_movk_i32 s5, 0xff7a
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; SDAG-NEXT: v_add_u16_sdwa v10, v8, s5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
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; SDAG-NEXT: v_add_u16_e32 v10, 0xff7a, v8
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; SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v4
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; SDAG-NEXT: v_mov_b32_e32 v1, s4
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; SDAG-NEXT: v_sub_u32_e32 v2, 64, v10
|
||||
@ -788,8 +787,7 @@ define i128 @fptosi_bf16_to_i128(bfloat %x) {
|
||||
; SDAG-NEXT: .LBB6_3: ; %Flow
|
||||
; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]
|
||||
; SDAG-NEXT: ; %bb.4: ; %fp-to-i-if-exp.small
|
||||
; SDAG-NEXT: s_movk_i32 s8, 0x86
|
||||
; SDAG-NEXT: v_sub_u16_sdwa v0, s8, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
||||
; SDAG-NEXT: v_sub_u16_e32 v0, 0x86, v8
|
||||
; SDAG-NEXT: v_lshrrev_b16_e32 v0, v0, v4
|
||||
; SDAG-NEXT: v_mul_hi_i32_i24_e32 v1, v0, v5
|
||||
; SDAG-NEXT: v_ashrrev_i32_e32 v2, 31, v1
|
||||
@ -936,28 +934,27 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
|
||||
; SDAG: ; %bb.0: ; %fp-to-i-entry
|
||||
; SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; SDAG-NEXT: v_mov_b32_e32 v4, v0
|
||||
; SDAG-NEXT: v_lshrrev_b16_e32 v5, 7, v4
|
||||
; SDAG-NEXT: v_bfe_u32 v5, v4, 7, 8
|
||||
; SDAG-NEXT: s_movk_i32 s4, 0x7e
|
||||
; SDAG-NEXT: v_mov_b32_e32 v0, 0
|
||||
; SDAG-NEXT: v_mov_b32_e32 v2, 0
|
||||
; SDAG-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SDAG-NEXT: v_mov_b32_e32 v3, 0
|
||||
; SDAG-NEXT: v_cmp_gt_u16_sdwa s[4:5], v5, s4 src0_sel:BYTE_0 src1_sel:DWORD
|
||||
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
||||
; SDAG-NEXT: v_cmp_lt_u16_e32 vcc, s4, v5
|
||||
; SDAG-NEXT: s_and_saveexec_b64 s[6:7], vcc
|
||||
; SDAG-NEXT: s_cbranch_execz .LBB7_6
|
||||
; SDAG-NEXT: ; %bb.1: ; %fp-to-i-if-check.exp.size
|
||||
; SDAG-NEXT: v_and_b32_e32 v0, 0x7f, v4
|
||||
; SDAG-NEXT: s_movk_i32 s4, 0x85
|
||||
; SDAG-NEXT: v_or_b32_e32 v4, 0x80, v0
|
||||
; SDAG-NEXT: v_cmp_gt_u16_sdwa s[4:5], v5, s4 src0_sel:BYTE_0 src1_sel:DWORD
|
||||
; SDAG-NEXT: v_cmp_lt_u16_e32 vcc, s4, v5
|
||||
; SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1
|
||||
; SDAG-NEXT: ; implicit-def: $vgpr2_vgpr3
|
||||
; SDAG-NEXT: s_and_saveexec_b64 s[8:9], s[4:5]
|
||||
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[8:9]
|
||||
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
||||
; SDAG-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
|
||||
; SDAG-NEXT: s_cbranch_execz .LBB7_3
|
||||
; SDAG-NEXT: ; %bb.2: ; %fp-to-i-if-exp.large
|
||||
; SDAG-NEXT: s_movk_i32 s4, 0xff7a
|
||||
; SDAG-NEXT: v_add_u16_sdwa v6, v5, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
|
||||
; SDAG-NEXT: v_add_u16_e32 v6, 0xff7a, v5
|
||||
; SDAG-NEXT: s_mov_b32 s4, 0
|
||||
; SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v4
|
||||
; SDAG-NEXT: v_mov_b32_e32 v1, s4
|
||||
@ -979,8 +976,7 @@ define i128 @fptoui_bf16_to_i128(bfloat %x) {
|
||||
; SDAG-NEXT: .LBB7_3: ; %Flow
|
||||
; SDAG-NEXT: s_andn2_saveexec_b64 s[4:5], s[8:9]
|
||||
; SDAG-NEXT: ; %bb.4: ; %fp-to-i-if-exp.small
|
||||
; SDAG-NEXT: s_movk_i32 s8, 0x86
|
||||
; SDAG-NEXT: v_sub_u16_sdwa v0, s8, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
|
||||
; SDAG-NEXT: v_sub_u16_e32 v0, 0x86, v5
|
||||
; SDAG-NEXT: v_mov_b32_e32 v2, 0
|
||||
; SDAG-NEXT: v_lshrrev_b16_e32 v0, v0, v4
|
||||
; SDAG-NEXT: v_mov_b32_e32 v3, 0
|
||||
|
||||
@ -2146,12 +2146,12 @@ define hidden void @trunc_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1
|
||||
; GFX10-NEXT: global_load_dword v9, v[2:3], off
|
||||
; GFX10-NEXT: v_mov_b32_e32 v0, 1
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(1)
|
||||
; GFX10-NEXT: v_and_b32_sdwa v1, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
||||
; GFX10-NEXT: v_and_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: v_and_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
|
||||
; GFX10-NEXT: v_lshlrev_b16 v1, 1, v1
|
||||
; GFX10-NEXT: v_lshlrev_b16 v2, 2, v0
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; GFX10-NEXT: v_bfe_u32 v1, v9, 8, 1
|
||||
; GFX10-NEXT: v_lshlrev_b16 v0, 1, v0
|
||||
; GFX10-NEXT: v_lshlrev_b16 v2, 2, v1
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
|
||||
; GFX10-NEXT: v_lshlrev_b16 v1, 3, v4
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v0, v2
|
||||
; GFX10-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
@ -2175,12 +2175,12 @@ define hidden void @trunc_store_div(ptr addrspace(1) %in0, ptr addrspace(1) %in1
|
||||
; GFX9-NEXT: v_mov_b32_e32 v0, 1
|
||||
; GFX9-NEXT: s_mov_b32 s4, 0x50205
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(1)
|
||||
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 3, v4
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_and_b32_sdwa v2, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
|
||||
; GFX9-NEXT: v_and_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
||||
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-NEXT: v_bfe_u32 v2, v9, 8, 1
|
||||
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 1, v0
|
||||
; GFX9-NEXT: v_perm_b32 v1, v9, v4, s4
|
||||
; GFX9-NEXT: v_lshlrev_b16_e32 v3, 3, v4
|
||||
; GFX9-NEXT: v_lshlrev_b16_e32 v4, 2, v2
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
|
||||
; GFX9-NEXT: v_or_b32_e32 v0, v0, v4
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user