[RISCV][IR] Implement verifier check for llvm.experimental.vp.splice immediate. (#147458)
This applies the same check as llvm.vector.splice which checks that the immediate is in the range [-VL, VL-1] where VL is the minimum vector length. If vscale_range is available, the lower bound is used to increase the known minimum vector length for this check. This ensures the immediate is in range for any possible value of vscale that satisfies the vscale_range.
This commit is contained in:
Craig Topper
GitHub
parent
d3d77f71aa
commit
6ee87759e3
@ -6939,20 +6939,44 @@ void Verifier::visitVPIntrinsic(VPIntrinsic &VPI) {
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break;
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}
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}
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if (VPI.getIntrinsicID() == Intrinsic::vp_fcmp) {
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switch (VPI.getIntrinsicID()) {
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case Intrinsic::vp_fcmp: {
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auto Pred = cast<VPCmpIntrinsic>(&VPI)->getPredicate();
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Check(CmpInst::isFPPredicate(Pred),
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"invalid predicate for VP FP comparison intrinsic", &VPI);
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break;
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}
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if (VPI.getIntrinsicID() == Intrinsic::vp_icmp) {
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case Intrinsic::vp_icmp: {
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auto Pred = cast<VPCmpIntrinsic>(&VPI)->getPredicate();
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Check(CmpInst::isIntPredicate(Pred),
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"invalid predicate for VP integer comparison intrinsic", &VPI);
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break;
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}
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if (VPI.getIntrinsicID() == Intrinsic::vp_is_fpclass) {
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case Intrinsic::vp_is_fpclass: {
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auto TestMask = cast<ConstantInt>(VPI.getOperand(1));
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Check((TestMask->getZExtValue() & ~static_cast<unsigned>(fcAllFlags)) == 0,
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"unsupported bits for llvm.vp.is.fpclass test mask");
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break;
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}
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case Intrinsic::experimental_vp_splice: {
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VectorType *VecTy = cast<VectorType>(VPI.getType());
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int64_t Idx = cast<ConstantInt>(VPI.getArgOperand(2))->getSExtValue();
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int64_t KnownMinNumElements = VecTy->getElementCount().getKnownMinValue();
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if (VPI.getParent() && VPI.getParent()->getParent()) {
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AttributeList Attrs = VPI.getParent()->getParent()->getAttributes();
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if (Attrs.hasFnAttr(Attribute::VScaleRange))
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KnownMinNumElements *= Attrs.getFnAttrs().getVScaleRangeMin();
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}
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Check((Idx < 0 && std::abs(Idx) <= KnownMinNumElements) ||
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(Idx >= 0 && Idx < KnownMinNumElements),
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"The splice index exceeds the range [-VL, VL-1] where VL is the "
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"known minimum number of elements in the vector. For scalable "
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"vectors the minimum number of elements is determined from "
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"vscale_range.",
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&VPI);
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break;
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}
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}
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}
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@ -10,7 +10,7 @@ declare <vscale x 16 x i1> @llvm.experimental.vp.splice.nxv16i1(<vscale x 16 x i
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declare <vscale x 32 x i1> @llvm.experimental.vp.splice.nxv32i1(<vscale x 32 x i1>, <vscale x 32 x i1>, i32, <vscale x 32 x i1>, i32, i32)
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declare <vscale x 64 x i1> @llvm.experimental.vp.splice.nxv64i1(<vscale x 64 x i1>, <vscale x 64 x i1>, i32, <vscale x 64 x i1>, i32, i32)
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define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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@ -22,19 +22,19 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1(<vscale x 1 x i1> %va, <vscale x
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
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; CHECK-NEXT: addi a0, a0, -5
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vslidedown.vi v9, v9, 5
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; CHECK-NEXT: vslidedown.vi v9, v9, 1
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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; CHECK-NEXT: vslideup.vx v9, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 1, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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ret <vscale x 1 x i1> %v
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}
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define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv1i1_negative_offset:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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@ -46,19 +46,19 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_negative_offset(<vscale x 1 x i1
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
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; CHECK-NEXT: addi a0, a0, -5
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; CHECK-NEXT: vsetivli zero, 5, e8, mf8, ta, ma
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; CHECK-NEXT: addi a0, a0, -2
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; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
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; CHECK-NEXT: vslidedown.vx v9, v9, a0
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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; CHECK-NEXT: vslideup.vi v9, v8, 5
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; CHECK-NEXT: vslideup.vi v9, v8, 2
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 -5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 -2, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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ret <vscale x 1 x i1> %v
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}
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define <vscale x 1 x i1> @test_vp_splice_nxv1i1_masked(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 1 x i1> @test_vp_splice_nxv1i1_masked(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv1i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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@ -70,20 +70,20 @@ define <vscale x 1 x i1> @test_vp_splice_nxv1i1_masked(<vscale x 1 x i1> %va, <v
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; CHECK-NEXT: vmv.v.i v11, 0
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; CHECK-NEXT: vmv1r.v v0, v10
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; CHECK-NEXT: vmerge.vim v10, v11, 1, v0
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; CHECK-NEXT: addi a0, a0, -5
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; CHECK-NEXT: addi a0, a0, -1
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vslidedown.vi v10, v10, 5, v0.t
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; CHECK-NEXT: vslidedown.vi v10, v10, 1, v0.t
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
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; CHECK-NEXT: vslideup.vx v10, v8, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
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; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 5, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
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%v = call <vscale x 1 x i1> @llvm.experimental.vp.splice.nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb, i32 1, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
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ret <vscale x 1 x i1> %v
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}
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define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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@ -95,19 +95,19 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1(<vscale x 2 x i1> %va, <vscale x
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
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; CHECK-NEXT: addi a0, a0, -5
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; CHECK-NEXT: addi a0, a0, -3
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; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
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; CHECK-NEXT: vslidedown.vi v9, v9, 5
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; CHECK-NEXT: vslidedown.vi v9, v9, 3
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vx v9, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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ret <vscale x 2 x i1> %v
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}
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define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv2i1_negative_offset:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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@ -119,19 +119,19 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_negative_offset(<vscale x 2 x i1
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v9, v10, 1, v0
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; CHECK-NEXT: addi a0, a0, -5
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; CHECK-NEXT: vsetivli zero, 5, e8, mf4, ta, ma
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; CHECK-NEXT: addi a0, a0, -4
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslidedown.vx v9, v9, a0
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v9, v8, 5
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; CHECK-NEXT: vslideup.vi v9, v8, 4
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; CHECK-NEXT: vmsne.vi v0, v9, 0
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 -4, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
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ret <vscale x 2 x i1> %v
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}
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define <vscale x 2 x i1> @test_vp_splice_nxv2i1_masked(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 2 x i1> @test_vp_splice_nxv2i1_masked(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv2i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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@ -143,20 +143,20 @@ define <vscale x 2 x i1> @test_vp_splice_nxv2i1_masked(<vscale x 2 x i1> %va, <v
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; CHECK-NEXT: vmv.v.i v11, 0
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; CHECK-NEXT: vmv1r.v v0, v10
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; CHECK-NEXT: vmerge.vim v10, v11, 1, v0
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; CHECK-NEXT: addi a0, a0, -5
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; CHECK-NEXT: addi a0, a0, -3
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
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; CHECK-NEXT: vslidedown.vi v10, v10, 5, v0.t
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; CHECK-NEXT: vslidedown.vi v10, v10, 3, v0.t
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
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; CHECK-NEXT: vslideup.vx v10, v8, a0, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
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; CHECK-NEXT: vmsne.vi v0, v10, 0, v0.t
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; CHECK-NEXT: ret
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%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
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%v = call <vscale x 2 x i1> @llvm.experimental.vp.splice.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
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ret <vscale x 2 x i1> %v
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}
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define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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@ -180,7 +180,7 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1(<vscale x 4 x i1> %va, <vscale x
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ret <vscale x 4 x i1> %v
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}
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define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv4i1_negative_offset:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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@ -204,7 +204,7 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_negative_offset(<vscale x 4 x i1
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ret <vscale x 4 x i1> %v
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}
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define <vscale x 4 x i1> @test_vp_splice_nxv4i1_masked(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 4 x i1> @test_vp_splice_nxv4i1_masked(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb, <vscale x 4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv4i1_masked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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@ -229,7 +229,7 @@ define <vscale x 4 x i1> @test_vp_splice_nxv4i1_masked(<vscale x 4 x i1> %va, <v
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ret <vscale x 4 x i1> %v
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}
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define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
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@ -253,7 +253,7 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1(<vscale x 8 x i1> %va, <vscale x
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ret <vscale x 8 x i1> %v
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}
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define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
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define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
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; CHECK-LABEL: test_vp_splice_nxv8i1_negative_offset:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
|
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@ -277,7 +277,7 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_negative_offset(<vscale x 8 x i1
|
||||
ret <vscale x 8 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @test_vp_splice_nxv8i1_masked(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 8 x i1> @test_vp_splice_nxv8i1_masked(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb, <vscale x 8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv8i1_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
|
||||
@ -302,7 +302,7 @@ define <vscale x 8 x i1> @test_vp_splice_nxv8i1_masked(<vscale x 8 x i1> %va, <v
|
||||
ret <vscale x 8 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv16i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
|
||||
@ -326,7 +326,7 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1(<vscale x 16 x i1> %va, <vscal
|
||||
ret <vscale x 16 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv16i1_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
|
||||
@ -350,7 +350,7 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_negative_offset(<vscale x 16 x
|
||||
ret <vscale x 16 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb, <vscale x 16 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv16i1_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
|
||||
@ -376,7 +376,7 @@ define <vscale x 16 x i1> @test_vp_splice_nxv16i1_masked(<vscale x 16 x i1> %va,
|
||||
ret <vscale x 16 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv32i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
|
||||
@ -400,7 +400,7 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1(<vscale x 32 x i1> %va, <vscal
|
||||
ret <vscale x 32 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv32i1_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
|
||||
@ -424,7 +424,7 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_negative_offset(<vscale x 32 x
|
||||
ret <vscale x 32 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va, <vscale x 32 x i1> %vb, <vscale x 32 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv32i1_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
|
||||
@ -450,7 +450,7 @@ define <vscale x 32 x i1> @test_vp_splice_nxv32i1_masked(<vscale x 32 x i1> %va,
|
||||
ret <vscale x 32 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv64i1:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
|
||||
@ -474,7 +474,7 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1(<vscale x 64 x i1> %va, <vscal
|
||||
ret <vscale x 64 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv64i1_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
|
||||
@ -498,7 +498,7 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_negative_offset(<vscale x 64 x
|
||||
ret <vscale x 64 x i1> %v
|
||||
}
|
||||
|
||||
define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, <vscale x 64 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv64i1_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
|
||||
@ -523,3 +523,5 @@ define <vscale x 64 x i1> @test_vp_splice_nxv64i1_masked(<vscale x 64 x i1> %va,
|
||||
%v = call <vscale x 64 x i1> @llvm.experimental.vp.splice.nxv64i1(<vscale x 64 x i1> %va, <vscale x 64 x i1> %vb, i32 5, <vscale x 64 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 64 x i1> %v
|
||||
}
|
||||
|
||||
attributes #0 = { vscale_range(2,0) }
|
||||
|
||||
@ -4,33 +4,33 @@
|
||||
; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v,+zfh,+zfbfmin,+zvfhmin,+zvfbfmin -verify-machineinstrs \
|
||||
; RUN: < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN
|
||||
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v10, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64_negative_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64_negative_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i64_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e64, m2, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetivli zero, 3, e64, m2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v10, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v10, 3
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64_zero_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64_zero_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i64_zero_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma
|
||||
@ -40,98 +40,98 @@ define <vscale x 2 x i64> @test_vp_splice_nxv2i64_zero_offset(<vscale x 2 x i64>
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64_masked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i64> @test_vp_splice_nxv2i64_masked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i64_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v10, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 1 x i64> @test_vp_splice_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 1 x i64> @test_vp_splice_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv1i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -1
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 1
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 1, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 1 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 1 x i64> @test_vp_splice_nxv1i64_negative_offset(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 1 x i64> @test_vp_splice_nxv1i64_negative_offset(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv1i64_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e64, m1, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -2
|
||||
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 2
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 -5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 -2, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 1 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 1 x i64> @test_vp_splice_nxv1i64_masked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 1 x i64> @test_vp_splice_nxv1i64_masked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv1i64_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -1
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 1, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 5, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 1, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 1 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_negative_offset(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_negative_offset(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i32_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e32, m1, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -4
|
||||
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 4
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 -4, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_masked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_masked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i32_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 4 x i16> @test_vp_splice_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 4 x i16> @test_vp_splice_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv4i16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
@ -144,7 +144,7 @@ define <vscale x 4 x i16> @test_vp_splice_nxv4i16(<vscale x 4 x i16> %va, <vscal
|
||||
ret <vscale x 4 x i16> %v
|
||||
}
|
||||
|
||||
define <vscale x 4 x i16> @test_vp_splice_nxv4i16_negative_offset(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 4 x i16> @test_vp_splice_nxv4i16_negative_offset(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv4i16_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
@ -157,7 +157,7 @@ define <vscale x 4 x i16> @test_vp_splice_nxv4i16_negative_offset(<vscale x 4 x
|
||||
ret <vscale x 4 x i16> %v
|
||||
}
|
||||
|
||||
define <vscale x 4 x i16> @test_vp_splice_nxv4i16_masked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 4 x i16> @test_vp_splice_nxv4i16_masked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv4i16_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
@ -170,7 +170,7 @@ define <vscale x 4 x i16> @test_vp_splice_nxv4i16_masked(<vscale x 4 x i16> %va,
|
||||
ret <vscale x 4 x i16> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i8> @test_vp_splice_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 8 x i8> @test_vp_splice_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv8i8:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
@ -183,7 +183,7 @@ define <vscale x 8 x i8> @test_vp_splice_nxv8i8(<vscale x 8 x i8> %va, <vscale x
|
||||
ret <vscale x 8 x i8> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i8> @test_vp_splice_nxv8i8_negative_offset(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 8 x i8> @test_vp_splice_nxv8i8_negative_offset(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv8i8_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
@ -196,7 +196,7 @@ define <vscale x 8 x i8> @test_vp_splice_nxv8i8_negative_offset(<vscale x 8 x i8
|
||||
ret <vscale x 8 x i8> %v
|
||||
}
|
||||
|
||||
define <vscale x 8 x i8> @test_vp_splice_nxv8i8_masked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 8 x i8> @test_vp_splice_nxv8i8_masked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv8i8_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
@ -209,85 +209,85 @@ define <vscale x 8 x i8> @test_vp_splice_nxv8i8_masked(<vscale x 8 x i8> %va, <v
|
||||
ret <vscale x 8 x i8> %v
|
||||
}
|
||||
|
||||
define <vscale x 1 x double> @test_vp_splice_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 1 x double> @test_vp_splice_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv1f64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -1
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 1
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 1, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 1 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 1 x double> @test_vp_splice_nxv1f64_negative_offset(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 1 x double> @test_vp_splice_nxv1f64_negative_offset(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv1f64_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e64, m1, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -2
|
||||
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 2
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 -5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 -2, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 1 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 1 x double> @test_vp_splice_nxv1f64_masked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 1 x double> @test_vp_splice_nxv1f64_masked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv1f64_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -1
|
||||
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 1, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 5, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 1, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 1 x double> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f32:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32_negative_offset(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32_negative_offset(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f32_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e32, m1, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 3
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f32_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i64> @test_vp_splice_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) nounwind {
|
||||
define <vscale x 16 x i64> @test_vp_splice_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv16i64:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: csrr a4, vlenb
|
||||
@ -355,7 +355,7 @@ define <vscale x 16 x i64> @test_vp_splice_nxv16i64(<vscale x 16 x i64> %va, <vs
|
||||
ret <vscale x 16 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 16 x i64> @test_vp_splice_nxv16i64_negative_offset(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) nounwind {
|
||||
define <vscale x 16 x i64> @test_vp_splice_nxv16i64_negative_offset(<vscale x 16 x i64> %va, <vscale x 16 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv16i64_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: csrr a5, vlenb
|
||||
@ -428,85 +428,85 @@ define <vscale x 16 x i64> @test_vp_splice_nxv16i64_negative_offset(<vscale x 16
|
||||
ret <vscale x 16 x i64> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3
|
||||
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16_negative_offset(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16_negative_offset(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f16_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 3
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16_masked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16_masked(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f16_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x half> @llvm.experimental.vp.splice.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2bf16:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3
|
||||
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x bfloat> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_negative_offset(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_negative_offset(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2bf16_negative_offset:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: vsetivli zero, 5, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetivli zero, 3, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vx v8, v8, a0
|
||||
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 5
|
||||
; CHECK-NEXT: vslideup.vi v8, v9, 3
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x bfloat> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_masked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_masked(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2bf16_masked:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: addi a0, a0, -5
|
||||
; CHECK-NEXT: addi a0, a0, -3
|
||||
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 5, v0.t
|
||||
; CHECK-NEXT: vslidedown.vi v8, v8, 3, v0.t
|
||||
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
|
||||
; CHECK-NEXT: vslideup.vx v8, v9, a0, v0.t
|
||||
; CHECK-NEXT: ret
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 3, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
|
||||
ret <vscale x 2 x bfloat> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i32_with_firstelt:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
@ -518,7 +518,7 @@ define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_firstelt(i32 %first, <vsc
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_splat_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
|
||||
define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_splat_firstelt(i32 %first, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2i32_with_splat_firstelt:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
|
||||
@ -531,7 +531,7 @@ define <vscale x 2 x i32> @test_vp_splice_nxv2i32_with_splat_firstelt(i32 %first
|
||||
ret <vscale x 2 x i32> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
|
||||
define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2f32_with_firstelt:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
|
||||
@ -543,7 +543,7 @@ define <vscale x 2 x float> @test_vp_splice_nxv2f32_with_firstelt(float %first,
|
||||
ret <vscale x 2 x float> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
|
||||
define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <vscale x 2 x half> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
|
||||
; ZVFH-LABEL: test_vp_splice_nxv2f16_with_firstelt:
|
||||
; ZVFH: # %bb.0:
|
||||
; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
|
||||
@ -563,7 +563,7 @@ define <vscale x 2 x half> @test_vp_splice_nxv2f16_with_firstelt(half %first, <v
|
||||
ret <vscale x 2 x half> %v
|
||||
}
|
||||
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %first, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) {
|
||||
define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %first, <vscale x 2 x bfloat> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evl) #0 {
|
||||
; CHECK-LABEL: test_vp_splice_nxv2bf16_with_firstelt:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: fmv.x.h a1, fa0
|
||||
@ -575,3 +575,5 @@ define <vscale x 2 x bfloat> @test_vp_splice_nxv2bf16_with_firstelt(bfloat %firs
|
||||
%v = call <vscale x 2 x bfloat> @llvm.experimental.vp.splice.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, i32 0, <vscale x 2 x i1> %mask, i32 1, i32 %evl)
|
||||
ret <vscale x 2 x bfloat> %v
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind vscale_range(2,0) }
|
||||
|
||||
@ -33,3 +33,36 @@ define void @test_vp_icmp(<4 x i32> %a, <4 x i32> %b, <4 x i1> %m, i32 %n) {
|
||||
%r1 = call <4 x i1> @llvm.vp.icmp.v4i32(<4 x i32> %a, <4 x i32> %b, metadata !"oeq", <4 x i1> %m, i32 %n)
|
||||
ret void
|
||||
}
|
||||
|
||||
; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector
|
||||
define <2 x double> @splice_v2f64_idx_neg3(<2 x double> %a, <2 x double> %b, i32 %evl1, i32 %evl2) #0 {
|
||||
%res = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -3, <2 x i1> splat (i1 1), i32 %evl1, i32 %evl2)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector
|
||||
define <vscale x 2 x double> @splice_nxv2f64_idx_neg3_vscale_min1(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 %evl1, i32 %evl2) #0 {
|
||||
%res = call <vscale x 2 x double> @llvm.experimental.vp.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -3, <vscale x 2 x i1> splat (i1 1), i32 %evl1, i32 %evl2)
|
||||
ret <vscale x 2 x double> %res
|
||||
}
|
||||
|
||||
; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector
|
||||
define <vscale x 2 x double> @splice_nxv2f64_idx_neg5_vscale_min2(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 %evl1, i32 %evl2) #1 {
|
||||
%res = call <vscale x 2 x double> @llvm.experimental.vp.splice.nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evl1, i32 %evl2)
|
||||
ret <vscale x 2 x double> %res
|
||||
}
|
||||
|
||||
; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector
|
||||
define <2 x double> @splice_v2f64_idx2(<2 x double> %a, <2 x double> %b, i32 %evl1, i32 %evl2) #0 {
|
||||
%res = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 2, <2 x i1> splat (i1 1), i32 %evl1, i32 %evl2)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector
|
||||
define <2 x double> @splice_v2f64_idx3(<2 x double> %a, <2 x double> %b, i32 %evl1, i32 %evl2) #1 {
|
||||
%res = call <2 x double> @llvm.experimental.vp.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 4, <2 x i1> splat (i1 1), i32 %evl1, i32 %evl2)
|
||||
ret <2 x double> %res
|
||||
}
|
||||
|
||||
attributes #0 = { vscale_range(1,16) }
|
||||
attributes #1 = { vscale_range(2,16) }
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user